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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -51
Q8200: FLI30336 (Video Processor, TORINO)
TERMINAL DESCRIPTION(9/10)
Frame Store DDR Interface
Pin name
FSDATA7
FSDATA6
FSDATA5
FSDATA4
FSDATA3
FSDATA2
FSDATA1
FSDATA0
FSDQM3
FSDQM2
FSDQM1
FSDQM0
FSBKSEL1
FSBKSEL0
FSADDR12
FSADDR11
FSADDR10
FSADDR9
FSADDR8
FSADDR7
FSADDR6
FSADDR5
FSADDR4
FSADDR3
FSADDR2
FSADDR1
FSADDR0
FSCS0
FSCS1
VDDA18_DLL
VSSA18_DLL
DDR2.5
Pin#
I/O
Description
A8
Data input/output. Synchronized with FSDQS0. SSTL2
I/O
B8
I/O
Data input/output. Synchronized with FSDQS0. SSTL2
A7
I/O
Data input/output. Synchronized with FSDQS0. SSTL2
B7
I/O
Data input/output. Synchronized with FSDQS0. SSTL2
A5
I/O
Data input/output. Synchronized with FSDQS0. SSTL2
B5
I/O
Data input/output. Synchronized with FSDQS0. SSTL2
A4
I/O
Data input/output. Synchronized with FSDQS0. SSTL2
B4
I/O
Data input/output. Synchronized with FSDQS0. SSTL2
B22
O
Data out mask. Only used during write cycles.
B17
O
Data out mask. Only used during write cycles.
A11
O
Data out mask. Only used during write cycles.
A6
O
Data out mask. Only used during write cycles.
C20
O
Bank select address.
C21
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C11
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C14
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
D16
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C12
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C6
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C7
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C8
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C10
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C13
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C15
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C16
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C17
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
C18
O
Bank select address. Row/column address outputs multiplexed on to the same pins.
D21
O
Chip select 0 pin(ball). SSTL2
C22
O
Chip select 1 pin(ball). SSTL2
A14
AP
1.8V power supply for on chip DLL for DDR interface timing control.
B14
AG
Power supply return for on chip DLL.
D4,D6,
P
2.5V power supply for DDR SSTL2 I/O's.
D7,D8,
D10,D11,
D12,D13,
D14,D15,
D17,D18,
D20,D22,
D23
TX-SR806/SA806
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