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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -58
Q8801: ADV7342 (Video Encoder)
BLOCK DIAGRAM
DGND (2)
GND_IO
VBI DATA SERVICE
INSERTION
VDD_IO
10-BIT
SD
4:2:2 TO 4:4:4
HD DDR
DEINTERLEAVE
VIDEO
DATA
R
G/B
20-BIT
ED/HD
ED/HD INPUT
DEINTERLEAVE
VIDEO
DATA
POWER
MANAGEMENT
CONTROL
PIN CONFIGURATION
SCL/
SDA/
V
(2)
MOSI
SCLK
DD
MPU PORT
PROGRAMMABLE
ADD
SYNC
RGB/YCrCb
TO
YUV
MATRIX
PROGRAMMABLE
ADD
CHROMINANCE
BURST
RGB
ASYNC
BYPASS
YCbCr
PROGRAMMABLE
HDTV FILTERS
HDTV
SHARPNESS AND
TEST
ADAPTIVE FILTER
PATTERN
CONTROL
GENERATOR
VIDEO TIMING GENERATOR
P_HSYNC P_VSYNC P_BLANK
S_HSYNC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V
1
DD_IO
PIN 1
TEST0
2
TEST1
3
Y0
4
Y1
5
Y2
6
Y3
7
Y4
8
Y5
9
V
10
DD
DGND
11
Y6
12
Y7
13
TEST2
14
TEST3
15
C0
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ALSB/
SFL/
SPI_SS
MISO
SUBCARRIER FREQUENCY
LOCK (SFL)
YUV
TO
LUMINANCE
YCrCb/
FILTER
RGB
SIN/COS DDS
BLOCK
FILTER
RGB
YCbCr
TO
RGB MATRIX
16x/4x OVERSAMPLING
DAC PLL
S_VSYNC
CLKIN (2) PV
DD
ADV7342
TOP VIEW
TX-SR806/SA806
AGND
V
AA
ADV7342/ADV7343
11-BIT
DAC 1
16×
FILTER
11-BIT
DAC 2
11-BIT
16×
DAC 3
FILTER
11-BIT
DAC 4
11-BIT
DAC 5
4×
FILTER
11-BIT
DAC 6
REFERENCE
AND CABLE
DETECT
PGND EXT_LF (2) V
COMP (2)
REF
48
SFL/MISO
47
R
SET1
46
V
REF
45
COMP1
DAC 1
44
43
DAC 2
42
DAC 3
V
41
AA
AGND
40
39
DAC 4
38
DAC 5
DAC 6
37
36
R
SET2
35
COMP2
34
PV
DD
33
EXT_LF1
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
R
(2)
SET
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