Onkyo TX-SA806 Service Manual page 116

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -59
Q8801: ADV7342 (Video Encoder)
TERMINAL DESCRIPTION
Pin No. Mnemonic
13, 12, Y7 to Y0
9 to 4
29 to 25, C7 to C0
18 to 16
62 to 58, S7 to S0
55 to 53
52, 51, 15, TEST5 to
14, 3, 2 TEST0
30 CLKIN_A
63 CLKIN_B
50 S_HSYNC
49 S_VSYNC
22 P_HSYNC
23 P_VSYNC
24 P_BLANK
48 SFL/MISO
47 R
SET1
36 R
SET2
45, 35 COMP1,
COMP2
44, 43, 42 DAC 1, DAC 2,
DAC 3
39, 38, 37 DAC 4, DAC 5,
DAC 6
21 SCL/MOSI
20 SDA/SCLK
19 ALSB/SPI_SS I
46 V
REF
41 V
AA
10, 56 V
DD
1 V
DD_IO
34 PV
DD
33 EXT_LF1
31 EXT_LF2
32 PGND
40 AGND
11, 57 DGND
64 GND_IO
ED = enhanced definition = 525p and 625p.
LSB = least significant bit. In the ADV7342, setting the LSB to 0 sets the I
LSB to 0 sets the I
2 C address to 0x54. Setting it to 1 sets the I
Input/
Output Description
I 8-Bit Pixel Port. Y0 is the LSB. Refer to Table 31 for input modes.
I 8-Bit Pixel Port. C0 is the LSB. Refer to Table 31 for input modes.
I 8-Bit Pixel Port. S0 is the LSB. Refer to Table 31 for input modes.
I Unused. These pins should be connected to DGND.
I Pixel Clock Input for HD Only (74.25 MHz), ED Only (27 MHz or 54 MHz) or SD Only (27 MHz).
I Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a
74.25 MHz reference clock for HD operation.
I/O SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
horizontal synchronization signal. See the External Horizontal and Vertical Synchronization
Control section.
I/O SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control
section.
I ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical
Synchronization Control section.
I ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization
Control section.
I ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.
I/O Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is
used to drive the color subcarrier DDS system, timing reset, or subcarrier reset.
I This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive
operation (for example, into a 37.5 ? load), a 510 ? resistor must be connected from R
AGND. For low drive operation (for example, into a 300 ? load), a 4.12 k? resistor must be
connected from R
SET1
I This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 k?
resistor must be connected from R
O Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to V
O DAC Outputs. Full and low drive capable DACs.
O DAC Outputs. Low drive only capable DACs.
I Multifunctional Pin: I
I/O Multifunctional Pin: I
Multifunctional Pin: This signal sets up the LSB of the MPU I
Optional External Voltage Reference Input for DACs or Voltage Reference Output.
P Analog Power Supply (3.3 V).
P Digital Power Supply (1.8 V). For dual-supply configurations, V
supplies through a ferrite bead or suitable filtering.
P Input/Output Digital Power Supply (3.3 V).
P PLL Power Supply (1.8 V). For dual-supply configurations, PV
supplies through a ferrite bead or suitable filtering.
I External Loop Filter for On-Chip PLL 1.
I External Loop Filter for On-Chip PLL 2.
G PLL Ground Pin.
G Analog Ground Pin.
G Digital Ground Pin.
G Input/Output Supply Ground Pin.
2 C address to 0xD4. Setting it to 1 sets the I
2 C address to 0x56.
to AGND.
to AGND.
SET2
2 C Clock Input/SPI Data Input.
C Data Input/Output. Also, SPI clock input.
2
TX-SR806/SA806
SET1
.
AA
2
C address. Also, SPI slave select.
can be connected to other 1.8 V
DD
can be connected to other 1.8 V
DD
2 C address to 0xD6. In the ADV7343, setting the
to