Channel Interleaving; Cs Sparing; Bank Swizzle Mode; Ecc Configuration - Silicon Graphics Rackable C2112-4G3 User Manual

7: BIOS

Channel Interleaving

CS Sparing

Bank Swizzle Mode

ECC Configuration

ECC Mode

DRAM ECC Enable

DRAM Timing Configuration

DRAM Timing Config

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This option enables channel memory interleaving. Options include Auto or Disabled.
This setting will reserve a spare memory rank in each node when enabled.
Options are Enabled and Disabled.
This setting Enables or Disables the bank swizzle mode.
This submenu sets the level of ECC protection. Options include Disabled, Basic, Good, Super,
Max and User. Selecting User activates the other options for user setting.
Note: The "Super" ECC mode dynamically sets the DRAM scrub rate so all of memory is
scrubbed in 8-hours.
This setting allows hardware to report and correct memory errors automatically, maintaining
system integrity. Options are Enabled or Disabled.
This setting specifies the DRAM timing configuration. Options are Auto and Manual.
007-5759-001