Chipset Features Setup; Chipset Setting - SOYO SY-7VBA133U User Manual

BIOS Setup Utility
After you have completed the changes, press [Esc] and follow the
instructions on your screen to save your settings or exit without saving.
The following table describes each field in the Advanced Chipset Features
Menu and how to configure each parameter.

3-4.1 CHIPSET FEATURES SETUP

CHIPSET
FEATURES
DRAM Timing
By SPD
DRAM Clock
SDRAM Cycle
Length
Bank Interleave
Memory Hole
P2C/C2P
Concurrency
Setting Description
Disable If enable the DRAM will auto
detect the DRAM timing.
Enabled
Host Clock
This item allows you to control
HCLK-33M
the DRAM speed.
HCLK+33M
2 When synchronous DRAM is
installed, the number of clock
3
cycles of CAS latency depends
on the DRAM timing. Do not
reset this field from the default
value specified by the system
designer.
4 Bank Increase DRAM performance.
Disabled
2 Bank
Disabled
Enabled Some interface cards will map
their ROM address to this area.
If this occurs, select [Enabled] in
this field.
Disabled This item allows you to
enable/disable the PCI to CPU,
Enabled
CPU to PCI concurrency
44
SY-7VBA133U
Note
Default
Default
Default
Default
Default
Default