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interrupts 4-8
introduction 1-1, 2-1, 3-1, 4-1, A-1
J
J1 2-2
J2 2-2
J3 4-10
J6 2-4
J7 2-4
J8 2-5
jumpers 2-1
L
LAN (see 82596CA and Ethernet) 4-6
LAN DMA transfers 4-9
LAN FIFO buffer 4-9
LAN transceiver 2-8
LCSR (Local Control and Status Regis-
ters) (see VMEchip2 LCSR) 2-2
LEDs 3-2
levels of implementation A-3
LFM (linear feet per minute) 1-3
linear feet per minute (LFM) 1-3
little endian mode 3-24
Local Area Network (see LAN) 4-6
local bus 4-8
local bus access 4-8
local bus memory map 3-3, 3-4
local bus timeout 4-8
local bus to DRAM cycle times 4-8
Local Control and Status Registers
(LCSR) (see VMEchip2 LCSR)
2-2
local I/O devices memory map 3-5
local reset (LRST) 3-1, 3-30
local reset operation 3-30
local resources 4-7
local SCSI ID 3-28
location monitors 2-8
longword 1-9
LRST (local reset) 3-1, 3-30
MVME167/D3
M
manual terminology 1-9
map decoders 3-29
MC68040 MPU 4-2
MCECC 1-5
MCECC internal register memory map
3-17
MEMC040 1-5
MEMC040 internal register memory map
3-17
memory maps 3-3
53C710 SCSI 3-24
82596CA Ethernet LAN 3-23
BBRAM configuration area 3-25
BBRAM, TOD Clock 3-26
Cirrus Logic CD2401 serial port 3-19
detailed I/O 3-6
interrupt acknowledge 3-28
local bus 3-3
local I/O devices 3-5
MCECC internal register 3-17
MEMC040 internal register 3-17
MK48T08 BBRAM, TOD Clock 3-25
PCCchip2 3-14
printer 3-16
TOD clock 3-26
VMEbus 3-29
VMEbus short I/O 3-29
VMEchip2 3-8
mezzanine module
ECC DRAM 4-13
parity DRAM 4-12
middle-of-the-road EIA-232-D configu-
ration A-4
minimum EIA-232-D connection A-5
MK48T08 (see Battery Backed Up RAM,
BBRAM, and NVRAM) 4-4
MK48T08 BBRAM,TOD Clock memory
map 3-25
model designations 1-1
modem(s) A-1
I
N
D
E
X
IN-3
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