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Functional Description
The DRAM map decoder can be programmed to accommodate different base
address(es) and sizes of mezzanine boards. The onboard DRAM is disabled by a local
bus reset and must be programmed before the DRAM can be accessed. Refer to the
MEMC040 or the MCECC in the MVME166/MVME167/MVME187 Single Board
Computers Programmer's Reference Guide for detailed programming information.
Most DRAM devices require some number of access cycles before the DRAMs are
fully operational. Normally this requirement is met by the onboard refresh circuitry
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and normal DRAM initialization. However, software should insure a minimum of 10
initialization cycles are performed to each bank of RAM.
Battery Backed Up RAM and Clock
The MK48T08 RAM and clock chip is used on the MVME167. This chip provides a
time of day clock, oscillator, crystal, power fail detection, memory write protection,
8KB of RAM, and a battery in one 28-pin package. The clock provides seconds,
minutes, hours, day, date, month, and year in BCD 24-hour format. Corrections for
28-, 29- (leap year), and 30-day months are automatically made. No interrupts are
generated by the clock. The MK48T08 is an 8 bit device; however, the interface
provided by the PCCchip2 supports 8-, 16-, and 32-bit accesses to the MK48T08.
Refer to the PCCchip2 in the MVME166/MVME167/MVME187 Single Board
Computers Programmer's Reference Guide and to the MK48T08 data sheet for
detailed programming information.
VMEbus Interface
The local bus to VMEbus interface, the VMEbus to local bus interface, and the
local-VMEbus DMA controller functions on the MVME167 are provided by the
VMEchip2. The VMEchip2 can also provide the VMEbus system controller functions.
Refer to the VMEchip2 in the MVME166/MVME167/MVME187 Single Board
Computers Programmer's Reference Guide for detailed programming information.
I/O Interfaces
The MVME167 provides onboard I/O for many system applications. The I/O functions
include serial ports, printer port, Ethernet transceiver interface, and SCSI mass storage
interface.
Serial Port Interface
The CD2401 serial controller chip (SCC) is used to implement the four serial ports.
The serial ports support the standard baud rates (110 to 38.4K baud). The four serial
ports are different functionally because of the limited number of pins on the P2 I/O
connector. Serial port 1 is a minimum function asynchronous port. It uses RXD, CTS,
TXD, and RTS. Serial ports 2 and 3 are full function asynchronous ports. They use
RXD, CTS, DCD, TXD, RTS, and DTR. Serial port 4 is a full function asynchronous
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MVME167 Single Board Computer User's Manual
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