MATSONIC MS8137C User Manual page 53

CPU & PCI Bus Control
Scroll to this item and press <Enter> to view the following
screen:
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
AGP & P2P Bridge Control
PCI1 Master 0 WS Write
PCI2 Master 0 WS Write
PCI1 Post Write
PCI2 Post Write
PCI Delay Transaction
: Move Enter : Select
F5:Previous Values
PCI 1/2 Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero
wait states, providing faster data transfer.
PCI 1/2 Post Write (Enabled)
When enabled, writes from the CPU to PCU bus are buffered,
to compensate for the speed differences between the CPU
and PCI bus. When disabled, the writes are not buffered and
the CPU must wait until the write is complete before starting
another write cycle.
PCI Delay Transaction (Disabled)
The mainboard's chipset has an embedded 32-bit post write
buffer to support delay transactions cycles. Select Enabled to
support compliance with PCI specification version 2.1.
Press <Esc> to return to the previous screen.
Memory Hole (Disabled)
This item is used to reserve memory space for ISA expansion
cards that require it.
System BIOS/Video RAM Cacheable (Enabled)
These items allow the video and system to be cached in
memory for faster execution. Leave these items at the default
value for better performance.
[Enabled]
[Enabled]
[Enabled]
Menu Level
[Enabled]
[Disabled]
+/-/PU/PD:Value: F10: Save ESC: Exit
F6:Fail-Safe Defaults F7:Optimized Defaults
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Item Help
F1:General Help