Motorola M68CPU32BUG User Manual page 184

Table C-1. CPU32Bug Customization Area (continued)
Offset Default Value
$90-95 $60FF0000E056
$96-9B $60FF0000DEE8 PWR_INI
$9C-A1 $60FF0000E070
$A2-A7 $60FF00000004
$A8-AD $60FF0000D8AA PWR_TST
$AE-B3 $60FF0000D4B4
$B4-B9 all $FF's
$BA-BF all $FF's
$C0-CF all $FF's
M68CPU32BUG REV 1
Mnemonic
Power On Branch Vectors (PWR_XXX)
PWR_TBL1 BRA.L to Initialization Table #1 routine. See INITTBL
below.
BRA.L to MCU (chip selects) initialization routine:
Exit: D7.L = power up status flags (bits 31-8)
Returns to PWR_TTL (no stack usage!).
PWR_TBL2 BRA.L to Initialization Table #2 routine. See INITTBL
below.
Exit: D7.L = preserved
PWR_TTL BRA.L to title printing routine:
Returns to PWR_TST (no stack usage!).
Exit: D7.L = preserved
BRA.L to self-test routine:
Exit: D7.B = error code
D7:31-8 = power up status flags
Returns to PWR_GO (no stack usage!).
PWR_GO BRA.L to CPU32Bug start up routine:
Entry: D7.B = 0 for no self-test errors, else it equals
the error code number (see Appendix B).
D7:31-8 = power up status flags
Never returns.
BRA.L <reserved>
BRA.L <reserved>
<reserved>
C-10
USER CUSTOMIZATION
Description