Motorola M68CPU32BUG User Manual page 180

Table C-1. CPU32Bug Customization Area (continued)
Offset Default Value
Common Chip Select Table: (Rev. A BCC + Rev. A PFB) &
$3C-3D $0E04
$3E-3F $68B0
$40-41 $0003
$42-43 $503E
$44-45 $0003
$46-47 $303E
$48-49 $0003
$4A-4B $683E
$4C-4D $0000
$4E-4F $0000
$50-51 $FFF8
$52-53 $680F
$54-55 $FFE8
$56-57 $783F
$58-59 $1004
$5A-5B $38F0
$5C-5D $1004
$5E-5F $58F0
$60-61 $0103
$62-63 $6870
$64-65 $0103
$66-67 $3030
$68-69 $0103
$6A-6B $5030
$6C-6D $020F
$6E-6F $DFFF
M68CPU32BUG REV 1
Mnemonic
(Rev. B BCC + Rev. B PFB)
.CSBARBT CSBOOT base address register value and
.CSORBT .
New Chip Select Table: (Rev. B BCC + Rev. B PFB)
.CSBAR0 CS0
.CSOR0 .
.CSBAR1 CS1
.CSOR1 .
.CSBAR2 CS2
.CSOR2 .
.CSBAR3 CS3
.CSOR3 .
.CSBAR4 CS4
.CSOR4 .
.CSBAR5 CS5
.CSOR5 .
.CSBAR6 CS6
.CSOR6 .
.CSBAR7 CS7
.CSOR7 .
.CSBAR8 CS8
.CSOR8 .
.CSBAR9 CS9
.CSOR9 .
.CSBAR10 CS10
.CSOR10 .
MCR_OR Value ORed with contents of MCR register at power-
on/reset.
MCR_AND Value ANDed with result value after MCR_OR and
stored back into MCR. If bit 6 (MM bit)of MCR_AND =
0, then module register block is placed at $7FF000.
Otherwise it is placed at $FFF000 (default).
Description
option register value
base address register value and
option register value
base address register value and
option register value
base address register value and
option register value
base address register value and
option register value
base address register value and
option register value
base address register value and
option register value
base address register value and
option register value
base address register value and
option register value
base address register value and
option register value
base address register value and
option register value
base address register value and
option register value
C-6
USER CUSTOMIZATION