Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 37

2. The BTS/PEBS absolute maximum is less than a record size from the end of the virtual
address space, and
3. The record that would cross the BTS/PEBS absolute maximum will also continue past the end
of the virtual address space,
a. BTS/PEBS record can be written that will wrap at the 4-Gbyte boundary (IA-32) or 2^64
boundary (Intel EM64T mode), and write memory outside of the BTS/PEBS buffer.
Software that uses BTS/PEBS near the 4-Gbyte boundary (IA-32) or 2^64 boundary (Intel EM64T
Implication:
mode), and defines the buffer such that it does not hold an integer multiple of records, can update
memory outside the BTS/PEBS buffer.
Define the BTS/PEBS buffer such that the BTS/PEBS absolute maximum minus the BTS/PEBS
Workaround:
buffer base is an integer multiple of the corresponding record sizes as recommended in the IA-32
IA-32 Intel
Status: For the steppings affected, see the Summary Table of Changes.
S72 L-bit of CS and LMA bit of IA32_EFER register may have erroneous value for
one instruction following mode transition in Hyper-Threading
Technology-Enabled processor supporting Intel
Technology (Intel
Problem: In an Intel EM64T-enabled processor, the L-bit of the Code Segment (CS) descriptor may not
update with the correct value in a processor with HT Technology. This may occur in a small
window when one logical processor is making a transition from a compatibility-mode to a 64-bit
mode (or vice versa) while the other logical processor is being stalled. A similar problem may
occur for the observation of the EFER.LMA bit by the decode logic.
Implication: The first instruction following a mode transition may be decoded as if it was still in the previous
mode. For example, this may result in an incorrect stack size used for a stack operation, i.e. a write
of only 4 bytes and an adjustment to ESP of only 4 in 64-bit mode. The problem can manifest itself
on any instruction which may behave differently in 64-bit mode than in compatibility mode.
It is possible for BIOS to contain a workaround for this erratum.
Workaround:
Status: For the steppings affected, see the Summary Table of Changes.
S73 The base of an LDT (Local Descriptor Table) register may be non-zero on a
processor supporting Intel
EM64T)
Problem: In IA-32e mode of an Intel EM64T-enabled processor, the base of an LDT register may be
non-zero.
Implication: Due to this erratum, Intel EM64T-enabled systems may encounter unexpected behavior when
accessing an LDT register using the null selector. There may be no #GP fault in response to this
access.
None identified.
Workaround:
For the steppings affected, see the Summary of Changes.
Status:
S74 Unaligned Page-Directory-Pointer (PDPTR) Base with 32-bit mode PAE
(Page Address Extension) paging may cause processor to hang
When the MOV to CR0, CR3 or CR4 instructions are executed in legacy PAE paging mode and
Problem:
software is using an unaligned PDPTR base the processor may hang or an incorrect page
translation may be used.
Implication: Software that is written according to Intel's alignment specification (32-byte aligned PDPTR Base)
will not encounter this erratum. Intel has not observed this erratum with commercially available
software. Systems may hang or experience unpredictable behavior when this erratum occurs.
® ®
64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
®
Architecture Software Developer's Manual, Volume 3.
®
EM64T)
®
®
Extended Memory 64 Technology (Intel
Extended Memory 64
®
Errata
37