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1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).
2.
The voltage specifications are assumed to be measured across V
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-M minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
Specified at 105 °C T
4.
Specified at the nominal V
5.
Measured at the bulk capacitors on the motherboard.
6.
V
tolerance shown in
CC,BOOT
7.
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal V
8.
This is a power-up peak current specification that is applicable when V
9.
This is a steady-state I
10.
Instantaneous current I
current will be less than maximum specified I
current levels described herein.
Figure 3.
Active V
V
CC-CORE
V
CC-CORE, DC
V
CC-CORE
V
CC-CORE, DC
V
CC-CORE
30
.
J
.
CC
Figure 7
and
Figure
. Not 100% tested.
CC
current specification that is applicable when both V
CC
of 57 A has to be sustained for short time (t
CC_CORE_INST
and I
Loadline for Pentium Processors
CC
CC
V
CC-CORE
Slope = -2.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
max {HFM|LFM}
max {HFM|LFM}
nom {HFM|LFM}
min {HFM|LFM}
min {HFM|LFM}
+/-V
CC-CORE
= VR St. Pt. Error 1/
0
Note 1 / V
C C - C O R E
T ol e ra n c e
V
C C - C O R E
-- - - -- - - -- - -- - - -- - - -- - - -- - -- - - -- - - -- - - -- - - -- - -- - - -- - - -- - - -- - - -- - -- - - -- -
+ / - 1. 5%
V
C C - C O R E
+ / - 11 .5 mV
0 . 50 00 V < /= V c c _ c o r e </ = 0. 75 00 0 V
CC_SENSE
8.
CCP
. VR OCP threshold should be high enough to support
CCDES
[V]
10mV= RIPPLE
Tolerance
S et P oi n t Er ro r T o l er a nce i s pe r b el o w :
V ID V ol t ag e R an ge
> 0 .7 50 0 V
Electrical Specifications
and V
pins at socket with
SS_SENSE
is high and V
is low.
CC_CORE
and V
are high.
CCP
CC_CORE
) of 35 µs. Average
INST
I
CC-CORE
[A]
I
max
CC-CORE
{HFM|LFM}
Datasheet
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