Intel BX80532PG3200D Datasheet page 64

Table 12. Signal Description (Sheet 6 of 8)
Name
PWRGOOD
REQ[4:0]#
RESET#
RS[2:0]#
RSVD
SLP#
SMI#
64
Package Mechanical Specifications and Pin Information
Type
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. 'Clean'
implies that the signal remains low (capable of sinking leakage
current), without glitches, from the time that the power supplies
Input
are turned on until they come within specification. The signal must
then transition monotonically to a high state.
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins
Input/ of both FSB agents. They are asserted by the current bus owner to
Output define the currently active transaction type. These signals are
source synchronous to ADSTB[0]#.
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at
least two milliseconds after V
proper specifications. On observing active RESET#, both FSB
Input
agents will deassert their outputs within two clocks. All processor
straps must be valid within the specified setup time before RESET#
is deasserted.
There is a 55  (nominal) on die pull-up resistor on this signal.
RS[2:0]# (Response Status) are driven by the response agent (the
Input agent responsible for completion of the current transaction), and
must connect the appropriate pins of both FSB agents.
Reserved/ These pins are RESERVED and must be left unconnected on the
No board. However, it is recommended that routing channels to these
Connect pins on the board be kept open for possible future use.
SLP# (Sleep), when asserted in Stop-Grant state, causes the
processor to enter the Sleep state. During Sleep state, the
processor stops providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating. Processors in this
state will not recognize snoops or interrupts. The processor will
recognize only assertion of the RESET# signal, deassertion of SLP#,
Input
and removal of the BCLK input while in Sleep state. If SLP# is
deasserted, the processor exits Sleep state and returns to Stop-
Grant state, restarting its internal clock signals to the bus and
processor core units. If DPSLP# is asserted while in the Sleep state,
the processor will exit the Sleep state and transition to the Deep
Sleep state.
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt, the
processor saves the current state and enters System Management
Mode (SMM). An SMI Acknowledge transaction is issued and the
Input
processor begins program execution from the SMM handler.
If an SMI# is asserted during the deassertion of RESET#, then the
processor will tristate its outputs.
Description
and BCLK have reached their
CC
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