Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specification page 9

Summary Tables of Changes
AK =
AL =
AM =
AN =
AO =
AP =
AQ =
AR =
AS =
AV =
AW =
AX =
AY=
AZ =
AAA =
AAB =
AAC =
AAD
=
AAE =
NO B1
AA1 X
AA2 X
AA3 X
AA4 X
AA5 X
AA6 X
AA7 X
AA8 X
AA9 X
Specification Update
Intel® Core™2 Extreme quad-core processor QX6000 sequence and
Intel® Core™2 Quad processor Q6000 sequence
Dual-Core Intel® Xeon® processor 7100 series
Intel® Celeron® processor 400 sequence
Intel® Pentium® dual-core processor
Quad-Core Intel® Xeon® processor 3200 series
Dual-Core Intel® Xeon® processor 3000 series
Intel® Pentium® dual-core desktop processor E2000 sequence
Intel® Celeron® processor 500 series
Intel® Xeon® processor 7200, 7300 series
Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad
processor Q9000 series
Intel® Core™ 2 Duo processor E8000 series
Quad-Core Intel® Xeon® processor 5400 series
Dual-Core Intel® Xeon® processor 5200 series
Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on
45-nm Process
Quad-Core Intel® Xeon® processor 3300 series
Dual-Core Intel® Xeon® E3110 Processor
Intel® Celeron® dual-core processor E1000 series
Intel® Core™2 Extreme Processor QX9775Δ
Intel® Atom™ processor Z5xx series
C1 D0 Plan ERRATA
Locks and SMC Detection May Cause the Processor to
X X No Fix
Temporarily Hang
Memory Aliasing of Pages as Uncacheable Memory Type and Write
X X No Fix
Back (WB) May Hang the System
Data Breakpoints on the High Half of a Floating Point Line Split
X X No Fix
may not be Captured
MOV CR3 Performs Incorrect Reserved Bit Checking When in
X X No Fix
PAE Paging
Plan VMEntry from 64-bit Host to 32-bit Guest may Cause IERR#
X X
Fix with Hyper-Threading Enabled
FXRSTOR May Not Restore Non-canonical Effective Addresses
X X No Fix on Processors with Intel
(Intel
X X No Fix A Push of ESP that Faults may Zero the Upper 32 Bits of RSP
Checking of Page Table Base Address May Not Match the
X X No Fix
Address Bit Width Supported by the Platform
With TF (Trap Flag) Asserted, FP Instruction That Triggers an
X X No Fix Unmasked FP Exception May Take Single Step Trap Before
Retirement of Instruction
®
Extended Memory 64 Technology
®
EM64T) Enabled
9