Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specification page 29

Errata
AA38. The Processor May Issue Front Side Bus Transactions up to 6 Clocks
after RESET# is Asserted
The processor may issue transactions beyond the documented 3 Front Side
Problem:
Bus (FSB) clocks and up to 6 FSB clocks after RESET# is asserted in the case
of a warm reset. A warm reset is where the chipset asserts RESET# when
the system is running.
Implication: The processor may issue transactions up to 6 FSB clocks after the RESET# is
asserted
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AA39. Front Side Bus Machine Checks May be Reported as a Result of On-
Going Transactions during Warm Reset
Processor Front Side Bus (FSB) protocol/signal integrity machine checks may
Problem:
be reported if the transactions are initiated or in-progress during a warm
reset. A warm reset is where the chipset asserts RESET# when the system is
running.
Implication: The processor may log FSB protocol/signal integrity machine checks if
transactions are allowed to occur during RESET# assertions.
Workaround: BIOS may clear FSB protocol/signal integrity machine checks for
systems/chipsets which do not block new transactions during RESET#
assertions.
For the steppings affected, see the Summary Tables of Changes
Status:
AA40. NMI-blocking Information Recorded in VMCS May be Incorrect after a
#GP on an IRET Instruction
In a system supporting Intel
Problem:
in the Interruption-Information Field in the guest VMCS may be set
incorrectly. This erratum will happen if a VMExit occurs for a #GP fault on an
IRET instruction due to an EIP that violates the segment limit or is non-
canonical.
Implication: If this erratum occurs, monitor software may not be able to handle #GP and
then inject an NMI since monitor software does not have information about
whether NMIs are blocked in the guest.
Workaround: Monitor software can workaround this bug by avoiding injection of NMI after
#GP emulation.
For the steppings affected, see the Summary Tables of Changes.
Status:
Specification Update
®
Virtualization Technology, the NMI blocking bit
29