Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specification page 24

AA23. Machine Check Exceptions May not Update Last-Exception Record
MSRs (LERs)
The Last-Exception Record MSRs (LERs) may not get updated when Machine
Problem:
Check Exceptions occur
Implication: When this erratum occurs, the LER may not contain information relating to
the machine check exception. They will contain information relating to the
exception prior to the machine check exception.
Workaround: None identified
For the steppings affected, see the Summary Tables of Changes.
Status:
AA24. VM Entry/Exit Writes to LSTAR/SYSCALL_FLAG MSR's May Cause
Incorrect Data to be Written to Bits [63:32]
Incorrect MSR data in bits [63:32] may be observed in the following two cases:
Problem:
1. When ECX contains 0xC0000084 and a VM entry/exit writes the
IA32_CR_LSTAR MSR (MSR Address 0xC0000082) bits [63:32] of the
data may be zeroed
2. When ECX does not contain 0xC0000084 and a VM entry/exit writes the
IA32_CR_SYSCALL_FLAG_MASK MSR (MSR Address 0xC0000084) bits
[63:32] of the data may not be zeroed
Implication: Bits [63:32] of the affected MSRs may contain the wrong data after a VM
exit/entry which loads the affected MSR.
Workaround: It is possible for the BIOS to contain a workaround for this erratum
For the steppings affected, see the Summary Tables of Changes.
Status:
AA25. Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
If a local interrupt is pending when the LVT entry is written, an interrupt may
Problem:
be taken on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT
entry is written, even if the new LVT entry has the mask bit set.
no Interrupt Service Routine (ISR) set up for that vector the system will GP
fault. If the ISR does not do an End of Interrupt (EOI) the bit for the vector
will be left set in the in-service register and mask all interrupts at the same
or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with
it, even if that vector was programmed as masked. This ISR routine must do
an EOI to clear any unexpected interrupts that may occur. The ISR
associated with the spurious vector does not generate an EOI, therefore the
spurious vector should not be used when writing the LVT.
For the steppings affected, see the Summary Tables of Changes.
Status:
24
Errata
If there is
Specification Update