Intel SL8K2 - Pentium 4 3.20EGHz 800MHz 1MB Socket 478 CPU Specification page 33

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• The Overflow Error bit (bit 62) in the IA32_MC0_STATUS register indicates, when set, that
a machine check error occurred while the results of a previous error were still in the error
reporting bank (i.e. The Valid bit was set when the new error occurred). If an uncorrectable
error is logged in the error-reporting bank and another error occurs, the overflow bit will not
be set.
• The MCA Error Code field of the IA32_MC0_STATUS register gets written by a different
mechanism than the rest of the register. For uncorrectable errors, the other fields in the
IA32_MC0_STATUS register are only updated by the first error. Any further errors that are
detected will update the MCA Error Code field without updating the rest of the register,
thereby leaving the IA32_MC0_STATUS register with stale information.
• When a speculative load operation hits the L2 cache and receives a correctable error, the
IA32_MC1_Status Register may be updated with incorrect information. The
IA32_MC1_Status Register should not be updated for speculative loads.
• The processor should only log the address for L1 parity errors in the IA32_MC1_Status
register if a valid address is available. If a valid address is not available, the Address Valid
bit in the IA32_MC1_Status register should not be set. In instances where an L1 parity error
occurs and the address is not available because the linear to physical address translation is not
complete or an internal resource conflict has occurred, the Address Valid bit is incorrectly
set.
• The processor may hang when an instruction code fetch receives a hard failure response from
the system bus. This occurs because the bus control logic does not return data to the core,
leaving the processor empty. IA32_MC0_STATUS MSR does indicate that a hard fail
response occurred.
• The processor may hang when the following events occur and the machine check exception
is enabled, CR4.MCE=1. A processor that has it's STPCLK# pin asserted will internally
enter the Stop Grant State and finally issue a Stop Grant Acknowledge special cycle to the
bus. If an uncorrectable error is generated during the Stop Grant process it is possible for the
Stop Grant special cycle to be issued to the bus before the processor vectors to the machine
check handler. Once the chipset receives its last Stop Grant special cycle it is allowed to
ignore any bus activity from the processors. As a result, processor accesses to the machine
check handler may not be acknowledged, resulting in a processor hang.
Implication: The processor is unable to correctly report and/or recover from certain errors.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
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Intel Pentium 4 Processor on 90 nm Process Specification Update
Errata
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