Intel SL8K2 - Pentium 4 3.20EGHz 800MHz 1MB Socket 478 CPU Specification page 10

Summary Tables of Changes
1 2
NO. C0 D0 LD0
R10 X X X
R11 X X X
R12 X X X
R13 X X X
R14 X X X
R15 X X X
R16 X X X
R17 X X X
R18 X
R19 X X X
R20 X
R21 X X X
R22 X X X
R23 X X X
10
2 1 2
E0 LE0 G1 LG1
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X
X X X X
® ®
Intel Pentium 4 Processor on 90 nm Process Specification Update
2 2
LN0 LR0 Plan
The Processor Signals Page-Fault
Exception (#PF) Instead of
No
X X Alignment Check Exception (#AC)
Fix
on an Unlocked CMPXCHG8B
Instruction
FSW May Not Be Completely
No
X X Restored after Page Fault on
Fix
FRSTOR or FLDENV Instructions
Processor Issues Inconsistent
No
X X Transaction Size Attributes for
Fix
Locked Operation
When the Processor Is in the
No System Management Mode (SMM),
X X
Fix Debug Registers May Be Fully
Writeable
Shutdown and IERR# May Result
No Due to a Machine Check Exception
X X
Fix on a Hyper-Threading Technology
Enabled Processor
Processor May Hang under Certain
No
X X Frequencies and 12.5% STPCLK#
Fix
Duty Cycle
System May Hang if a Fatal Cache
Error Causes Bus Write Line (BWL)
No Transaction to Occur to the Same
X X
Fix Cache Line Address as an
Outstanding Bus Read Line (BRL)
or Bus Read-Invalidate Line (BRIL}
A Write to an APIC Registers
No
X X Sometimes May Appear to Have
Fix
Not Occurred
Some Front Side Bus I/O
Fixed
Specifications are not Met
No Parity Error in the L1 Cache May
X X
Fix Cause the Processor to Hang
BPM4# Signal Not Being Asserted
Fixed
According to Specification
Sequence of Locked Operations
Can Cause Two Threads to
Fixed
Receive Stale Data and Cause
Application Hang
A 16-bit Address Wrap Resulting
from a Near Branch (Jump or Call)
Fixed May Cause an Incorrect Address to
be Reported to the #GP Exception
Handler
Bus Locks and SMC Detection May
No
X X Cause the Processor to Hang
Fix
Temporarily
R
ERRATA