J2: Serial Interface Pins - Texas Instruments DAC7716EVM User Manual

Digital Interface
3.1 Serial Data Interface
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a 10-pin, dual-row,
header/socket combination at J2. This header/socket provides access to the digital control and serial data
pins from both J2A (top side) and J2B (bottom side) of the connector. Consult Samtec at
http://www.samtec.com
Table 2 describes the serial interface pins.
Pin No.
J2.1
J2.2
J2.3 J2.5
J2.4
J2.6
J2.7 J2.9
J2.8
J2.10
J2.11
J2.12
J2.13
J2.14
J2.15
J2.16
J2.17
J2.18
J2.19
J2.20
(1)
Group A contains V
The SCLK signal and the CS signal can each be controlled by two different pins on J2. Pins J2.3 and J2.5
have been shorted together, as well as pins J2.7 and J2.9.
Pins J2.8, J2.12, J2.14, J2.15, and J2.17 have weak pull-up/pulldown resistors. These resistors provide
default settings for many of the control pins. J2.3, J2.5, J2.7, J2.9, J2.11 correspond directly to DAC7716
pins. See the DAC7716 product data sheet
Control signals to and from the DAC7716 can be accessed through the digital interface, or switches and
jumpers found directly on the EVM. The /LDAC, Uni/Bip A, Uni/Bip B, and RST signals are initially pulled
high through 10kΩ resistors and can be controlled by switch S1 or through J2.
The load DAC (LDAC) pin is connected via jumper JP1 to either the J2.15 or J2.17 pin. Updating the DAC
registers can be completed in two different ways. LDAC can either be tied to ground, in which case the
input registers are immediately updated, or LDAC can be pulled high. Therefore, the DAC registers update
when LDAC is taken low. Switch S1.1 can be closed to hold the LDAC low. See the DAC7716 data sheet
for more information on updating the DAC.
4
DAC7716EVM
or call 1-800-SAMTEC-9 for a variety of mating connector options.
Table 2. J2: Serial Interface Pins
Signal Name I/O Type
Unused —
GPIO-0 In/Out
SCLK In
DGND In/Out
GPIO-1 In/Out
CS In
Uni/Bip A In
DGND In/Out
SDO/SDI In/Out
Uni/Bip B In
Unused —
RST In
LDAC In
Unused —
LDAC In
DGND In/Out
Unused —
Unused —
-0 and V -1. Group B contains V
OUT OUT
for complete details on these pins.
Copyright © 2009, Texas Instruments Incorporated
(1)
Pullup Function
—
High GPIO-0
None DAC7716 SPI
clock; pins are
shorted together
None Digital ground
High GPIO-1
None SPI bus chip select;
pins are shorted
together
High Output mode select
of Group A
None Digital ground
None DAC7716 SPI data
in/out
High Output mode select
of Group B
—
High Input register reset
High GPIO signal to
control LDAC for
DAC output latch
update
—
High Alternate GPIO
signal to control
LDAC for DAC
output latch update
None Digital ground
—
—
-2 and V -3.
OUT OUT
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SBAU159 – October 2009