Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 4 REV 2.3 Manual page 63

CALL—Call Procedure (Continued)
#SS(0)
#SS(selector)
#NP(selector)
#TS(selector)
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#GP
Virtual 8086 Mode Exceptions
#GP(0)
#PF(fault-code)
#AC(0)
4:56
If pushing the return address, parameters, or stack segment pointer
onto the stack exceeds the bounds of the stack segment, when no
stack switch occurs.
If a memory operand effective address is outside the SS segment
limit.
If pushing the return address, parameters, or stack segment pointer
onto the stack exceeds the bounds of the stack segment, when a
stack switch occurs.
If the SS register is being loaded as part of a stack switch and the
segment pointed to is marked not present.
If stack segment does not have room for the return address,
parameters, or stack segment pointer, when stack switch occurs.
If a code segment, data segment, stack segment, call gate, task
gate, or TSS is not present.
If the new stack segment selector and ESP are beyond the end of
the TSS.
If the new stack segment selector is null.
If the RPL of the new stack segment selector in the TSS is not equal
to the DPL of the code segment being accessed.
If DPL of the stack segment descriptor for the new stack segment is
not equal to the DPL of the code segment descriptor.
If the new stack segment is not a writable data segment.
If segment-selector index for stack segment is outside descriptor
table limits.
If a page fault occurs.
If an unaligned memory access occurs when the CPL is 3 and
alignment checking is enabled.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the target offset is beyond the code segment limit.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the target offset is beyond the code segment limit.
If a page fault occurs.
If an unaligned memory access occurs when alignment checking is
enabled.
Volume 4: Base IA-32 Instruction Reference