Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 4 REV 2.3 Manual page 257

JMPE—Jump to Intel
Operation
IF(NOT Itanium System Environment) {
IF (PSR.cpl==0) Terminate_IA-32_System_Env();
ELSE IA_32_Exception(IllegalOpcode);
} ELSE IF(PSR.di==1) {
Disabled_Instruction_Set_Transition_Fault();
} ELSE IF(pending_numeric_exceptions()) {
IA_32_exception(FPError);
} ELSE {
IF(absolute_form) {
} ELSE IF(indirect_form) {
}
PSR.is = 0;
IP{3:0}= 0;
IP{63:32} = 0;
GR[1]{31:0} = EIP + AR[CSD].base;
GR[1]{63:32} = 0;
PSR.id = EFLAG.rf = 0;
IF (PSR.tb)
}
Flags Affected
None (other than EFLAG.rf)
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Fault.
Disabled ISA
IA_32_Exception
IA_32_Exception
IA-32 System Environment Exceptions (All Operating Modes)
#UD
4:250
® ®
Itanium Instruction Set (Continued)
IP{31:0} = disp16/32 + AR[CSD].base;//disp is 16/32-bit unsigned value
IP{31:0} = [r/m16/32] + AR[CSD].base;
IA_32_Exception(Debug);
Disabled Instruction Set Transition Fault, if PSR.di is 1
Floating-point Error, if any floating-point exceptions are pending
Taken Branch trap, if PSR.tb is 1.
JMPE raises an invalid opcode exception at privilege levels 1, 2 and
3. Privilege level 0 results in termination of the IA-32 System
Environment on a processor based on the Itanium architecture.
//compute virtual target
//set Itanium Instruction Set bit
//Force 16-byte alignment
//zero extend from 32-bits to 64-bits
//next sequential instruction address
//taken branch trap
Volume 4: Base IA-32 Instruction Reference