Infineon Technologies XC161CJ-16FF Errata Sheet

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__________________________________________________________

Device

Stepping Code/Marking

Package

This Errata Sheet describes the deviations from the current user documentation.

The module oriented classification and numbering system uses an ascending sequence over several

derivatives, including already solved deviations. So gaps inside this enumeration can occur.

This Errata Sheet applies to all temperature (SAB-/SAF-/SAK-.....) and frequency versions (.20./.40.),

unless explicitly noted otherwise.

Current Documentation

•

XC161 User's Manual V2.0, Volume 1: System Units - 2003-03

•

XC161 User's Manual V2.0, Volume 2: Peripheral Units - 2003-03

•

XC161CJ Data Sheet - V2.1, 2002-11

•

C166S V2 User's Manual (Core, Instruction Set) - V1.7, 2001-01

Note:

Devices additionally marked with EES- or ES- or E followed by a 3-digit date code are

engineering samples which may not be completely tested in all functional and electrical

characteristics, therefore they should be used for evaluation only.

The specific test conditions for EES and ES are documented in a separate Status Sheet.

Contents

Section

1. History List/Change Summary

2. Functional Problems

3. Deviations from Electrical- and Timing Specification

4. Application Hints

5. Documentation Update

Errata Sheet XC161CJ-16F20F/40F (ES-)AC

XC161CJ-16FF, -16F20F, -16F40F

ES-AC, AC

P-TQFP-144-19

- 1 of 30 –

Microcontrollers

Errata Sheet

V0.7, 2004-08-19

Mh/Es/UK, V0.7, 2004-08-19

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Summary of Contents for Infineon Technologies XC161CJ-16FF

Page 1 Microcontrollers Errata Sheet __________________________________________________________ V0.7, 2004-08-19 Device XC161CJ-16FF, -16F20F, -16F40F Stepping Code/Marking ES-AC, AC Package P-TQFP-144-19 This Errata Sheet describes the deviations from the current user documentation. The module oriented classification and numbering system uses an ascending sequence over several derivatives, including already solved deviations.
Page 2 1. History List/Change Summary from Errata Sheet Rev. 0.6 for XC161CJ-16F devices with marking ES-AC, AC to this Errata Sheet Rev. 0.7 for XC161CJ-16F devices with marking ES-AC, AC: Description of the following problems added: Frequency Limits for Flash Read Accesses (FCPUR_X.162832): see section “Deviations from DC/AC Specification”...
Page 3 1.1 Summary of Fixed Problems Problem Name Short Description Fixed in Step PORTS_X.001 Power Loss Operation EES-AA PORTS_X.003 PORT1 still active in Multiplexed Bus Modes EES-AA PORTS_X.004 P0H still active in 8-bit Non-multiplexed Bus Mode EES-AA PORTS_X.005 P3.5 increased leakage current for V >...
Page 4 1.2 Summary of Open Problems Problem Name Short Description Fixed in Step EBC_X.003 TwinCAN access with EBC enabled SDLM_X.001 Reset TXRQ - TXCPU CPU_X.002 Branch to wrong target after mispredicted JMPI ADC_X.003 Coincidence of Result Read and End of next Conversion or Start of Injected Conversion in Wait for Read Mode ADC_X.004 ADC Overrun Error Generation when result is read during last cycle...
Page 5 1.3 Summary of Application Hints Problem Name Short Description Remarks CPU_X.H1 Configuration of Registers CPUCON1 and CPUCON2 CPU_X.H2 Special Characteristics of I/O Areas steps ≥ AC FLASH_X.H1.1 Access to Flash Module after Program/Erase steps ≥ AC FLASH_X.H2.1 Access to Flash Module after Wake-Up from Sleep/Idle Mode or Shut-Down FLASH_X.H3.1 Read Access to internal Flash Module with modified Margin Level...
Page 6 2. Functional Problems EBC_X.003: TwinCAN Access with EBC enabled If the External Bus Controller (EBC) is enabled, a read or write access to the TwinCAN module fails when an external bus access with TCONCSx.PHA ≠ 00b precedes the TwinCAN access. Workaround: Since it is hard to predict the order of external bus and TwinCAN accesses (in particular when PEC transfers are involved), it is recommended to set bitfield PHA to '00' in all TCONCSx registers which...
Page 7 Effect on tools: In the Altium/Tasking compiler (v7.0 and above) the problem is not present. The result of a MUL/DIV instruction is available through the MDL/MDH SFRs. These SFRs are not allocatable by the register allocator. Therefore, the compiler always needs a MOV instruction to transfer MDL/H to a GPR. This avoids the problem.
Page 8 assign the highest priority to the PEC channel or interrupt service routine, and use local register banks and the interrupt jump table cache (fast interrupt) check for long ATOMIC or EXTEND sequences, or phases where the interrupt system is temporarily disabled (e.g. by an operating system) extend the ADC conversion time (bit fields ADCTC, ADSTC) Workaround 2.1 (for standard conversions if no injected conversions are used) Use an interrupt service routine to read the results of standard conversions from register DAT.
Page 9 Workaround 2.2 (for standard conversions if injected conversions are used in parallel) Use an interrupt service routine to read the results of standard conversions from register DAT. In the interrupt service routine, read the result register DAT twice. In case a lock situation had occurred, the second (dummy) read access will terminate the lock situation: the next conversion result #n+1 will be transferred to DAT, and interrupt request flag ADCIR will be set, such that the result #n+1 will be read correctly in the associated interrupt service routine.
Page 10 Workaround 3 In order to avoid the problem, make sure that only one conversion is started at a time. a) For standard conversions: Instead of continuous and auto scan conversion modes, use a sequence of fixed channel single conversions which are started in the ADC conversion complete interrupt service routine (triggered by ADCIR) after the result of the previous conversion has been read from register DAT.
Page 11 Workaround 1 In order to avoid the problem (when PLLCTRL ≠ 00b), make sure that the wake up trigger only occurs after the device has already entered sleep mode: check the RTC before entering sleep mode. If the wake up trigger will occur soon, either skip entry into sleep mode, or extend the time for the next wake up.
Page 12 TwinCAN2.005: Double Send Under the following conditions, the problem described below will occur: Message Object X (MO , lower priority) is in the process of actually being transmitted, and then the transmit request bit for Message Object Y (MO higher priority) is set via the user software. Other message objects MO may be pending for transmission, where the priorities are MO >...
Page 13 Simplified sample code: // Interrupt which takes place on a regular base interrupt (CC1_T0INT) void CC1_viTmr0(void) // Message Object Number ubObjNr; // for all message objects do (ubObjNr=0;ubObjNr<32;ubObjNr++) // if TxRQ is still set for MOX (CAN_HWOBJ[ubObjNr].uwMSGCTR & 0x2000) // reset TxRQ CAN_HWOBJ[ubObjNr].uwMSGCTR=0xDFFF;...
Page 14 TwinCAN2.007: Transmit after Error During a CAN error, transmission may stop (after EOF or an error frame), until a successful reception or a write access to the TwinCAN module. Detailed Description In case of a CAN error and there is no other activity on the CAN module (e.g. frame reception / frame transmission on the other CAN node / write access to any CAN register), the transmission of messages may stop, even if some transmit requests are still set.
Page 15 b1) 01b (VCO bypass with oscillator watchdog) if pin EA# is sampled low, and P0H.[7:5] = 000b or 011b, and ALE = low and RD# = high b2) 00b (VCO bypass without oscillator watchdog) if pin EA# is sampled low, and P0H.[7:5] = 000b or 011b, and both ALE and RD# are low b3) 11b (PLL mode) for all other combinations of P0H.[7:5] if pin EA# is sampled low Note that register SYSCON1 is only cleared after a hardware reset, therefore bit CPSYS remains at ‘1’...
Page 16 If this failure mode has been entered, write accesses to register PLLCON have no effect. Entry into sleep mode or further internal resets (SRST or WDT reset) will not change the settings of the clock system. Also, if an oscillator fail condition or PLL unlock event occurs in this mode, the clock system will remain unchanged.
Page 17 OCDS_X.002: OCDS indicates incorrect status after break_now requests if PSW.ILVL ≥ CMCTR.LEVEL When the OCDS processes a break_now request while the CPU priority level (in PSW.ILVL) is not lower than the OCDS break level (in CMCTR.LEVEL), the actual break is delayed until either PSW.ILVL or CMCTR.LEVEL is reprogrammed such that CMCTR.LEVEL >...
Page 18 3. Deviations from Electrical and Timing Specification Reference: XC161CJ Data Sheet - V2.1, 2002-11 (see also Status Sheet) The following restrictions should be considered: Symbol Parameter Value TAP_X.85 Maximum ambient temperature < 85°C (SAK version only) during flash programming FCPUR X.162832 Frequency Limits for Flash Read Accesses For instruction and data read accesses to the internal flash module (including programming and erase sequences), the frequency limits listed below must be considered, otherwise instructions and operands...
Page 19 The performance decrease due to an additional wait state depends on the individual characteristics of the software. Due to the internal instruction prefetch queue, the average performance decrease when using 1 wait state instead of 0 wait states is expected to be approximately 5%, and approximately 15% when using 2 wait states instead of 1 wait state.
Page 20 FLASH_X.H1.1 Access to Flash Module after Program/Erase After the last instruction of a program or erase command, the BUSY bit in register FSR is set to '1' (status = busy) after a delay of one instruction cycle. When polling the BUSY flag, one NOP or other instruction which is not evaluating the BUSY flag must be inserted after the last instruction of a program or erase command.
Page 21 If code is executed from the internal flash after wake-up, at least 16 instructions should be executed from the internal flash before re-entering sleep/idle mode. If code is executed from external memory or PRAM, wait until the flash BUSY bit returns to ‘0’ before re-entering sleep/idle mode.
Page 22 Note that in either case, the PLL is turned off during sleep mode, and does not contribute to any additional power consumption. IDLE_X.H1 Entering Idle Mode after Flash Program/Erase After a program/erase operation, idle mode should not be entered before the BUSY bit in register FSR has returned to '0' (status = not busy).
Page 23 The Watchdog Timer is stopped when a breakpoint is hit. Recommendation: The debugger (or application program) may stop/restart the on-chip peripherals by setting/clearing the corresponding disable bits in register SYSCON3. With an OCDS debugger, this may be achieved using the debug event action 'call a monitor', and executing an instruction sequence to modify SYSCON3 e.g.
Page 24 POWER_X.H1 Initialization of SYSCON3 for Power Saving Modes For minimum power consumption during power saving modes, all modules which are not required should be disabled in register SYSCON3, i.e. the corresponding disable bits should be set to '1', including bits which are marked as 'reserved' (this provides compatibility with future devices, since all SYSCON3 bits are disable bits).
Page 25 high byte low byte Write Access 1: 0x(00)(low byte) Write Access 2: 0x(high byte)(00) TxData1 TxData0 TxData3 TxData2 TxData5 TxData4 TxData7 TxData6 TxData9 TxData8 Data Figure 1: Scheme of writing to TxD0 Application code: Word Write: for (i=0; i<number_of_words; i++) SDLM_TxD0 = write_wordwise[i];...
Page 26 RxDATA00 first read RxDATA01 second read Figure 3: Reading RxD0 in FIFO mode Here again, the software application can handle the FIFO in two different ways: Application code: Read Words number_of_words=RxCNT; number_of_words=(number_of_words >> 1) + (number_of_words & 0x1) for (i=0; i<number_of_words; i++) read_wordwise[i] = SDLM_RxD00 | SDLM_RxD00;...
Page 27 Note: The result of injected conversions is directly written to ADC_DAT2. This register always contains the last (i.e. most up to date) result. If the previous result has not been read in the meantime, it is overwritten. Standard conversions, which may be performed alternating with injected conversions, are suspended if the temporary buffer is full (due to ADWR = 1).
Page 28 When using odd values (1..15) for PLLODIV, where PLLODIV = 15 (0Fh) is selected by hardware only during clock system emergency mode or reconfiguration, the duty cycle for signal CLKOUT is on its nominal value of 50% PLLODIV Duty 33.33 42.86 44.44 45.45...
Page 29 When the RTC module is not used and shall be disabled after a (power-on) hardware reset, the following steps are recommended: 1. reset the RTC by setting bit SYSCON0.15/RTCRST = 1 2. clear the RTC run bit by setting RTC_CON.0/RUN = 0 3.
Page 30 Notes: 1) There is no difference in the port output characteristics (driver strength, edge shape) between the 3 selections for medium driver mode (PDMyN = 010Xb, 0110b). The electrical characteristics are comparable to medium driver/sharp edge mode of the XC16x-16F step AB devices. 2) Currently, weak driver mode is selected for setting 0111b.

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Xc161cj-16f20f Xc161cj-16f40f