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DSP48E1 Slice
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Xilinx DSP48E1 Slice User Manual
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Contents
Table of Contents
Bookmarks
Table of Contents
Revision History
Table of Contents
Preface: about this Guide
Guide Contents
Additional Documentation Resources
Additional Support Resources
Chapter 1: Overview
DSP48E1 Slice Overview
Features Relative to Prior Generations
Device Resources
Design Recommendations
Stacked Silicon Interconnect
Chapter 2: DSP48E1 Description and Specifics
DSP48E1 Slice Features
Architectural Highlights of the 7 Series FPGA DSP48E1 Slice
DSP48E1 Tile and Interconnect
DSP48E1 Slice Primitive
Simplified DSP48E1 Slice Operation
DSP48E1 Slice Attributes
Input Ports
Output Ports
Embedded Functions
Single Instruction, Multiple Data (SIMD) Mode
Pattern Detect Logic
Chapter 3: DSP48E1 Design Considerations
Designing for Performance
Designing for Power
Adder Tree Versus Adder Cascade
Adder Tree
Adder Cascade
Connecting DSP48E1 Slices Across Columns
Time Multiplexing the DSP48E1 Slice
Miscellaneous Notes and Suggestions
DSP48E1 Design Resources
Pre-Adder Block Applications
Memory-Mapped I/O Register Application
Appendix A: CARRYOUT, CARRYCASCOUT, and MULTSIGNOUT
Carryout/Carrycascout
MULTSIGNOUT and CARRYCASCOUT
Summary
Adder/Subtracter-Only Operation
MACC Operation
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See also:
User Manual
7 Series DSP48E1 Slice
User Guide
UG479 (v1.10) March 27, 2018
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