Introduction; Terminology - Intel E3300 Datasheet

Introduction

1 Introduction
The Intel
microarchitecture. The Intel Enhanced Core™ microarchitecture combines the
performance of previous generation Desktop products with the power efficiencies of a
low-power microarchitecture to enable smaller, quieter systems. The Intel Celeron
processor E3000 series is a 64-bit processor that maintains compatibility with IA-32
software.
Note: In this document, the Intel
"the processor."
Note: In this document, unless otherwise specified, the Intel
series refers to the Intel
The processors use Flip-Chip Land Grid Array (FC-LGA8) package technology, and plugs
into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the
LGA775 socket.
The processors are based on 45 nm process technology. The processors feature the
®
Intel Advanced Smart Cache, a shared multi-core optimized cache that significantly
reduces latency to frequently used data. The processors feature an 800 MHz front side
bus (FSB) and 1 MB of L2 cache. The processors support all the existing Streaming
SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Supplemental
Streaming SIMD Extension 3 (SSSE3). The processors support several Advanced
Technologies: Execute Disable Bit, Intel
SpeedStep
The processor's front side bus (FSB) use a split-transaction, deferred reply protocol.
The FSB uses Source-Synchronous Transfer of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a "double-clocked" or 2X address bus. Working together, the
4X data bus and 2X address bus provide a data bus bandwidth of up to 8.5 GB/s.
Intel has enabled support components for the processor including heatsink, heatsink
retention mechanism, and socket. Manufacturability is a high priority; hence,
mechanical assembly may be completed from the top of the baseboard and should not
require any special tooling.
1.1

Terminology

A '#' symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the '#' symbol implies
that the signal is inverted. For example, D[3:0] = 'HLHL' refers to a hex 'A', and
D[3:0]# = 'LHLH' also refers to a hex 'A' (H= High logic level, L= Low logic level).
"Front Side Bus" refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.
Datasheet
® ®
Celeron processor E3000 series is based on the Enhanced Intel
®
Celeron
®
Celeron
®
Technology.
®
processor E3000 series may be referred to as
®
Celeron
®
processor E3500, E3400, E3300, and E3200.
®
64 architecture, and Enhanced Intel
®
Core™
®
processor E3000
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