Intel E3300 Datasheet page 67

Land Listing and Signal Descriptions
Table 24. Signal Description (Sheet 4 of 10)
Name
DEFER#
DPRSTP#
DPSLP#
DRDY#
DSTBN[3:0]#
DSTBP[3:0]#
FC0/BOOTSELECT
FCx
Datasheet
Type
DEFER# is asserted by an agent to indicate that a transaction
cannot be ensured in-order completion. Assertion of DEFER# is
Input normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins/lands
of all processor FSB agents.
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state. To
return to the Deep Sleep State, DPRSTP# must be de-asserted. Use
of the DPRSTP# pin, and corresponding low power state, requires
Input
chipset support and may not be available on all platforms.
NOTE: Some processors may not have the Deeper Sleep State
enabled, refer to the Specification Update for specific sku
and stepping guidance.
DPSLP#, when asserted on the platform, causes the processor to
transition from the Sleep State to the Deep Sleep state. To return
to the Sleep State, DPSLP# must be de-asserted. Use of the
DPSLP# pin, and corresponding low power state, requires chipset
Input
support and may not be available on all platforms.
NOTE: Some processors may not have the Deep Sleep State
enabled, refer to the Specification Update for specific
processor and stepping guidance.
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
Input/
clock data transfer, DRDY# may be de-asserted to insert idle
Output
clocks. This signal must connect the appropriate pins/lands of all
processor FSB agents.
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
D[15:0]#, DBI0#
Input/
Output
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
D[15:0]#, DBI0#
Input/
Output
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
FC0/BOOTSELECT is not used by the processor. When this land is
Other tied to V previous processors based on the Intel NetBurst
SS
microarchitecture should be disabled and prevented from booting.
FC signals are signals that are available for compatibility with other
Other
processors.
Description
Associated Strobe
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
Associated Strobe
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
®
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