Renesas R7F0C30 Series User Manual
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Renesas R7F0C30 Series User Manual

Renesas R7F0C30 Series User Manual

8-bit single-chip microcontrollers
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R7F0C30x, R7F0C31x
8
8-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
The sales of these products are limited for China and Hong Kong.
User's Manual: Hardware
Rev.1.20 Oct 2014

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Summary of Contents for Renesas R7F0C30 Series

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.

  • Page 3: Notes For Cmos Devices

    NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
  • Page 4 How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions of the R7F0C30x, R7F0C31x microcontrollers and design and develop application systems and programs for these devices. Purpose This manual is intended to give users an understanding of the functions described in the Organization below.
  • Page 5 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations:  (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ...
  • Page 6 Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Semiconductor Reliability Handbook R51ZZ0001E Note See the “Semiconductor Package Mount Manual” website (http://www.renesas.com/products/package/manual/index.jsp). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing.
  • Page 7 All trademarks and registered trademarks are the property of their respective owners. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. ® Caution: This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc.

  • Page 8: Table Of Contents

    CONTENTS CHAPTER 1 OUTLINE..........................1 1.1 Features............................1 1.2 List of Part Numbers ........................3 1.3 Pin Configuration (Top View) ......................4 1.3.1 16-pin products ..........................4 1.3.2 20-pin products ..........................5 1.4 Block Diagram ..........................6 1.4.1 16-pin products ..........................6 1.4.2 20-pin products ..........................
  • Page 9 3.4.5 Special function register (SFR) addressing ..................51 3.4.6 Register indirect addressing......................52 3.4.7 Based addressing..........................53 3.4.8 Based indexed addressing ......................54 3.4.9 Stack addressing..........................55 CHAPTER 4 PORT FUNCTIONS ......................56 4.1 Port Functions ..........................56 4.2 Port Configuration........................58 4.2.1 Port 2...............................
  • Page 10 6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input ......... 159 6.4.5 Free-running timer operation......................172 6.4.6 PPG output operation........................181 6.4.7 One-shot pulse output operation ....................185 6.4.8 Pulse width measurement operation ..................... 190 6.5 Special Use of TM00........................
  • Page 11 10.6 Cautions for A/D Converter ..................... 270 CHAPTER 11 OPERATIONAL AMPLIFIERS ..................274 11.1 Function of Operational Amplifier ..................274 11.2 Configuration of Operational Amplifier.................. 275 11.3 Registers Used in Operational Amplifier ................277 11.4 Operational Amplifier Operations................... 284 CHAPTER 12 COMPARATOR ......................285 12.1 Features of Comparator......................
  • Page 12 16.1 Register for Confirming Reset Source ................... 359 CHAPTER 17 POWER-ON-CLEAR CIRCUIT..................360 17.1 Functions of Power-on-Clear Circuit..................360 17.2 Configuration of Power-on-Clear Circuit ................361 17.3 Operation of Power-on-Clear Circuit ..................361 17.4 Cautions for Power-on-Clear Circuit ..................364 CHAPTER 18 LOW-VOLTAGE DETECTOR ..................
  • Page 13 22.1 Connecting QB-MINI2 to R7F0C30x, R7F0C31x ..............403 22.2 On-Chip Debug Security ID ..................... 406 22.3 Securing of User Resources ....................407 CHAPTER 23 INSTRUCTION SET....................... 408 23.1 Conventions Used in Operation List ..................408 23.1.1 Operand identifiers and specification methods................408 23.1.2 Description of operation column ....................

  • Page 14: Chapter 1 Outline

    R01UH0389EJ0120 R7F0C30x, R7F0C31x Rev.1.20 RENESAS MCU Oct 09, 2014 CHAPTER 1 OUTLINE 1.1 Features  78K0 CPU core  I/O ports, ROM and RAM capacities Item I/O ports Program Memory Data Memory (Internal (Flash Memory) High-Speed RAM) Products R7F0C30042ESP, R7F0C30642ESN...
  • Page 15 R7F0C30x, R7F0C31x CHAPTER 1 OUTLINE  Timer  16-bit timer/event counter … PPG output, capture input, external event counter input  8-bit timer H … PWM output, operable with low-speed internal oscillation clock  8-bit timer/event counter 5 … External event counter input ...

  • Page 16: List Of Part Numbers

    0C300, 0C303, 0C306, 0C309: 4 KB ROM 0C301, 0C304, 0C307, 0C310: 8 KB ROM 0C302, 0C305, 0C308, 0C311: 16 KB ROM Memory type F: Flash memory Renesas MCU Renesas semiconductor product Table 1-1. List of Ordering Part Numbers Package Package Style, Environmental Part Number Count...

  • Page 17: Pin Configuration (Top View)

    R7F0C30x, R7F0C31x CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 16-pin products Note P31/TxD0/<TO00>/CMPCOM Note P32/RxD0/<TI010>/CMPIN Note ANI0/P20/AMP0- RESET/P125/<TI000>/<INTP1> Note ANI1/P21/AMP0OUT Note P122/X2/EXCLK/TOOLD0 ANI2/P22/AMP0+ Note P121/X1/<TI000>/<INTP1>/TOOLC0 ANI5/P25/AMP1- Note ANI6/P26/AMP1OUT REGC Note ANI7/P27/AMP1+ P30/TOH1/TI51/INTP0 AMP0-, AMP0+, : Amplifier Input P20 to P22, P25 to P27 : Port 2 Note AMP1-, AMP1+...

  • Page 18: 20-Pin Products

    R7F0C30x, R7F0C31x CHAPTER 1 OUTLINE 1.3.2 20-pin products Note P31/TxD0/CMPCOM Note Note ANI0/P20/AMP0- P32/RxD0/CMPIN Note ANI1/P21/AMP0OUT P33/TI000/INTP1 Note Note P34/TO00/TI010/CMPOUT ANI2/P22/AMP0+ ANI3/P23 RESET/P125 P122/X2/EXCLK/TOOLD0 ANI4/P24 P121/X1/TOOLC0 Note P25/AMP1- Note P26/AMP1OUT REGC Note P27/AMP1+ P30/TOH1/TI51/INTP0 AMP0-, AMP0+, : Amplifier Input P20 to P27 : Port 2 Note AMP1-, AMP1+...

  • Page 19: Block Diagram

    R7F0C30x, R7F0C31x CHAPTER 1 OUTLINE 1.4 Block Diagram 1.4.1 16-pin products <TO00>/P31 <TI010>/P32 16-bit TIMER/ P20 to P22, PORT 2 <TI000>/P125 EVENT COUNTER 00 P25 to P27 <TI000>/P121 PORT 3 P30 to P32 TI51/P30 8-bit TIMER 51 P121, P122 PORT 12 P125 TOH1/P30 8-bit TIMER H1...

  • Page 20: 20-Pin Products

    R7F0C30x, R7F0C31x CHAPTER 1 OUTLINE 1.4.2 20-pin products TO00/TI010/P34 16-bit TIMER/ PORT 2 P20 to P27 EVENT COUNTER 00 TI000/P33 PORT 3 P30 to P34 TI51/P30 8-bit TIMER 51 P121, P122 PORT 12 P125 TOH1/P30 8-bit TIMER H1 INTERNAL LOW-SPEED OSCILLATOR 78K/0 FLASH...

  • Page 21: Outline Of Functions

    R7F0C30x, R7F0C31x CHAPTER 1 OUTLINE 1.5 Outline of Functions 1.5.1 16-pin products Item R7F0C3004, R7F0C3014, R7F0C3024, R7F0C3034, R7F0C3044, R7F0C3054, R7F0C3064 R7F0C3074 R7F0C3084 R7F0C3094 R7F0C3104 R7F0C3114 Internal Flash memory 4 KB 8 KB 16 KB 4 KB 8 KB 16 KB memory (self-programming supported )

  • Page 22: 20-Pin Products

    R7F0C30x, R7F0C31x CHAPTER 1 OUTLINE 1.5.2 20-pin products R7F0C3006, R7F0C3016, R7F0C3026, R7F0C3036, R7F0C3046, R7F0C3056, Item R7F0C3066 R7F0C3076 R7F0C3086 R7F0C3096 R7F0C3106 R7F0C3116 Internal Flash memory 4 KB 8 KB 16 KB 4 KB 8 KB 16 KB memory (self-programming supported ) High-Speed RAM 512 bytes 512 bytes...

  • Page 23: Chapter 2 Pin Functions

    R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are two types of pin I/O buffer power supplies: AV and V . The relationship between these power supplies and the pins is shown below. Table 2-1.
  • Page 24 R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS (2) Non-port functions: 16-pin products 1 (1/2) Function Name Function After Reset Alternate Function Note P20/AMP0 ANI0 Input A/D converter analog input Analog input Note P21/AMP0OUT ANI1 Note P22/AMP0+ ANI2 Note P25/AMP1 ANI5 Note P26/AMP1OUT ANI6 Note...
  • Page 25 R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS (2) Non-port functions: 16-pin products 1 (2/2) Function Name Function After Reset Alternate Function  Connecting resonator for main system clock Input port P121/<TI000>/ <INTP1>/TOOLC0 P122/EXCLK/TOOLD0 EXCLK Input External clock input for main system clock Input port P122/X2/TOOLD0 ...

  • Page 26: 20-Pin Products

    R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS 2.1.2 20-pin products (1) Port functions: 20-pin products Function Name Function After Reset Alternate Function Note ANI0/AMP0 Port 2. Analog input 8-bit I/O port. Note ANI1/AMP0OUT Input/output can be specified in 1-bit units. Note ANI2/AMP0+ ANI3 ANI4...
  • Page 27 R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS (2) Non-port functions: 20-pin products Function Name Function After Reset Alternate Function Note ANI0 Input A/D converter analog input Analog input P20/AMP0 Note P21/AMP0OUT ANI1 Note P22/AMP0+ ANI2 ANI3 ANI4 Note AMP0- Input Operational amplifier 0 input Analog input P20/ANI0 Note...

  • Page 28: Description Of Pin Functions

    R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions Remark The pins mounted depend on the product. Refer to 1.3 Pin Configuration (Top View) and 2.1 Pin Function List. 2.2.1 P20 to P27 (port 2) P20 to P27 function as an I/O port. These pins also function as pins for A/D converter analog input, and operational amplifier I/O.

  • Page 29: P30 To P34 (Port 3)

    R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS 2.2.2 P30 to P34 (port 3) P30 to P34 function as an I/O port. These pins also function as pins for external interrupt request input, timer I/O, and data I/O for serial interface, comparator output, comparator analog input, comparator common input. 16-pin products 20-pin products P30/TOH1/TI51/INTP0...

  • Page 30: P121, P122, P125 (Port 12)

    R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS (h) TxD0 This is a serial data output pin for serial interface UART0. CMPCOM This is a comparator common input pin. CMPIN This is a comparator input pin. (k) CMPOUT This is a comparator output pin. 2.2.3 P121, P122, P125 (port 12) P121 and P122 function as an I/O port.

  • Page 31: Av Ref , Vdd , Vss

    R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS (e) TOOLD0 This is a data I/O pin for flash memory programmer/on-chip debugger. (f) INTP1 This is external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.
  • Page 32 R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS (a) REGC This is a pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this  pin to V via a capacitor (0.47 to 1 F). However, when using the STOP mode that has been entered since ...

  • Page 33: Pin I/O Circuits And Recommended Connection Of Unused Pins

    R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Tables 2-2 and 2-3 show the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2.
  • Page 34 R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types (20-pin products) Pin Name I/O Circuit Type Recommended Connection of Unused Pins Note 3 ANI0/P20/AMP0- 11-P <Digital input setting> Independently connect to AV or V via a resistor. Note 3 ANI1/P21/AMP0OUT 11-S...
  • Page 35 R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 5-AH Type 11-G data pullup P-ch P-ch enable IN/OUT output N-ch disable data P-ch P-ch Comparator IN/OUT output N-ch N-ch disable (Threshold voltage) input enable input enable Type 5-BB Type 11-N data...
  • Page 36 R7F0C30x, R7F0C31x CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 11-P Type 37-H reset data P-ch data P-ch IN/OUT output N-ch disable output N-ch disable input P-ch enable Comparator reset N-ch data P-ch (Threshold voltage) output N-ch disable input enable...

  • Page 37: Chapter 3 Cpu Architecture

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the R7F0C30x, R7F0C31x can access a 64 KB memory space. Figures 3-1 to 3-3 show the memory maps. Caution Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value corresponding to each product as indicated below after release of reset.
  • Page 38 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (R7F0C300x, R7F0C303x, R7F0C306x, R7F0C309x) FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 512 × 8 bits FD00H 0FFFH FCFFH...
  • Page 39 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (R7F0C301x, R7F0C304x, R7F0C307x, R7F0C310x) FFFFH Special function registers 1FFFH (SFR) 1FFFH 256 × 8 bits Program area FF00H FEFFH General-purpose 108FH registers 108EH On-chip debug security 32 × 8 bits Note 1 FEE0H ID setting area...
  • Page 40 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (R7F0C302x, R7F0C305x, R7F0C308x, R7F0C311x) FFFFH 3FFFH Special function registers (SFR) 1FFFH 256 × 8 bits Program area FF00H FEFFH General-purpose 108FH registers 108EH On-chip debug security 32 × 8 bits FEE0H Note 1 ID setting area...

  • Page 41: Internal Program Memory Space

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory Address Value Block Number 0000H to 03FFH 0400H to 07FFH 0800H to 0BFFH 0C00H to 0FFFH...
  • Page 42 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area.

  • Page 43: Internal Data Memory Space

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space R7F0C30x, R7F0C31x incorporate the following RAMs. (1) Internal high-speed RAM Table 3-5. Internal High-Speed RAM Capacity Product Internal High-Speed RAM 512  8 bits (FD00H to FEFFH) R7F0C3004, R7F0C3034, R7F0C3006, R7F0C3036, R7F0C3064, R7F0C3094, R7F0C3066, R7F0C3096 512 ...

  • Page 44: Data Memory Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the R7F0C30x, R7F0C31x microcontrollers, based on operability and other considerations.
  • Page 45 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Correspondence Between Data Memory and Addressing (R7F0C301x, R7F0C304x, R7F0C307x, R7F0C310x) FFFFH Special function registers SFR addressing (SFR) 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose Register addressing registers 32 × 8 bits Short direct FEE0H addressing...
  • Page 46 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Correspondence Between Data Memory and Addressing (R7F0C302x, R7F0C305x, R7F0C308x, R7F0C311x) F F F F H Special function registers SFR addressing (SFR) 256 x 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose...

  • Page 47: Processor Registers

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The R7F0C30x, R7F0C31x incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
  • Page 48 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored.
  • Page 49 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H Register pair higher FEDFH FEDEH Register pair lower FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) FEE0H FEE0H FEDFH...
  • Page 50 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH...

  • Page 51: General-Purpose Registers

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general- purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).

  • Page 52: Special Function Registers (Sfrs)

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
  • Page 53 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (1/4) Address Symbol Bit No. Number of Bits After Manipulated Reset Simultaneously                FF00H ...
  • Page 54 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (2/4) Address Symbol Bit No. Number of Bits After Manipulated Reset Simultaneously <FLMD    FF2BH FPCTL PUP>    FF2CH PM12 PM122 PM121   ...
  • Page 55 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (3/4) Address Symbol Bit No. Number of Bits After Manipulated Reset Simultaneously <TMH TMMD TMMD <TOLE <TOE    FF70H TMHMD1 CKS12 CKS11 CKS10 E1> V1> N1> ...
  • Page 56 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (4/4) Address Symbol Bit No. Number of Bits After Manipulated Reset Simultaneously   Note 1  FFACH RESF WDTRF LVIRF FFADH       ...

  • Page 57: Instruction Address Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by contents of the program counter (PC) and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.

  • Page 58: Immediate Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
  • Page 59 R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.

  • Page 60: Register Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during...

  • Page 61: Register Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.

  • Page 62: Direct Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces. [Operand format] Identifier Description...

  • Page 63: Short Direct Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

  • Page 64: Special Function Register (Sfr) Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.

  • Page 65: Register Indirect Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all of the memory spaces.

  • Page 66: Based Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.

  • Page 67: Based Indexed Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.

  • Page 68: Stack Addressing

    R7F0C30x, R7F0C31x CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.

  • Page 69: Chapter 4 Port Functions

    R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: AV and V . The relationship between these power supplies and the pins is shown below. Table 4-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins Note...
  • Page 70 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (16-pin products) Function Name Function After Reset Alternate Function Note ANI0/AMP0 Port 2. Analog input 6-bit I/O port. Note ANI1/AMP0OUT Input/output can be specified in 1-bit units. Note ANI2/AMP0+ Note ANI5/AMP1 Note ANI6/AMP1OUT...

  • Page 71: Port Configuration

    R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-4. Port Configuration Item Configuration Port mode registers (PMxx): PM2, PM3, PM12 Control registers Port registers (Pxx): P2, P3, P12 Pull-up resistor option registers (PUxx): PU3, PU12 Reset pin mode register (RSTMASK) A/D port configuration register (ADPC) Port alternate switch control register (MUXSEL) (16-pin products only)

  • Page 72: Port 2

    R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 2 (1) 16-pin products 16-pin products Note P20/ANI0/AMP0- Note P21/ANI1/AMP0OUT Note P22/ANI2/AMP0+   Note P25/ANI5/AMP1- Note P26/ANI6/AMP1OUT Note P27/ANI7/AMP1+ Note R7F0C3034, R7F0C3044, R7F0C3054, R7F0C3094, R7F0C3104, and R7F0C3114 (products with operational amplifier) only Port 2 is an I/O port with an output latch.
  • Page 73 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Table 4-5. Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+, P25/ANI5/AMP1-, and P27/ANI7/AMP1+ Pins OPAMPmE bit ADS Register P20/ANI0/AMP0-, ADPC Register PM2 Register (m = 0, 1) (n = 0, 2, 5, 7) P22/ANI2/AMP0+, P25/ANI5/AMP1-, and P27/ANI7/AMP1+ Pins ...
  • Page 74 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-1. Block Diagram of P20 and P25 PORT Output latch Note P20/ANI0/AMP0- (P20 and P25) Note P25/ANI5/AMP1- PM20, PM25 A/D converter Note Operational amplifier (-) input Port register 2 PM2: Port mode register 2 Read signal WR: Write signal Note...
  • Page 75 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P21 and P25 PORT Output latch Note P21/ANI1/AMP0OUT (P21 and P26) Note P26/ANI6/AMP1OUT PM21, PM26 AMP0M Note AMPM Note OPAMP0E Note OPAMP1E Note Operational amplifier output A/D converter Port register 2 PM2: Port mode register 2 AMPM: Operational amplifier control register...
  • Page 76 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P22 and P27 PORT Output latch Note P22/ANI2/AMP0+ (P22 and P27) Note P27/ANI7/AMP1+ PM22, PM27 A/D converter Note Operational amplifier (+) input Port register 2 PM2: Port mode register 2 Read signal WR: Write signal Note...
  • Page 77 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS (2) 20-pin products 20-pin products Note P20/ANI0/AMP0- Note P21/ANI1/AMP0OUT Note P22/ANI2/AMP0+ P23/ANI3 P24/ANI4 Note P25/AMP1- Note P26/AMP1OUT Note P27/AMP1+ Note R7F0C3036, R7F0C3046, R7F0C3056, R7F0C3096, R7F0C3106, and R7F0C3116 (products with operational amplifier/comparator) only Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2).
  • Page 78 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Table 4-7. Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+ Pins ADS Register P20/ANI0/AMP0-, ADPC Register PM2 Register OPAMP0E bit (n = 0, 2) P22/ANI2/AMP0+ Pins  Digital I/O Input mode Selects ANIn. Setting prohibited selection Does not select ANIn. Digital input ...
  • Page 79 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Table 4-9. Setting Functions of P23/ANI3, P24/ANI4 Pins ADPC Register PM2 Register ADS Register(n = 3, 4) P23/ANI3, P24/ANI4 Pins Digital I/O Input mode Selects ANIn. Setting prohibited selection Does not select ANIn. Digital input Output mode Selects ANIn.
  • Page 80 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P20 PORT Output latch Note P20/ANI0/AMP0- (P20) PM20 A/D converter Note Operational amplifier (-) input Port register 2 PM2: Port mode register 2 Read signal WR: Write signal Note R7F0C3036, R7F0C3046, R7F0C3056, R7F0C3096, R7F0C3106, and R7F0C3116 (products with operational amplifier) only R01UH0389EJ0120 Rev.1.20...
  • Page 81 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P21 PORT Output latch Note P21/ANI1/AMP0OUT (P21) PM21 AMP0M Note AMPM Note OPAMP0E Note Operational amplifier output A/D converter Port register 2 PM2: Port mode register 2 AMPM: Operational amplifier control register Read signal WR: Write signal Note...
  • Page 82 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 PORT Output latch Note P22/ANI2/AMP0+ (P22) PM22 A/D converter Note Operational amplifier (+) input Port register 2 PM2: Port mode register 2 Read signal WR: Write signal Note R7F0C3036, R7F0C3046, R7F0C3056, R7F0C3096, R7F0C3106, and R7F0C3116 (products with operational amplifier) only R01UH0389EJ0120 Rev.1.20...
  • Page 83 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P23, P24 PORT Output latch P23/ANI3, (P23 and P24) P24/ANI4 PM23, PM24 A/D converter Port register 2 PM2: Port mode register 2 Read signal WR: Write signal R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 84 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P25 PORT Output latch Note P25/AMP1- (P25) PM25 Note Operational amplifier (-) input Port register 2 PM2: Port mode register 2 Read signal WR: Write signal Note R7F0C3036, R7F0C3046, R7F0C3056, R7F0C3096, R7F0C3106, and R7F0C3116 (products with operational amplifier) only R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 85 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P26 PORT Output latch Note P26/AMP1OUT (P26) PM26 AMP0M Note AMPM Note OPAMP1E Note Operational amplifier output Port register 2 PM2: Port mode register 2 AMPM: Operational amplifier control register Read signal WR: Write signal Note...
  • Page 86 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P27 PORT Output latch Note P27/AMP1+ (P27) PM27 Note Operational amplifier (+) input Port register 2 PM2: Port mode register 2 Read signal WR: Write signal Note R7F0C3036, R7F0C3046, R7F0C3056, R7F0C3096, R7F0C3106, and R7F0C3116 (products with operational amplifier) only R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...

  • Page 87: Port 3

    R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 3 16-pin products 20-pin products P30/TOH1/TI51/INTP0 P30/TOH1/TI51/INTP0 Note 1 Note 2 P31/TxD0/<TO00>/CMPCOM P31/TxD0/CMPCOM Note 1 Note 2 P32/RxD0/<TI010>/CMPIN P32/RxD0/CMPIN  P33/TI000/INTP1 Note 2  P34/TO00/TI010/CMPOUT Notes 1. R7F0C3034, R7F0C3044, R7F0C3054, R7F0C3094, R7F0C3104, and R7F0C3114 (products with operational amplifier/comparator) only R7F0C3036, R7F0C3046, R7F0C3056, R7F0C3096, R7F0C3106, and R7F0C3116 (products with operational amplifier/comparator) only...
  • Page 88 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P30 PU30 P-ch Alternate function PORT Output latch P30/TOH1/TI51/INTP0 (P30) PM30 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR: Write signal R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 89 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P31 (1/2) (1) 16-pin products PU31 P-ch PORT Output latch (P31) P31/TxD0/<TO00>/ Note CMPCOM PM31 Alternate function (16-Bit timer/event counter 00) TO00SEL1 MUXSEL Alternate function (UART0) Note Comparator common input Port register 3 PU3: Pull-up resistor option register 3...
  • Page 90 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P31 (2/2) (2) 20-pin products PU31 P-ch PORT Output latch Note (P31) P31/TxD0/CMPCOM PM31 Alternate function Note Comparator common input Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal...
  • Page 91 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P32 (1/2) (1) 16-pin products PU32 P-ch Alternate function (UART0) MUXSEL TI010SEL1 Alternate function (16-Bit timer/event counter 00) PORT Output latch P32/RxD0/ (P32) Note <TI010>/CMPIN PM32 Note Comparator input Port register 3 PU3: Pull-up resistor option register 3...
  • Page 92 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P32 (2/2) (2) 20-pin products PU32 P-ch Alternate function PORT Output latch Note P32/RxD0/CMPIN (P32) PM32 Note Comparator input Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR: Write signal...
  • Page 93 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P33 PU33 P-ch Alternate function PORT Output latch P33/TI000/INTP1 (P33) PM33 Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR: Write signal R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 94 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P34 PU34 P-ch Alternate function PORT Output latch Note P34/TI010/TO00/CMPOUT (P34) PM34 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR: Write signal Note R7F0C3036, R7F0C3046, R7F0C3056, R7F0C3096, R7F0C3106, and R7F0C3116 (products with...

  • Page 95: Port 12

    R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 12 16-pin products 20-pin products P121/X1/<TI000>/<INTP1>/TOOLC0 P121/X1/TOOLC0 P122/X2/EXCLK/TOOLD0 P122/X2/EXCLK/TOOLD0 P125/<TI000>/<INTP1>/RESET P125/RESET Remark Functions in angle brackets < > can be assigned by setting the input switch control register (MUXSEL). P121, P122 function as an I/O port with an output latch. P125 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12).
  • Page 96 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P121, P122 (1/2) (1) 16-pin products OSCCTL OSCSEL PORT Output latch P122/X2/EXCLK/TOOLD0 (P122) PM12 PM122 OSCCTL OSCSEL OSCCTL EXCLK, OSCSEL MUXSEL INTP1SEL1 INTP1SEL0 TM00SEL1 TM00SEL0 Alternate function PORT Output latch (P121) P121/X1/<TI000>/ <INTP1>/TOOLC0...
  • Page 97 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P121, P122 (2/2) (2) 20-pin products OSCCTL OSCSEL PORT Output latch P122/X2/EXCLK/TOOLD0 (P122) PM12 PM122 OSCCTL OSCSEL OSCCTL EXCLK, OSCSEL PORT Output latch (P121) P121/X1/TOOLC0 PM12 PM121 OSCCTL OSCSEL P12: Port register 12 PU12:...
  • Page 98 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P125 (1/2) (1) 16-pin products PU12 PU125 P-ch MUXSEL INTP1SEL1 INTP1SEL0 TM00SEL1 TM00SEL0 Alternate function P125/<TI000>/ <INTP1>/RESET Internal reset RSTMASK RSTM PU12: Pull-up resistor option register 12 RSTMASK: Reset pin mode register MUXSEL: Port alternate switch control register Read signal...
  • Page 99 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P125 (2/2) (2) 20-pin products PU12 PU125 P-ch P125/RESET Internal reset RSTMASK RSTM PU12: Pull-up resistor option register 12 RSTMASK: Reset pin mode register Read signal WR: Write signal Caution Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset signal is generated during low level input, the reset status continues until the input rises to the high...

  • Page 100: Registers Controlling Port Function

    R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following six types of registers.  Port mode registers (PMxx)  Port registers (Pxx)  Pull-up resistor option registers (PUxx)  Reset pin mode register (RSTMASK) ...
  • Page 101 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Figure 4-18. Format of Port Mode Register (16-pin products) Symbol Address After reset Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 PM27 PM26 PM25 PM22 PM21 PM20 FF22H <R> Note 2 Note 2 PM32 PM31...
  • Page 102 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS (2) Port registers (Pxx) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is read.
  • Page 103 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
  • Page 104 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS (4) Reset pin mode register (RSTMASK) This register sets the pin function of RESET/P125 (external reset input/input-dedicated port). This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 4-24.
  • Page 105 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS (5) A/D port configuration register (ADPC) ADPC switches the P20/AMP0-/ANI0 to P24/ANI4 (if the 16-pin products, P20/AMP0-/ANI0 to P22/AMP0+/ANI2, P25/AMP1-/ANI5 to P27/AMP1+/ANI7) pins to digital I/O or analog I/O of port. Each bit of ADPC corresponds to a pin of port 2 and can be specified in 1-bit units.
  • Page 106 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS (6) Port alternate switch control register (MUXSEL) (16-pin products only) This register assigns the pin function. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears MUXSEL to 00H. Figure 4-27.

  • Page 107: Port Function Operations

    R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again.

  • Page 108: Settings Of Port Mode Register And Output Latch When Using Alternate Function

    R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 4-12, 4-13. Table 4-12.
  • Page 109 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Table 4-12. Settings of Port Mode Register and Output Latch When Using Alternate Function (16-pin products) (2/2) Pin Name Alternate Function PM P Function Name    Note 1 P121  <TI000> Input ...
  • Page 110 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Table 4-13. Settings of Port Mode Register and Output Latch When Using Alternate Function (20-pin prodcts) (1/2) Pin Name Alternate Function PM P Function Name  Note 1 ANI0 Input  Notes 1, 2 AMP0- Input ...
  • Page 111 R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS Table 4-13. Settings of Port Mode Register and Output Latch When Using Alternate Function (20-pin products) (2/2) Pin Name Alternate Function PM P Function Name    Note 1 P121   TOOLC0 Input ...

  • Page 112: Cautions On 1-Bit Manipulation Instruction For Port Register N (Pn)

    R7F0C30x, R7F0C31x CHAPTER 4 PORT FUNCTIONS 4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.

  • Page 113: Chapter 5 Clock Generator

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1>...

  • Page 114: Configuration Of Clock Generator

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode select register (OSCCTL) Processor clock control register (PCC) Internal oscillation mode register (RCM) Main OSC control register (MOC) Main clock mode register (MCM) Oscillation stabilization time counter status register (OSTC)
  • Page 115 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...

  • Page 116: Registers Controlling Clock Generator

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR Remark f X1 clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency EXCLK High-speed system clock frequency Main system clock frequency Peripheral hardware clock frequency CPU clock frequency Internal low-speed oscillation clock frequency 5.3 Registers Controlling Clock Generator The following seven registers are used to control the clock generator.
  • Page 117 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR (1) Clock operation mode select register (OSCCTL) This register selects the operation modes of the high-speed system clock. OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-2.
  • Page 118 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR (2) Processor clock control register (PCC) This register is used to select the CPU clock and the division ratio. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC to 01H. Figure 5-3.
  • Page 119 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR (3) Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation sets this register to 80H Figure 5-4.
  • Page 120 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock.
  • Page 121 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR (5) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
  • Page 122 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked.
  • Page 123 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR (7) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.

  • Page 124: System Clock Oscillator

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 10 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. Figure 5-9 shows an example of the external circuit of the X1 oscillator.
  • Page 125 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR Figure 5-10. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...

  • Page 126: Internal High-Speed Oscillator

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR Figure 5-10. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched 5.4.2 Internal high-speed oscillator The internal high-speed oscillator is incorporated in the R7F0C30x, R7F0C31x. Oscillation can be controlled by the internal oscillation mode register (RCM). After a reset release, the internal high-speed oscillator automatically starts oscillation.

  • Page 127: Clock Generator Operation

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (refer to Figure 5-1).  Main system clock f  High-speed system clock f X1 clock f External main system clock f EXCLK...
  • Page 128 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR Figure 5-11. Clock Generator Operation When Power Supply Voltage Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte: LVISTART = 0)) Power supply 1.8 V voltage (V 1.59 V (TYP.) 0.5 V/ms (MIN.) Internal reset signal...
  • Page 129 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage reaches 1.8 V, or set the LVI default start function enabled by using the option byte (LVISTART = 1) (refer to Figure 5-12).

  • Page 130: Controlling Clock

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR Note When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high- speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC).
  • Page 131 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR (1) Example of setting procedure when oscillating the X1 clock <1> Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register) When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is switched from port mode to X1 oscillation mode.
  • Page 132 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware...

  • Page 133: Example Of Controlling Internal High-Speed Oscillation Clock

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock. When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the CPU clock to a clock other than the high-speed system clock.
  • Page 134 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock <1>  Restarting oscillation of the internal high-speed oscillation clock Note (Refer to 5.6.2 (1) Example of setting procedure when restarting oscillation of the internal high- speed oscillation clock).
  • Page 135 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR (3) Example of setting procedure when stopping the internal high-speed oscillation clock The internal high-speed oscillation clock can be stopped in the following two ways.  Executing the STOP instruction to set the STOP mode ...

  • Page 136: Example Of Controlling Internal Low-Speed Oscillation Clock

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock.  Watchdog timer  8-bit timer H1 (if f is selected as the count clock) In addition, the following operation modes can be selected by the option byte.

  • Page 137: Clocks Supplied To Cpu And Peripheral Hardware

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR 5.6.4 Clocks supplied to CPU and peripheral hardware The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting of registers. Table 5-3. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting Supplied Clock XSEL MCM0...

  • Page 138: Cpu Clock Status Transition Diagram

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR 5.6.5 CPU clock status transition diagram Figure 5-13 shows the CPU clock status transition diagram of this product. Figure 5-13. CPU Clock Status Transition Diagram (When LVI Default Start Mode Function Stopped Is Set (Option Byte: LVISTART = 0)) Internal low-speed oscillation: Woken up Power ON...
  • Page 139 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/2) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition SFR Register Setting (A) ...
  • Page 140 R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/2) (4) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0...

  • Page 141: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR 5.6.6 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-5. Changing CPU Clock CPU Clock Condition Before Change Processing After Change Before Change...

  • Page 142: Time Required For Switchover Of Main System Clock

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR 5.6.7 Time required for switchover of main system clock By setting bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC), the division ratio of the main system clock can be changed. The actual switchover operation is not performed immediately after rewriting to PCC;...

  • Page 143: Conditions Before Clock Oscillation Is Stopped

    R7F0C30x, R7F0C31x CHAPTER 5 CLOCK GENERATOR 5.6.8 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 5-8. Conditions Before the Clock Oscillation Is Stopped and Flag Settings Clock Conditions Before Clock Oscillation Is Stopped Flag Settings of SFR...

  • Page 144: Chapter 6 16-Bit Timer/Event Counter 00

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 is mounted onto all R7F0C30x, R7F0C31x products. 16-bit timer/event counter 00 has the following functions. Caution In 16-pin products, the timer I/O pins are available only when the TI000, TI010, and TO00 functions are specified by using the MUXSEL register.

  • Page 145: Configuration Of 16-Bit Timer/Event Counter 00

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 includes the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration Time/counter 16-bit timer counter 00 (TM00) Register 16-bit timer capture/compare registers 000, 010 (CR000, CR010) Timer input TI000, TI010...
  • Page 146 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00 (1) 16-pin products Internal bus Capture/compare control register 00 (CRC00) CRC002CRC001 CRC000 To CR010 INTTM000 Noise 16-bit timer capture/compare <TI010>/P32/ elimi- register 000 (CR000) Note RxD0/CMPIN nator...
  • Page 147 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) 20-pin products Internal bus Capture/compare control register 00 (CRC00) CRC002CRC001 CRC000 To CR010 INTTM000 Noise 16-bit timer capture/compare elimi- TI010/TO00/P34/ register 000 (CR000) Note nator CMPOUT Match 16-bit timer counter 00 Clear TO00 output (TM00)
  • Page 148 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00) Address: FF10H, FF11H After reset: 0000H FF11H...
  • Page 149 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) 16-bit timer capture/compare register 000 (CR000), 16-bit timer capture/compare register 010 (CR010) CR000 and CR010 are 16-bit registers that are used with a capture function or comparison function selected by using CRC00.
  • Page 150 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010) Address: FF14H, FF15H After reset: 0000H FF15H FF14H CR010 (i) When CR010 is used as a compare register The value set in CR010 is constantly compared with the TM00 count value, and an interrupt request signal (INTTM010) is generated if they match.
  • Page 151 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Timer counter clear TM00 register Compare register set value (0000H) Operation Operation enabled Timer operation enable bit disabled (00) (other than 00) (TMC003, TMC002) Interrupt request signal Interrupt signal Interrupt signal is not generated is generated Remarks 1.
  • Page 152 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. Capture Operation of CR000 and CR010 External Input Signal TI000 Pin Input TI010 Pin Input Capture Operation Capture operation of CRC001 = 1 Set values of ES010 and CRC001 bit = 0 Set values of ES110 and CR000 TI000 pin input...

  • Page 153: Registers Controlling 16-Bit Timer/Event Counter 00

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 Registers used to control 16-bit timer/event counter 00 are shown below.  16-bit timer mode control register 00 (TMC00)  Capture/compare control register 00 (CRC00) ...
  • Page 154 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FF86H After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 Operation enable of 16-bit timer/event counter 00 Disables 16-bit timer/event counter 00 operation.
  • Page 155 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00) Address: FF88H After reset: 00H Symbol CRC00 CRC002 CRC001 CRC000 CRC002 CR010 operating mode selection Operates as compare register Operates as capture register CRC001 CR000 capture trigger selection Captures on valid edge of TI010 pin...
  • Page 156 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) TOC00 is an 8-bit register that controls the TO00 output. TOC00 can be rewritten while only OSPT00 is operating (when TMC003 and TMC002 = other than 00). Rewriting the other bits is prohibited during operation.
  • Page 157 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-8. Format of 16-Bit Timer Output Control Register 00 (TOC00) (2/2) Address: FF89H After reset: 00H Symbol <6> <5> <3> <2> <0> TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 LVS00 LVR00 Setting of TO00 output status No change...
  • Page 158 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) PRM00 is the register that sets the TM00 count clock and TI000 and TI010 pin input valid edges. Rewriting PRM00 is prohibited during operation (when TMC003 and TMC002 = other than 00). PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 159 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-9. Format of Prescaler Mode Register 00 (PRM00) Address: FF87H After reset: 00H Symbol PRM00 ES110 ES100 ES010 ES000 PRM001 PRM000 ES110 ES100 TI010 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES010...
  • Page 160 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (5) Port alternate switch control register (MUXSEL) (16-pin products only) This register assigns the TI000, TI010, and TO00 pins function. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears MUXSEL to 00H.
  • Page 161 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (6) Port mode registers 3, 12 (PM3, PM12) This register sets port 3 and 12 input/output in 1-bit units.  16-pin products Note When using the P31/TxD0/<TO00>/CMPCOM pin for timer output, set PM31 and the output latches of P31 to Note When using the P32/RxD0/<TI010>/CMPIN and P121/X1/<TI000>/<INTP1>/TOOLC0 pins for timer input, set...

  • Page 162: Operation Of 16-Bit Timer/Event Counter 00

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation If bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register (TMC00) are set to 11 (clear & start mode entered upon a match between TM00 and CR000), the count operation is started in synchronization with the count clock.
  • Page 163 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-14. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as compare register...
  • Page 164 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-15. Example of Software Processing for Interval Timer Function TM00 register 0000H Operable bits (TMC003, TMC002) CR000 register INTTM000 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed before PRM00 register, setting the TMC003 and TMC002 bits to 11.

  • Page 165: Square-Wave Output Operation

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.2 Square-wave output operation When 16-bit timer/event counter 00 operates as an interval timer (refer to 6.4.1), a square wave can be output from the TO00 pin by setting the 16-bit timer output control register 00 (TOC00) to 03H. When TMC003 and TMC002 are set to 11 (count clear &...
  • Page 166 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-18. Example of Register Settings for Square-Wave Output Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as compare register...
  • Page 167 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-19. Example of Software Processing for Square-Wave Output Function TM00 register 0000H Operable bits (TMC003, TMC002) CR000 register TO00 output INTTM000 signal TO0n output control bit (TOC001, TOE00) <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed before...

  • Page 168: External Event Counter Operation

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 External event counter operation When bits 1 and 0 (PRM001 and PRM000) of the prescaler mode register 00 (PRM00) are set to 11 (for counting up with the valid edge of the TI000 pin) and bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between TM00 and CR000 (INTTM000) is generated.
  • Page 169 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Example of Register Settings in External Event Counter Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as...
  • Page 170 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Example of Register Settings in External Event Counter Mode (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) If M is set to CR000, the interrupt signal (INTTM000) is generated when the number of external events reaches (M + 1).
  • Page 171 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-22. Example of Software Processing in External Event Counter Mode TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) TO00 output Compare match interrupt (INTTM000) TO00 output control bits (TOC004, TOC001, TOE00) <1>...

  • Page 172: Operation In Clear & Start Mode Entered By Ti000 Pin Valid Edge Input

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 10 (clear & start mode entered by the TI000 pin valid edge input) and the count clock (set by PRM00) is supplied to the timer/event counter, TM00 starts counting up.
  • Page 173 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Compare Register) (a) TOC00 = 13H, PRM00 = 10H, CRC00 = 00H, TMC00 = 08H TM00 register 0000H Operable bits...
  • Page 174 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: compare register, CR010: capture register) Figure 6-25. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Capture Register) Edge TI000 pin...
  • Page 175 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-26. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Capture Register) (2/2) (b) TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 0AH, CR000 = 0003H TM00 register 0003H 0000H...
  • Page 176 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Operation in clear & start mode by entered TI000 pin valid edge input (CR000: capture register, CR010: compare register) Figure 6-27. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) Edge TI000 pin...
  • Page 177 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-28. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) (1/2) (a) TOC00 = 13H, PRM00 = 10H, CRC00 = 03H, TMC00 = 08H, CR010 = 0001H TM00 register 0000H Operable bits...
  • Page 178 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-28. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) (2/2) (b) TOC00 = 13H, PRM00 = 10H, CRC00 = 03H, TMC00 = 0AH, CR010 = 0003H TM00 register 0003H 0000H...
  • Page 179 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: capture register, CR010: capture register) Figure 6-29. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) Operable bits TMC003, TMC002...
  • Page 180 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) (2/3) (b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 = 0AH FFFFH TM00 register 0000H...
  • Page 181 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) (3/3) (c) TOC00 = 13H, PRM00 = 00H, CRC00 = 07H, TMC00 = 0AH TM00 register 0000H Operable bits...
  • Page 182 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 0: Inverts TO00 output on match between TM00 and CR000/CR010.
  • Page 183 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (2/2) (d) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM000 Count clock selection (setting TI000 valid edge is prohibited) 00: Falling edge detection 01: Rising edge detection...
  • Page 184 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32. Example of Software Processing in Clear & Start Mode Entered by TI000 Pin Valid Edge Input TM00 register 0000H Operable bits (TMC003, TMC002) Count clear input (TI000 pin input) Compare register (CR000) Compare match interrupt (INTTM000)

  • Page 185: Free-Running Timer Operation

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 Free-running timer operation When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 01 (free-running timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (OVF00) is set to 1 at the next clock, and TM00 is cleared (to 0000H) and continues counting.
  • Page 186 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Timing Example of Free-Running Timer Mode (CR000: Compare Register, CR010: Compare Register)  TOC00 = 13H, PRM00 = 00H, CRC00 = 00H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000)
  • Page 187 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-36. Timing Example of Free-Running Timer Mode (CR000: Compare Register, CR010: Capture Register)  TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input (TI000)
  • Page 188 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Free-running timer mode operation (CR000: capture register, CR010: capture register) Figure 6-37. Block Diagram of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) Operable bits TMC003, TMC002 Timer counter Count clock (TM00) Capture register Interrupt signal...
  • Page 189 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-38. Timing Example of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) (1/2) (a) TOC00 = 13H, PRM00 = 50H, CRC00 = 05H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input...
  • Page 190 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-38. Timing Example of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) (2/2) (b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input...
  • Page 191 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-39. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 0: Inverts TO00 output on match between TM00 and CR000/CR010. 1: Inverts TO00 output on match between TM00 and CR000/CR010 valid edge of TI000 pin.
  • Page 192 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-39. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM000 Count clock selection (setting TI000 valid edge is prohibited) 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited...
  • Page 193 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-40. Example of Software Processing in Free-Running Timer Mode FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) Compare match interrupt (INTTM000) Compare register (CR010) Compare match interrupt (INTTM010) Timer output control bits (TOE00, TOC004, TOC001) TO00 output...

  • Page 194: Ppg Output Operation

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 PPG output operation A square wave having a pulse width set in advance by CR010 is output from the TO00 pin as a PPG (Programmable Pulse Generator) signal during a cycle set by CR000 when bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11 (clear &...
  • Page 195 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-42. Example of Register Settings for PPG Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as...
  • Page 196 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-42. Example of Register Settings for PPG Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) An interrupt signal (INTTM000) is generated when the value of this register matches the count value of TM00.
  • Page 197 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-43. Example of Software Processing for PPG Output Operation TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) Compare match interrupt (INTTM000) Compare register (CR010) Compare match interrupt (INTTM010) Timer output control bits (TOE00, TOC004, TOC001) TO00 output N + 1...

  • Page 198: One-Shot Pulse Output Operation

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.7 One-shot pulse output operation A one-shot pulse can be output by setting bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register 00 (TMC00) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI000 pin valid edge) and setting bit 5 (OSPE00) of 16-bit timer output control register 00 (TOC00) to 1.
  • Page 199 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-45. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 01: Free running timer mode 10: Clear and start mode by valid edge of TI000 pin.
  • Page 200 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-45. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a compare register when a one-shot pulse is output.
  • Page 201 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-46. Example of Software Processing for One-Shot Pulse Output Operation (1/2) FFFFH TM00 register 0000H Operable bits 01 or 10 (TMC003, TMC002) One-shot pulse enable bit (OSPE0) One-shot pulse trigger bit (OSPT0) One-shot pulse trigger input (TI000 pin)
  • Page 202 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-46. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM00 register, before setting the TMC003 and TMC002 bits. CRC00 register, Note TOC00 register...

  • Page 203: Pulse Width Measurement Operation

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.8 Pulse width measurement operation TM00 can be used to measure the pulse width of the signal input to the TI000 and TI010 pins. Measurement can be accomplished by operating the 16-bit timer/event counter 00 in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI000 pin.
  • Page 204 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 A pulse width can be measured in the following three ways.  Measuring the pulse width by using two input signals of the TI000 and TI010 pins (free-running timer mode)  Measuring the pulse width by using one input signal of the TI000 pin (free-running timer mode) ...
  • Page 205 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measuring the pulse width by using one input signal of the TI000 pin (free-running timer mode) Set the free-running timer mode (TMC003 and TMC002 = 01). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge detected on the TI000 pin.
  • Page 206 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the TI000 pin valid edge input) Set the clear & start mode entered by the TI000 pin valid edge (TMC003 and TMC002 = 10). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge of the TI000 pin, and the count value of TM00 is captured to CR010 and TM00 is cleared (0000H) when the valid edge of the TI000 pin is detected.
  • Page 207 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-52. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI000 pin.
  • Page 208 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-52. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a capture register.
  • Page 209 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-53. Example of Software Processing for Pulse Width Measurement (1/2) (a) Example of free-running timer mode FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input (TI000) Capture register 0000H (CR010) Capture interrupt (INTTM010)
  • Page 210 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-53. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM00 register, before setting the TMC003 and TMC002 bits. CRC00 register, port setting TMC003, TMC002 bits =...

  • Page 211: Special Use Of Tm00

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Special Use of TM00 6.5.1 Rewriting CR010 during TM00 operation In principle, rewriting CR000 and CR010 of the µPD79F7023, 79F7024 microcontrollers when they are used as compare registers is prohibited while TM00 is operating (TMC003 and TMC002 = other than 00). However, the value of CR010 can be changed, even while TM00 is operating, using the following procedure if CR010 is used for PPG output and the duty factor is changed.
  • Page 212 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Setting LVS00 and LVR00 Set LVS00 and LVR00 using the following procedure. Figure 6-54. Example of Flow for Setting LVS00 and LVR00 Bits Setting TOC00.OSPE00, TOC004, TOC001 bits <1> Setting of timer output operation Setting TOC00.TOE00 bit Setting TOC00.LVS00, LVR00 bits <2>...

  • Page 213: Cautions For 16-Bit Timer/Event Counter 00

    R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.6 Cautions for 16-Bit Timer/Event Counter 00 (1) Restrictions for each channel of 16-bit timer/event counter 00 Table 6-3 shows the restrictions for each channel. Table 6-3. Restrictions for Each Channel of 16-Bit Timer/Event Counter 00 Operation Restriction ...
  • Page 214 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI000/TI010 pin and the reverse phase of the TI000 pin is detected while CR000/CR010 is read, CR010 performs a capture operation but the read value of CR000/CR010 is not guaranteed.
  • Page 215 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (7) Operation of OVF00 flag (a) Setting OVF00 flag (1) The OVF00 flag is set to 1 in the following case, as well as when TM00 overflows. Select the clear & start mode entered upon a match between TM00 and CR000. ...
  • Page 216 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (9) Capture operation (a) When valid edge of TI000 is specified as count clock When the valid edge of TI000 is specified as the count clock, the capture register for which TI000 is specified as a trigger does not operate correctly.
  • Page 217 R7F0C30x, R7F0C31x CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (12) Reading of 16-bit timer counter 00 (TM00) TM00 can be read without stopping the actual counter, because the count values captured to the buffer are fixed when it is read. The buffer, however, may not be updated when it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up.

  • Page 218: Chapter 7 8-Bit Timer/Event Counter 51

    R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 7.1 Functions of 8-Bit Timer/Event Counter 51 8-bit timer/event counter 51 is mounted onto all R7F0C30x, R7F0C31x products. 8-bit timer/event counter 51 has the following functions. (1) Interval timer (2) External event counter (3) Square-wave output...

  • Page 219: Configuration Of 8-Bit Timer/Event Counter 51

    R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 7.2 Configuration of 8-Bit Timer/Event Counter 51 8-bit timer/event counter 51 includes the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counter 51 Item Configuration Timer register 8-bit timer counter 51 (TM51) Timer input TI51 Register...
  • Page 220 R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 (1) 8-bit timer counter 51 (TM51) TM51 is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. Figure 7-2.

  • Page 221: Registers Controlling 8-Bit Timer/Event Counter 51

    R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 7.3 Registers Controlling 8-Bit Timer/Event Counter 51 The following four registers are used to control 8-bit timer/event counter 51.  Timer clock selection register 51 (TCL51)  8-bit timer mode control register 51 (TMC51) ...
  • Page 222 R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 (2) 8-bit timer mode control register 51 (TMC51) TMC51 is a register that performs 8-bit timer counter 51 (TM51) count operation control. TMC51 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.

  • Page 223: Operations Of 8-Bit Timer/Event Counter 51

    R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 7.4 Operations of 8-Bit Timer/Event Counter 51 7.4.1 Operation as interval timer 8-bit timer/event counter 51 operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 51 (CR51). When the count value of 8-bit timer counter 51 (TM51) matches the value set to CR51, counting continues with the TM51 value cleared to 0 and an interrupt request signal (INTTM51) is generated.
  • Page 224 R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 Figure 7-7. Interval Timer Operation Timing (2/2) (b) When CR51 = 00H Count clock TM5n CR5n TCE5n INTTM5n Interval time (c) When CR51 = FFH Count clock TM5n FEH FFH 00H CR5n TCE5n INTTM5n Interrupt acknowledged...

  • Page 225: Operation As External Event Counter

    R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI51 pin by 8-bit timer counter 51 (TM51). TM51 is incremented each time the valid edge specified by timer clock selection register 51 (TCL51) is input. Either the rising or falling edge can be selected.

  • Page 226: Square-Wave Output Operation

    R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 7.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 51 (CR51). The timer 51 output status is inverted at intervals determined by the count value preset to CR51. This enables a square wave with any selected frequency to be output (duty = 50%).

  • Page 227: Pwm Output Operation

    R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 Figure 7-9. Square-Wave Output Operation Timing Count clock N − 1 N − 1 TM51 count value Count start CR51 Timer 51 output 7.4.4 PWM output operation 8-bit timer/event counter 51 operates as a PWM output when bit 6 (TMC516) of 8-bit timer mode control register 51 (TMC51) is set to 1.
  • Page 228 R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 (1) PWM output basic operation Setting <1> Set each register.  Clear the port output latch (P30) and port mode register (PM30) to 0.  TCL51: Select the count clock.  CR51: Compare value ...
  • Page 229 R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 Figure 7-10. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n <2>...
  • Page 230 R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 (2) Operation with CR51 changed Figure 7-11. Timing of Operation with CR51 Changed (a) CR51 value is changed from N to M before clock rising edge of FFH  Value is transferred to CR51 at overflow immediately after change. Count clock TM5n N N + 1 N + 2...

  • Page 231: Cautions For 8-Bit Timer/Event Counter 51

    R7F0C30x, R7F0C31x CHAPTER 7 8-BIT TIMER/EVENT COUNTER 51 7.5 Cautions for 8-Bit Timer/Event Counter 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counter 51 (TM51) is started asynchronously to the count clock.

  • Page 232: Chapter 8 8-Bit Timer H1

    R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 CHAPTER 8 8-BIT TIMER H1 8.1 Functions of 8-Bit Timer H1 8-bit timer H1 is mounted onto all R7F0C30x, R7F0C31x products. 8-bit timer H1 has the following functions.  Interval timer  Square-wave output ...
  • Page 233 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 234 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 (1) 8-bit timer H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP01 with the count value of the 8-bit timer counter H1 and, when the two values match, generates an interrupt request signal (INTTMH1) and inverts the output level of TOH1.

  • Page 235: Registers Controlling 8-Bit Timer H1

    R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 8.3 Registers Controlling 8-Bit Timer H1 The following four registers are used to control 8-bit timer H1.  8-bit timer H mode register 1 (TMHMD1)  8-bit timer H carrier control register 1 (TMCYC1) ...
  • Page 236 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Figure 8-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH After reset: 00H <7> <1> <0> TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) Note Count clock selection...
  • Page 237 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be refreshed (the same value is written). 2. In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11).
  • Page 238 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 (3) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TOH1/TI51/INTP0 pin for timer output, clear PM30 and the output latches of P30 to 0. PM3 can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 239: Operation Of 8-Bit Timer H1

    R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 8.4 Operation of 8-Bit Timer H1 8.4.1 Operation as interval timer/square-wave output When the 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is generated and the 8-bit timer counter H1 is cleared to 00H. Compare register 11 (CMP11) is not used in interval timer mode.
  • Page 240 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Figure 8-8. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (Operation When 01H  CMP01  FEH) Count clock Count start 01H 00H 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn Interval time TOHn...
  • Page 241 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Figure 8-8. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP01 = FFH Count clock Count start 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP01 = 00H Count clock Count start 8-bit timer counter Hn...

  • Page 242: Operation As Pwm Output

    R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 8.4.2 Operation as PWM output In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. The 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during timer operation is prohibited.
  • Page 243 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHE1 = 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the PWM pulse output cycle and duty are as follows.
  • Page 244 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Figure 8-10. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter Hn 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H CMP0n CMP1n TMHEn INTTMHn TOHn (TOLEVn = 0)
  • Page 245 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Figure 8-10. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n CMP1n...
  • Page 246 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Figure 8-10. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter Hn CMP0n CMP1n TMHEn INTTMHn...
  • Page 247 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Figure 8-10. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H  03H, CMP01 = A5H) Count clock 8-bit timer 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H counter Hn...

  • Page 248: Carrier Generator Operation

    R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 8.4.3 Carrier generator operation In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). The carrier clock generated by the 8-bit timer H1 is output in the cycle set by the 8-bit timer/event counter 51.
  • Page 249 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal.
  • Page 250 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Setting <1> Set each register. Figure 8-12. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHMD1 Timer output enabled Default setting of timer output level Carrier generator mode selection Count clock (f...
  • Page 251 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 <10> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the carrier clock output cycle and duty are as follows.
  • Page 252 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Figure 8-13. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer H1 count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H H1 count value CMP01...
  • Page 253 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Figure 8-13. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer H1 count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H H1 count value CMP01...
  • Page 254 R7F0C30x, R7F0C31x CHAPTER 8 8-BIT TIMER H1 Figure 8-13. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3> <3>’ CMP11 M (L) TMHE1 INTTMH1...

  • Page 255: Chapter 9 Watchdog Timer

    R7F0C30x, R7F0C31x CHAPTER 9 WATCHDOG TIMER CHAPTER 9 WATCHDOG TIMER 9.1 Functions of Watchdog Timer The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.

  • Page 256: Configuration Of Watchdog Timer

    R7F0C30x, R7F0C31x CHAPTER 9 WATCHDOG TIMER 9.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 9-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 9-2.

  • Page 257: Register Controlling Watchdog Timer

    R7F0C30x, R7F0C31x CHAPTER 9 WATCHDOG TIMER 9.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction.

  • Page 258: Operation Of Watchdog Timer

    R7F0C30x, R7F0C31x CHAPTER 9 WATCHDOG TIMER 9.4 Operation of Watchdog Timer 9.4.1 Controlling operation of watchdog timer When the watchdog timer is used, its operation is specified by the option byte (0080H).  Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, refer to CHAPTER 20).

  • Page 259: Setting Overflow Time Of Watchdog Timer

    R7F0C30x, R7F0C31x CHAPTER 9 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. LSROSC = 0 (Internal Low-Speed LSROSC = 1 (Internal Low-Speed Oscillator Can Be Stopped by Software) Oscillator Cannot Be Stopped)

  • Page 260: Setting Window Open Period Of Watchdog Timer

    R7F0C30x, R7F0C31x CHAPTER 9 WATCHDOG TIMER 9.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows. ...
  • Page 261 R7F0C30x, R7F0C31x CHAPTER 9 WATCHDOG TIMER Remark If the overflow time is set to 2 , the window close time and open time are as follows. Setting of Window Open Period 100% Window close time 0 to 7.11 ms 0 to 4.74 ms 0 to 2.37 ms None Window open time...

  • Page 262: Chapter 10 A/D Converter

    R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER CHAPTER 10 A/D CONVERTER Item 16 pins 20 pins 10-bit A/D converter 6 ch 5 ch 10.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to 6 channels (ANI0 to ANI2, ANI5 to ANI7) with a resolution of 10 bits.
  • Page 263 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER Figure 10-1. Block Diagram of A/D Converter (1) 16-pin products ADCS bit ANI0/P20 Sample & hold circuit Note ANI1/AMP0OUT /P21 A/D voltage comparator ANI2/P22 ANI5/P25 Note ANI6/AMP1OUT /P26 ADCE bit ANI7/P27 Successive approximation register (SAR) Controller INTAD A/D conversion...

  • Page 264: Configuration Of A/D Converter

    R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER 10.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI7 pins These are the analog input pins of the 8-channel A/D converter. They input analog signals to be converted into digital signals.
  • Page 265 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER (8) 10-bit A/D conversion result register (ADCR) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register stores the A/D conversion result in its higher 10 bits (the lower 6 bits are fixed to 0).

  • Page 266: Registers Used In A/D Converter

    R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER 10.3 Registers Used in A/D Converter The A/D converter uses the following six registers.  A/D converter mode register (ADM)  10-bit A/D conversion result register (ADCR)  8-bit A/D conversion result register H (ADCRH) ...
  • Page 267 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER Figure 10-4. Timing Chart When Comparator Is Used Comparator operation ADCE Comparator Conversion Conversion Conversion Conversion operation waiting operation stopped ADCS Note  Note To stabilize the internal circuit, the time from setting ADCE to 1 to setting ADCS to 1 must be 1 s or longer.
  • Page 268 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER Table 10-2. A/D Conversion Time Selection (1) 2.7 V  AV  5.5 V (LV0 = 0) A/D Converter Mode Register (ADM) Conversion Time Selection Conversion Clock = 2 MHz = 10 MHz  264/f Setting prohibited 26.4...
  • Page 269 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER Figure 10-5. A/D Converter Sampling and A/D Conversion Timing ADCS ← 1 or ADS rewrite ADCS Sampling timing INTAD Wait Sampling Sampling Successive conversion Transfer Note period clear to ADCR, clear INTAD generation Conversion time Conversion time Note For details of wait period, refer to CHAPTER 26 CAUTIONS FOR WAIT.
  • Page 270 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER (3) 8-bit A/D conversion result register H (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
  • Page 271 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER Figure 10-8. Format of Analog Input Channel Specification Register (ADS) (a) 16-pin products Address: FF0EH After reset: 00H Symbol <2> <1> <0> ADS2 ADS1 ADS0 ADS2 ADS1 ADS0 Analog input Input source channel P20/ANI0 pin ANI0 P21/ANI1 pin or operational ANI1...
  • Page 272 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER (5) A/D port configuration register (ADPC) ADPC switches the P20/AMP0-/ANI0 to P24/ANI4 pins (P20/AMP0-/ANI0 to P22/ANI2/AMP0+, P25/ANI5/AMP1- to P27/ANI7/AMP1+ for 16-pin products) to digital I/O or analog I/O of port. Each bit of ADPC corresponds to a pin of port 2 and can be specified in 1-bit units.
  • Page 273 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER Table 10-3. Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+, P25/ANI5/AMP1-, P27/ANI7/AMP1+ Pins ADPC Register PM2 Register OPAMPmE bit ADS Register P20/ANI0/AMP0-, (n = 0, 2, 5, 7) P22/ANI2/AMP0+, (m = 0, 1) P25/ANI5/AMP1-, P27/ANI7/AMP1+ Pins Analog input Analog input (to be converted into Input mode Selects ANIn.
  • Page 274 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER (b) 20-pin products When using the ANI0/AMP0-/P20 to ANI4/P24 pins for analog input port, set PM20 to PM24 to 1. The output latches of P20 to P24 at this time may be 0 or 1. If PM20 to PM24 are set to 0, they cannot be used as analog input port pins.
  • Page 275 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER Table 10-6. Setting Functions of P21/ANI1/AMP0OUT Pin ADPC Register PM2 Register OPAMP0E ADS Register P21/ANI1/AMP0OUT Pin Analog I/O Input mode Selects ANI1. Analog input (to be converted into digital selection signals) Does not select ANI1. Analog input (not to be converted into digital signals) Selects ANI1.

  • Page 276: A/D Converter Operations

    R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Operations 10.4.1 Basic operations of A/D converter <1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register (ADM).
  • Page 277 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER Figure 10-12. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR, result ADCRH ADCS INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.

  • Page 278: Input Voltage And Conversion Results

    R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER 10.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. ...

  • Page 279: A/D Converter Operation Mode

    R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER 10.4.3 A/D converter operation mode One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. Remark A/D converter analog input pins differ depending on products. ...
  • Page 280 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER The setting methods are described below. <1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register (ADM). <2>...

  • Page 281: How To Read A/D Converter Characteristics Table

    R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER 10.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
  • Page 282 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale  3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.

  • Page 283: Cautions For A/D Converter

    R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER 10.6 Cautions for A/D Converter (1) Operating current in STOP mode To satisfy the DC characteristics of the power supply current in STOP mode, clear bits 7 (ADCS) and 0 (ADCE) of A/D converter mode register (ADM) to 0 before executing a STOP instruction. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation.
  • Page 284 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER Figure 10-21. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AV equal to or lower than V may enter, clamp with a diode with a small V value (0.3 V or lower).
  • Page 285 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER (7) AV pin input impedance A series resistor string of several tens of k is connected between the AV and V pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AV and V pins, resulting in a large reference voltage error.
  • Page 286 R7F0C30x, R7F0C31x CHAPTER 10 A/D CONVERTER (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10-23. Internal Equivalent Circuit of ANIn Pin ANIn Table 10-8. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) 2.3 V ...

  • Page 287: Chapter 11 Operational Amplifiers

    R7F0C30x, R7F0C31x CHAPTER 11 OPERATIONAL AMPLIFIERS CHAPTER 11 OPERATIONAL AMPLIFIERS 11.1 Function of Operational Amplifier Operational amplifiers 0 and 1 are mounted onto R7F0C303x, R7F0C304x, R7F0C305x, R7F0C309x, R7F0C310x, and R7F0C311x. Operational amplifiers 0 and 1 both have two input pins (the AMPn- pin and the AMPn+ pin) and one output pin (the AMPnOUT pin), and can be used as single-power supply amplifiers that can be externally connected.

  • Page 288: Configuration Of Operational Amplifier

    R7F0C30x, R7F0C31x CHAPTER 11 OPERATIONAL AMPLIFIERS 11.2 Configuration of Operational Amplifier The operational amplifiers consist of the following hardware. Table 11-1. Configuration of Operational Amplifier Item Configuration  Operational amplifier input AMPn pin, AMPn+ pin Operational amplifier output AMPnOUT pin Control registers Operational amplifier control register (AMPM) A/D configuration register (ADPC)
  • Page 289 R7F0C30x, R7F0C31x CHAPTER 11 OPERATIONAL AMPLIFIERS Figure 11-1. Block Diagram of Operational Amplifier (1) R7F0C3034, R7F0C3044, R7F0C3054, R7F0C3094, R7F0C3104, R7F0C3114 Operational amplifier 0 AMP0OUT/ANI1/P21 AMP0-/ANI0/P20 AMP0 To A/D converter AMP0+/ANI2/P22 (Analog input channel: ANI1) AMP1OUT/ANI6/P26 Operational amplifier 1 AMP1-/ANI5/P25 To A/D converter AMP1 AMP1+/ANI7/P27 (Analog input channel: ANI6)

  • Page 290: Registers Used In Operational Amplifier

    R7F0C30x, R7F0C31x CHAPTER 11 OPERATIONAL AMPLIFIERS 11.3 Registers Used in Operational Amplifier The operational amplifiers use the following four registers.  Operational amplifier control register (AMPM)  A/D port configuration register (ADPC)  Analog input channel specification register (ADS)  Port mode register 2 (PM2) (1) Operational amplifier control register (AMPM) This register controls the operations of operational amplifiers 0 and 1.
  • Page 291 R7F0C30x, R7F0C31x CHAPTER 11 OPERATIONAL AMPLIFIERS (2) A/D port configuration register (ADPC) ADPC switches the P20/AMP0-/ANI0 to P24/ANI4 pins (P20/AMP0-/ANI0 to P22/ANI2/AMP0+, P25/ANI5/AMP1- to P27/ANI7/AMP1+ for R7F0C3034, R7F0C3044, R7F0C3054, R7F0C3094, R7F0C3104, and R7F0C3114) to digital I/O or analog I/O of ports. Each bit of ADPC corresponds to a pin of port 2 and can be specified in 1-bit units. Reset signal generation clears ADPC to 00H.
  • Page 292 R7F0C30x, R7F0C31x CHAPTER 11 OPERATIONAL AMPLIFIERS (3) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-4.
  • Page 293 R7F0C30x, R7F0C31x CHAPTER 11 OPERATIONAL AMPLIFIERS (4) Port mode register 2 (PM2) (a) R7F0C3034, R7F0C3044, R7F0C3054, R7F0C3094, R7F0C3104, R7F0C3114 When using AMP0-/ANI0/P20, AMP0OUT/ANI1/P21, and AMP0+/ANI2/P22 pins for the operational amplifier 0, set PM20 to PM22 to 1. When using AMP1-/ANI5/P25, AMP1OUT/ANI6/P26, and AMP1+/ANI7/P27 pins for the operational amplifier 1, set PM25 to PM27 to 1.
  • Page 294 R7F0C30x, R7F0C31x CHAPTER 11 OPERATIONAL AMPLIFIERS Table 11-2. Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+, P25/ANI5/AMP1-, P27/ANI7/AMP1+ Pins ADPC Register PM2 Register OPAMPmE bit ADS Register P20/ANI0/AMP0-, (n = 0, 2, 5, 7) P22/ANI2/AMP0+, (m = 0, 1) P25/ANI5/AMP1-, P27/ANI7/AMP1+ Pins Analog input Analog input (to be converted into Input mode Selects ANIn.
  • Page 295 R7F0C30x, R7F0C31x CHAPTER 11 OPERATIONAL AMPLIFIERS (b) R7F0C3036, R7F0C3046, R7F0C3056, R7F0C3096, R7F0C3106, R7F0C3116 When using AMP0-/ANI0/P20, AMP0OUT/ANI1/P21, and AMP0+/ANI2/P22 pins for the operational amplifier 0, set PM20 to PM22 to 1. When using AMP1-/P25, AMP1OUT/P26, and AMP1+/P27 pins for the operational amplifier 1, set PM25 to PM27 to 1. The output latches of P20 to P22 and P25 to P27 at this time may be 0 or 1.
  • Page 296 R7F0C30x, R7F0C31x CHAPTER 11 OPERATIONAL AMPLIFIERS Table 11-5. Setting Functions of P21/ANI1/AMP0OUT Pin ADPC Register PM2 Register OPAMP0E ADS Register P21/ANI1/AMP0OUT Pin Analog I/O Input mode Selects ANI1. Analog input (to be converted into digital selection signals) Does not select ANI1. Analog input (not to be converted into digital signals) Selects ANI1.

  • Page 297: Operational Amplifier Operations

    R7F0C30x, R7F0C31x CHAPTER 11 OPERATIONAL AMPLIFIERS 11.4 Operational Amplifier Operations Operational amplifiers 0 and 1 both have two input pins (the AMPn- pin and the AMPn+ pin) and one output pin (the AMPnOUT pin), and can be used as single-power supply amplifiers that can be externally connected. The amplified voltage can be used as an analog input of the A/D converter, because the AMP0OUT pin is alternatively used with analog input pin of the A/D converter (In R7F0C3034, R7F0C3044, R7F0C3054, R7F0C3094, R7F0C3104, and R7F0C3114, AMP1OUT is also used as the analog input pin of A/D converter).

  • Page 298: Chapter 12 Comparator

    R7F0C30x, R7F0C31x CHAPTER 12 COMPARATOR CHAPTER 12 COMPARATOR 12.1 Features of Comparator Comparator is mounted onto R7F0C303x, R7F0C304x, R7F0C305x, R7F0C309x, R7F0C310x, and R7F0C311x. Comparator has the following functions. • The following reference voltages can be selected. <1> Internal reference voltage <2>...
  • Page 299 R7F0C30x, R7F0C31x CHAPTER 12 COMPARATOR Figure 12-1. Block Diagram of Comparator (1) R7F0C3034, R7F0C3044, R7F0C3054, R7F0C3094, R7F0C3104, R7F0C3114 External interrupt falling edge External interrupt rising enable registers (EGN) edge enable registers (EGP) Comparator port configuration register (CMPPC) EGN2 EGP2 CMPIN CMPCOM Edge detection INTCMP...

  • Page 300: Configuration Of Comparator

    R7F0C30x, R7F0C31x CHAPTER 12 COMPARATOR 12.2 Configuration of Comparator The comparator consists of the following hardware. Table 12-1. Configuration of Comparator Item Configuration Control registers Comparator control register (CMPCTL) Comparator port configuration register (CMPPC) Port mode register 3 (PM3) Port register 3 (P3) R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...

  • Page 301: Registers Controlling Comparator

    R7F0C30x, R7F0C31x CHAPTER 12 COMPARATOR 12.3 Registers Controlling Comparator The comparator uses the following three registers. • Comparator control register (CMPCTL) • Comparator port configuration register (CMPPC) • Port mode register 3 (PM3) (1) Comparator control register (CMPCTL) CMPCTL is used to control the operation of comparator n, enable or disable comparator output, reverse the output, and set the noise elimination width.
  • Page 302 R7F0C30x, R7F0C31x CHAPTER 12 COMPARATOR Figure 12-2. Format of Comparator Control Register (CMPCTL) (2/2) CINV Output reversal setting Forward Reverse Cautions 1. Rewrite CDFS1, CDFS0, CMPOUTEN, CREGSEL, COUTEN, CINV after setting the comparator operation to the disabled state (CMP0EN = 0). 2.
  • Page 303 R7F0C30x, R7F0C31x CHAPTER 12 COMPARATOR (3) Port mode register 3 (PM3) PM3 is used to set port 3 input or output in 1-bit units. Note Note When CMPIN/P32/RxD0/<TI010> pin, and CMPCOM/P31/TxD0/<TO00> pin are used for the comparator input and comparator common input respectively, set PM31, PM32 bits to 1. The output latches of P31, P32 at this time may be 0 or 1.
  • Page 304 R7F0C30x, R7F0C31x CHAPTER 12 COMPARATOR Note Note When using P32/RxD0/CMPIN/<TI010> and P31/TxD0/CMPCOM/<TO00> , set the registers according to the pin function to be used (refer to Tables 12-2 and 12-3). Note Table 12-2. Setting Functions of P32/RxD0/CMPIN/<TI010> Note CMPPC PM3 Register CMP0EN bit P32/RxD0/CMPIN/<TI010>...

  • Page 305: Operation Of Comparator

    R7F0C30x, R7F0C31x CHAPTER 12 COMPARATOR 12.4 Operation of Comparator 12.4.1 Starting comparator operation (using internal reference voltage for comparator reference voltage) Figure 12-5. Example of Setting Procedure when Starting Comparator Operation (Using Internal Reference Voltage for Comparator Reference Voltage) Start Setting the pin to be used as CMPPC register setting a comparator input to analog input.

  • Page 306: Starting Comparator Operation (Using Input Voltage From Cmpcom Pin For Comparator Reference Voltage)

    R7F0C30x, R7F0C31x CHAPTER 12 COMPARATOR 12.4.2 Starting comparator operation (using input voltage from CMPCOM pin for comparator reference voltage) Figure 12-6. Example of Setting Procedure when Starting Comparator Operation (Using Input Voltage from Comparator Common (CMPCOM) Pin for Comparator Reference Voltage) Start Setting the pin to be used as a comparator input and CMPPC register setting...

  • Page 307: Chapter 13 Serial Interface Uart0

    R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 CHAPTER 13 SERIAL INTERFACE UART0 13.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 13.4.1 Operation stop mode.

  • Page 308: Configuration Of Serial Interface Uart0

    R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 13.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 13-1. Configuration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0)
  • Page 309 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 310 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 311 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0).

  • Page 312: Registers Controlling Serial Interface Uart0

    R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 13.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers.  Asynchronous serial interface operation mode register 0 (ASIM0)  Asynchronous serial interface reception error status register 0 (ASIS0) ...
  • Page 313 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
  • Page 314 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction.
  • Page 315 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 1FH.
  • Page 316 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 Remarks 1. f : Frequency of base clock selected by the TPS01 and TPS00 bits XCLK0 2. f Peripheral hardware clock frequency 3. k: Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) 4.

  • Page 317: Operation Of Serial Interface Uart0

    R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 13.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes.  Operation stop mode  Asynchronous serial interface (UART) mode 13.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode.

  • Page 318: Asynchronous Serial Interface (Uart) Mode

    R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 13.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
  • Page 319 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 The relationship between the register settings and pins is shown below. Table 13-2. Relationship Between Register Settings and Pins (16-pin products) POWER0 TXE0 RXE0 PM31 PM32 UART0 Pin Function Operation TxD0/<TO00>/ RxD0/<TI010>/ Note 1 Note 1 CMPCOM /P31...
  • Page 320 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 13-6 and 13-7 show the format and waveform example of the normal transmit/receive data. Figure 13-6. Format of Normal UART Transmit/Receive Data 1 data frame Start Parity...
  • Page 321 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
  • Page 322 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 (c) Transmission If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0).
  • Page 323 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the R D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the R D0 pin input is detected.
  • Page 324 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt (INTSR0) is generated.

  • Page 325: Dedicated Baud Rate Generator

    R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 13.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator ...

  • Page 326: Calculation Of Baud Rate

    R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock to be generated can be specified by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value (f /8 to f /31) of the 5-bit...
  • Page 327 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 (2) Error of baud rate The baud rate error can be calculated by the following expression. Actual baud rate (baud rate with error)  Error (%) =  1  100 [%] Desired baud rate (correct baud rate) Cautions 1.
  • Page 328 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
  • Page 329 R7F0C30x, R7F0C31x CHAPTER 13 SERIAL INTERFACE UART0 k  2 21k + 2 Minimum permissible data frame length: FLmin = 11  FL   FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. ...

  • Page 330: Chapter 14 Interrupt Functions

    R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS CHAPTER 14 INTERRUPT FUNCTIONS 14.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L).
  • Page 331 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS Table 14-1. Interrupt Source List (1/2) Interrupt Internal/ Basic Default Interrupt Source Vector Note 2 Type External Configuration Priority Table Name Trigger Note 1 Type Address Note 3 Maskable Internal INTLVI Low-voltage detection 0004H External INTP0 Pin input edge detection...
  • Page 332 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS Table 14-1. Interrupt Source List (2/2) Interrupt Internal/ Basic Default Interrupt Source Vector Note 2 Type External Configuration Priority Table Name Trigger Note 1 Type Address Maskable 002EH 0030H 0032H 0034H 0036H 0038H 003AH 003CH ...
  • Page 333 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal Note (B) External maskable interrupt (INTPn, INTCMP Internal bus External interrupt edge enable register (EGP, EGN)
  • Page 334 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Basic Configuration of Interrupt Function (2/2) (C) Software interrupt Internal bus Interrupt Vector table Priority controller request address generator Interrupt request flag Interrupt enable flag ISP: In-service priority flag Interrupt mask flag Priority specification flag R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...

  • Page 335: Registers Controlling Interrupt Functions

    R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS 14.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions.  Interrupt request flag registers (IF0L, IF0H, IF1L)  Interrupt mask flag registers (MK0L, MK0H, MK1L) ...
  • Page 336 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
  • Page 337 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L) Address: FFE0H After reset: 00H R/W Symbol <3> <2> <1> <0> Note CMPIF IF0L PIF1 PIF0 LVIIF Address: FFE1H After reset: 00H Symbol <7>...
  • Page 338 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form 16-bit register MK0, they are set by a 16-bit memory manipulation instruction.
  • Page 339 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set by a 16-bit memory manipulation instruction.
  • Page 340 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable registers (EGP), external interrupt falling edge enable registers (EGN) These registers specify the valid edge for INTPn. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
  • Page 341 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.

  • Page 342: Interrupt Servicing Operations

    R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS 14.4 Interrupt Servicing Operations 14.4.1 Maskable interrupt acknowledgment A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
  • Page 343 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated...
  • Page 344 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock)

  • Page 345: Software Interrupt Request Acknowledgment

    R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS 14.4.2 Software interrupt request acknowledgment A software interrupt acknowledge is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH, 003FH) are loaded into the PC and branched.
  • Page 346 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0)
  • Page 347 R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx RETI (PR = 0)

  • Page 348: Interrupt Request Hold

    R7F0C30x, R7F0C31x CHAPTER 14 INTERRUPT FUNCTIONS 14.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.

  • Page 349: Chapter 15 Standby Function

    R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION CHAPTER 15 STANDBY FUNCTION 15.1 Standby Function and Configuration 15.1.1 Standby function The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode.

  • Page 350: Registers Controlling Standby Function

    R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION 15.1.2 Registers controlling standby function The standby function is controlled by the following two registers.  Oscillation stabilization time counter status register (OSTC)  Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, refer to CHAPTER 5 CLOCK GENERATOR. (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
  • Page 351 R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION Figure 15-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H After reset: 00H Symbol OSTC MOST11 MOST13 MOST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status = 10 MHz ...
  • Page 352 R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION Figure 15-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H After reset: 05H Symbol OSTS OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection = 10 MHz  204.8  819.2 1.64 ms 3.27 ms 6.55 ms...

  • Page 353: Standby Function Operation

    R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION 15.2 Standby Function Operation 15.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, or internal high-speed oscillation clock. The operating statuses in the HALT mode are shown below.
  • Page 354 R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
  • Page 355 R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 15-4.
  • Page 356 R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION Table 15-2. Operation in Response to Interrupt Request in HALT Mode Release Source MK PR Operation  Maskable interrupt Next address request instruction execution  Interrupt servicing execution Next address instruction execution  Interrupt servicing execution ...

  • Page 357: Stop Mode

    R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION 15.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the main system clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.
  • Page 358 R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware.
  • Page 359 R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION (2) STOP mode release Figure 15-5. Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request Is Generated) STOP mode release STOP mode High-speed system clock (X1 oscillation) High-speed system clock (external clock input) Internal high-speed oscillation clock...
  • Page 360 R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed.
  • Page 361 R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION Figure 15-6. STOP Mode Release by Interrupt Request Generation (2/2) (3) When internal high-speed oscillation clock is used as CPU clock Interrupt request STOP instruction Standby release signal Normal operation Normal operation (internal high-speed (internal high-speed Note 1 oscillation clock)
  • Page 362 R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION Figure 15-7. STOP Mode Release by Reset (1) When high-speed system clock is used as CPU clock STOP instruction Reset signal Reset Normal operation Normal operation processing (high-speed Reset (internal high-speed (11 to 63 μs) Status of CPU system clock) STOP mode...
  • Page 363 R7F0C30x, R7F0C31x CHAPTER 15 STANDBY FUNCTION Table 15-4. Operation in Response to Interrupt Request in STOP Mode Release Source MK PR Operation  Maskable interrupt Next address request instruction execution  Interrupt servicing execution Next address instruction execution  Interrupt servicing execution ...

  • Page 364: Chapter 16 Reset Function

    R7F0C30x, R7F0C31x CHAPTER 16 RESET FUNCTION CHAPTER 16 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage of the low-voltage detector (LVI) and detection voltage External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is generated.
  • Page 365 R7F0C30x, R7F0C31x CHAPTER 16 RESET FUNCTION R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 366 R7F0C30x, R7F0C31x CHAPTER 16 RESET FUNCTION Figure 16-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization (90 to 482 μs) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset Wait for voltage processing...
  • Page 367 R7F0C30x, R7F0C31x CHAPTER 16 RESET FUNCTION Figure 16-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation accuracy stabilization STOP instruction execution (90 to 482 μs) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Wait for voltage...
  • Page 368 R7F0C30x, R7F0C31x CHAPTER 16 RESET FUNCTION Table 16-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped Operation stopped (X1 and X2 pins are input port mode) Clock input invalid (EXCLK pin is input port mode) EXCLK Operation stopped...
  • Page 369 R7F0C30x, R7F0C31x CHAPTER 16 RESET FUNCTION Table 16-2. Hardware Statuses After Reset Acknowledgment (1/3) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined...
  • Page 370 R7F0C30x, R7F0C31x CHAPTER 16 RESET FUNCTION Table 16-2. Hardware Statuses After Reset Acknowledgment (2/3) Hardware Status After Reset Note 1 Acknowledgment Clock operation mode select register (OSCCTL) Processor clock control register (PCC) Internal oscillation mode register (RCM) Main OSC control register (MOC) Main clock mode register (MCM) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS)
  • Page 371 R7F0C30x, R7F0C31x CHAPTER 16 RESET FUNCTION Table 16-2. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Status After Reset Note 1 Acknowledgment Note 2 Reset function Reset control flag register (RESF) Note 2 Low-voltage detector Low-voltage detection register (LVIM) Note 2 Low-voltage detection level selection register (LVIS) Interrupt Request flag registers 0L, 0H, 1L (IF0L, IF0H, IF1L)

  • Page 372: Register For Confirming Reset Source

    R7F0C30x, R7F0C31x CHAPTER 16 RESET FUNCTION 16.1 Register for Confirming Reset Source Many internal reset generation sources exist in the R7F0C30x, R7F0C31x microcontrollers. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction.

  • Page 373: Chapter 17 Power-On-Clear Circuit

    R7F0C30x, R7F0C31x CHAPTER 17 POWER-ON-CLEAR CIRCUIT CHAPTER 17 POWER-ON-CLEAR CIRCUIT 17.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. (1) When LVI default start function stopped is set (option byte: LVISTART = 0)  An internal reset signal is generated on power application. When the supply voltage (V ) exceeds the detection = 1.59 V 0.15 V), the reset status is released.

  • Page 374: Configuration Of Power-On-Clear Circuit

    R7F0C30x, R7F0C31x CHAPTER 17 POWER-ON-CLEAR CIRCUIT 17.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 17-1. Figure 17-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Reference voltage source 17.3 Operation of Power-on-Clear Circuit ...
  • Page 375 R7F0C30x, R7F0C31x CHAPTER 17 POWER-ON-CLEAR CIRCUIT Figure 17-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) When LVI is OFF upon power application (option byte: LVISTART = 0) Set LVI to be Set LVI to be Set LVI to be used for reset used for interrupt...
  • Page 376 R7F0C30x, R7F0C31x CHAPTER 17 POWER-ON-CLEAR CIRCUIT Figure 17-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) When LVI is ON upon power application (option byte: LVISTART = 1) Set LVI to be Set LVI to be Set LVI to be used for interrupt used for reset...

  • Page 377: Cautions For Power-On-Clear Circuit

    R7F0C30x, R7F0C31x CHAPTER 17 POWER-ON-CLEAR CIRCUIT 17.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the detection voltage (V the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
  • Page 378 R7F0C30x, R7F0C31x CHAPTER 17 POWER-ON-CLEAR CIRCUIT Figure 17-3. Example of Software Processing After Reset Release (2/2)  Checking reset source Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Reset processing by low-voltage detector Power-on-clear/external...

  • Page 379: Chapter 18 Low-Voltage Detector

    R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR CHAPTER 18 LOW-VOLTAGE DETECTOR 18.1 Functions of Low-Voltage Detector The low-voltage detector has the following functions.  The LVI circuit compares the supply voltage (V ) with the LVI detection voltage (V ) and generates an internal reset or internal interrupt signal.

  • Page 380: Configuration Of Low-Voltage Detector

    R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR 18.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 18-1. Figure 18-1. Block Diagram of Low-Voltage Detector N-ch Internal reset signal − INTLVI Reference voltage source Low-voltage detection level Low-voltage detection register selection register (LVIS) (LVIM)

  • Page 381: Registers Controlling Low-Voltage Detector

    R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR 18.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers.  Low-voltage detection register (LVIM)  Low-voltage detection level select register (LVIS) (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 382 R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR Figure 18-2. Format of Low-Voltage Detection Register (LVIM) Note 1 Note 2 Address: FFBEH After reset: 00H <7> <1> <0> Symbol LVION LVIMD LVIF LVIM Notes 3, 4 LVION Enables low-voltage detection operation Disables operation Enables operation Note 3 LVIMD...
  • Page 383 R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input sets this register to 00H. Figure 18-3.

  • Page 384: Operation Of Low-Voltage Detector

    R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR 18.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. (1) Used as reset (LVIMD = 1)  Compares the supply voltage (V ) and LVI detection voltage (V ), generates an internal reset signal when V <...

  • Page 385: When Used As Reset

    R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR 18.4.1 When used as reset (1) When LVI default start function stopped is set (LVISTART = 0)  When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the LVI detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS).
  • Page 386 R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR Figure 18-4. Timing of Low-Voltage Detector Internal Reset Signal Generation (LVISTART = 0) Set LVI to be used for reset Supply voltage (V = 1.59 V (TYP.) Time LVIMK flag Note 1 (set by software) <1>...
  • Page 387 R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR (2) When LVI default start function enabled is set (LVISTART = 1) The setting when operation starts and when operation stops is the same as that described in 18.4.1 (1) When LVI default start function stopped is set (LVISTART = 0). Figure 18-5.

  • Page 388: When Used As Interrupt

    R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR 18.4.2 When used as interrupt (1) When LVI default start function stopped is set (LVISTART = 0)  When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the LVI detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS).
  • Page 389 R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR Figure 18-6. Timing of Low-Voltage Detector Interrupt Signal Generation (LVISTART = 0) Supply voltage (V = 1.59 V (TYP.) Note 3 Note 3 Time LVIMK flag (set by software) <1> Note 1 <8> Cleared by software LVION flag <2>...
  • Page 390 R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR (2) When LVI default start function enabled is set (LVISTART = 1) The setting when operation starts and when operation stops is the same as that described in 18.4.2 (1) When LVI default start function stopped is set (LVISTART = 0). Figure 18-7.

  • Page 391: Cautions For Low-Voltage Detector

    R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR 18.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. Operation example 1: When used as reset The system may be repeatedly reset and released from the reset status.
  • Page 392 R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR Figure 18-8. Example of Software Processing After Reset Release (1/2)  If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Note Check the reset source Initialization processing <1> LVI reset ;...
  • Page 393 R7F0C30x, R7F0C31x CHAPTER 18 LOW-VOLTAGE DETECTOR Figure 18-8. Example of Software Processing After Reset Release (2/2)  Checking reset source Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Power-on-clear/external reset generated Reset processing by...

  • Page 394: Chapter 19 Regulator

    R7F0C30x, R7F0C31x CHAPTER 19 REGULATOR CHAPTER 19 REGULATOR 19.1 Regulator Overview The R7F0C30x, R7F0C31x microcontrollers contain a circuit for operating the device with a constant voltage. At this  time, in order to stabilize the regulator output voltage, connect the REGC pin to V via a capacitor (0.47 to 1 However, when using the STOP mode that has been entered since operation of the internal high-speed oscillation clock ...

  • Page 395: Chapter 20 Option Byte

    R7F0C30x, R7F0C31x CHAPTER 20 OPTION BYTE CHAPTER 20 OPTION BYTE 20.1 Functions of Option Bytes The flash memory at 0080H, 0081H, and 0084H of the R7F0C30x, R7F0C31x is an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions.

  • Page 396: Format Of Option Byte

    R7F0C30x, R7F0C31x CHAPTER 20 OPTION BYTE (3) 0082H/1082H Be sure to set to 00H. Caution Set a 00H to 1082H because 0082H and 1082H are switched during the boot swap operation. (4) 0083H/1083H  On-chip debug mode  Disabling on-chip debug mode ...
  • Page 397 R7F0C30x, R7F0C31x CHAPTER 20 OPTION BYTE Figure 20-1. Format of Option Byte (1/3) Note Address: 0080H/1080H WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 LSROSC WINDOW1 WINDOW0 Watchdog timer window open period 100% WDTON Operation control of watchdog timer counter/illegal access detection Counter operation disabled (counting stopped after reset), illegal access detection operation disabled Counter operation enabled (counting started after reset), illegal access detection operation enabled...
  • Page 398 R7F0C30x, R7F0C31x CHAPTER 20 OPTION BYTE Figure 20-1. Format of Option Byte (2/3) Notes 1, 2 Address: 0081H/1081H LVISTART LVISTART LVI default start operation control LVI is OFF by default upon power application (LVI default start function stopped) LVI is ON by default upon power application (LVI default start function enabled) Notes 1.
  • Page 399 R7F0C30x, R7F0C31x CHAPTER 20 OPTION BYTE Figure 20-1. Format of Option Byte (3/3) Note Address: 0084H/1084H OCDEN1 OCDEN0 OCDEN1 OCDEN0 On-chip debug operation control Operation disabled Setting prohibited Operation enabled. Does not erase data of the flash memory in case authentication of the on-chip debug security ID fails.
  • Page 400 R7F0C30x, R7F0C31x CHAPTER 20 OPTION BYTE Here is an example of description of the software for setting the option bytes. CSEG AT 0080H OPTION: DB ; Enables watchdog timer operation (illegal access detection operation), ; Window open period of watchdog timer: 50%, ;...

  • Page 401: Chapter 21 Flash Memory

    R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY CHAPTER 21 FLASH MEMORY The R7F0C30x, R7F0C31x incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 21.1 Internal Memory Size Switching Register Select the internal memory capacity using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction.

  • Page 402: Writing With Flash Memory Programmer

    R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY Table 21-1. Set Values of Internal Memory Size Switching Register Products IMS Setting R7F0C3004, R7F0C3034, R7F0C3006, R7F0C3036, R7F0C3064, R7F0C3094, R7F0C3066, R7F0C3096 R7F0C3014, R7F0C3044, R7F0C3016, R7F0C3046, R7F0C3084, R7F0C3114, R7F0C3086, R7F0C3116 R7F0C3024, R7F0C3054, R7F0C3026, R7F0C3056, R7F0C3074, R7F0C3104, R7F0C3076, R7F0C3106 21.2 Writing with Flash Memory Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.

  • Page 403: Programming Environment

    R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY 21.3 Programming Environment The environment required for writing a program to the flash memory of the R7F0C30x, R7F0C31x are illustrated below. Figure 21-2. Environment for Writing Program to Flash Memory QB-MINI2 FlashPro5 RS-232-C /RESET RESET R7F0C30x, TOOLD0...

  • Page 404: Connection Of Pins On Board

    R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY 21.4 Connection of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.

  • Page 405: Reset Pin

    R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY 21.4.2 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator.

  • Page 406: On-Board Writing When Connecting Crystal/Ceramic Resonator

    R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY 21.4.7 On-board writing when connecting crystal/ceramic resonator To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.

  • Page 407: Programming Method

    R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY 21.5 Programming Method 21.5.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 21-6. Flash Memory Manipulation Procedure Start Flash memory programming mode is set Manipulate flash memory End? 21.5.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the R7F0C30x,...
  • Page 408 R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY Table 21-5. Flash Memory Control Commands Classification Command Name Function Verify Verify Compares the contents of a specified area of the flash memory with data transmitted from the programmer. Erase Chip Erase Erases the entire flash memory. Block Erase Erases a specified area in the flash memory.

  • Page 409: Security Settings

    R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY 21.6 Security Settings The R7F0C30x, R7F0C31x support a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. The security setting is valid when the programming mode is set next.
  • Page 410 R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY Table 21-7. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Batch Erase (Chip Erase) Block Erase Write Note Prohibition of batch erase (chip erase) Cannot be erased in batch Blocks cannot be Can be performed erased.

  • Page 411: Flash Memory Programming By Self Programming

    R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY 21.7 Flash Memory Programming by Self Programming The R7F0C30x, R7F0C31x support a self programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the R7F0C30x, R7F0C31x self programming library, it can be used to upgrade the program in the field.

  • Page 412: Register Controlling Self Programming Mode

    R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY 21.7.1 Register controlling self programming mode The self programming mode is controlled by the self programming mode control register (FPCTL). FPCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears FPCTL to 00H. Figure 21-8.
  • Page 413 R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY Figure 21-9. Flow of Self Programming (Rewriting Flash Memory) Start of self programming Setting FLMDPUP to 1 FlashStart Setting operating environment FlashEnv CheckFLMD FlashBlockBlankCheck Normal completion? FlashBlockErase FlashWordWrite FlashBlockVerify Normal completion? FlashBlockErase FlashWordWrite FlashBlockVerify Normal completion? Normal completion...

  • Page 414: Boot Swap Function

    R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY 21.7.3 Boot swap function If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or overwriting is disabled due to data destruction in the boot area. The boot swap function is used to avoid this problem.
  • Page 415 R7F0C30x, R7F0C31x CHAPTER 21 FLASH MEMORY Figure 21-11. Example of Executing Boot Swapping Block number Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7 Program Program Program Program Program Program Program Boot Program cluster 1 Program Program 1 0 0 0 H Boot program Boot program...

  • Page 416: Chapter 22 On-Chip Debug Function

    Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
  • Page 417 R7F0C30x, R7F0C31x CHAPTER 22 ON-CHIP DEBUG FUNCTION Figure 22-1. Connection Example of QB-MINI2 and R7F0C30x, R7F0C31x (1/2) (1) When using the TOOLC0 and TOOLD0 pins (X1 oscillator or EXCLK input clock is not used, both debugging and programming are performed) Target connector Target device 3 k to 10 k...
  • Page 418 R7F0C30x, R7F0C31x CHAPTER 22 ON-CHIP DEBUG FUNCTION Figure 22-1. Connection Example of QB-MINI2 and R7F0C30x, R7F0C31x (2/2) (2) When using the TOOLC0 and TOOLD0 pins (with X1/X2 oscillator is used, both debugging and programming are performed) Target connector Target device Note 1 RESET_OUT RESET...

  • Page 419: On-Chip Debug Security Id

    R7F0C30x, R7F0C31x CHAPTER 22 ON-CHIP DEBUG FUNCTION 22.2 On-Chip Debug Security ID The R7F0C30x, R7F0C31x have an on-chip debug operation control bit in the flash memory at 0084H (refer to CHAPTER 20 OPTION BYTE) and an on-chip debug security ID setting area at 0085H to 008EH, to prevent third parties from reading memory content.

  • Page 420: Securing Of User Resources

    R7F0C30x, R7F0C31x CHAPTER 22 ON-CHIP DEBUG FUNCTION 22.3 Securing of User Resources QB-MINI2 uses the user memory spaces (shaded portions in Figure 22-2) to implement communication with the target device, or each debug functions. The areas marked with a dot (•) are always used for debugging, and other areas are used for each debug function used.

  • Page 421: Chapter 23 Instruction Set

    R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET CHAPTER 23 INSTRUCTION SET This chapter lists each instruction set of the R7F0C30x, R7F0C31x in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 23.1 Conventions Used in Operation List 23.1.1 Operand identifiers and specification methods Operands are written in the “Operand”...

  • Page 422: Description Of Operation Column

    R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET 23.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer...

  • Page 423: Operation List

    R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET 23.2 Operation List Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2  r  byte 8-bit data r, #byte transfer (saddr)  byte saddr, #byte  sfr  byte sfr, #byte ...
  • Page 424 R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2  rp  word 16-bit data MOVW rp, #word transfer (saddrp)  word saddrp, #word  sfrp  word sfrp, #word AX ...
  • Page 425 R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2  A, CY  A  byte    8-bit A, #byte operation (saddr), CY  (saddr)  byte ...
  • Page 426 R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2  A  A  byte  8-bit A, #byte operation (saddr)  (saddr)  byte  saddr, #byte ...
  • Page 427 R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2  AX, CY  AX + word    16-bit ADDW AX, #word operation  AX, CY  AX  word ...
  • Page 428 R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 CY  CY  (saddr.bit)  AND1 CY, saddr.bit manipulate  CY  CY  sfr.bit  CY, sfr.bit ...
  • Page 429 R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2  (SP  1)  (PC + 3) , (SP  2)  (PC + 3) Call/return CALL !addr16 PC ...
  • Page 430 R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 PC  PC + 3 + jdisp8 if (saddr.bit) = 1 Conditional saddr.bit, $addr16 branch  PC  PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 ...

  • Page 431: Instructions Listed By Addressing Type

    R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET 23.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note Second Operand #byte saddr !addr16...
  • Page 432 R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH...
  • Page 433 R7F0C30x, R7F0C31x CHAPTER 23 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...

  • Page 434: Chapter 24 Electrical Specifications

    Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.

  • Page 435: Absolute Maximum Ratings

    R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25C) (1/2) Parameter Symbols Conditions Ratings Unit 0.5 to + 6.5 Supply voltage 0.5 to + 0.3 0.5 to V Note 1 + 0.3 0.5 to + 3.6 REGC pin input voltage IREGC Note 2 and 0.5 to V...
  • Page 436 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25C) (2/2) Parameter Symbols Conditions Ratings Unit 10 Output current, high Per pin P31 to P34 25 Total of all pins 10 Per pin 10 Total of all pins 0.5 Per pin P20 to P27...
  • Page 437 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS X1 Oscillator Characteristics = 40 to +85C, 1.8 V  V  5.5 V, V = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit 2.7 V  V  5.5 V Ceramic X1 clock 10.0...
  • Page 438 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS Internal High-speed Oscillator Characteristics = 40 to +85C, 1.8 V  V  5.5 V, V = 0 V) Resonator Parameter Conditions MIN. TYP. MAX. Unit = 20 to +70C (2%) Internal high-speed Oscillation frequency RSTS = 1 Package 7.84...
  • Page 439 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS DC Characteristics (1/6) (16-pin products) = 40 to +85C, 1.8 V  V  5.5 V, AV  V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V  V  5.5 V 3.0 Note 1 Output current, high...
  • Page 440 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS DC Characteristics (2/6) (20-pin products) = 40 to +85C, 1.8 V  V  5.5 V, AV  V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V  V  5.5 V 3.0 Note 1 Output current, high...
  • Page 441 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS DC Characteristics (3/6) = 40 to +85C, 1.8 V  V  5.5 V, AV  V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note Input voltage, high P122 , P31 0.7V P20 to P27 0.7AV...
  • Page 442 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS DC Characteristics (4/6) = 40 to +85C, 1.8 V  V  5.5 V, AV  V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit  Input leakage current, P30 to P34, P125/RESET LIH1 high ...
  • Page 443 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS DC Characteristics (5/6) = 40 to +85C, 1.8 V  V  5.5 V, AV  V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note Supply current Operating = 10 MHz Square wave input mode Resonator connection...
  • Page 444 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS DC Characteristics (6/6) = 40 to +85C, 1.8 V  V  5.5 V, AV  V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit  Watchdog timer In 240 kHz internal low-speed oscillation = 3.0 V Note 1 operating current...
  • Page 445 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS AC Characteristics (1) Basic operation = 40 to +85C, 1.8 V  V  5.5 V, V = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit  2.7 V  V  5.5 V Instruction cycle (minimum Main instruction execution time)
  • Page 446 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS vs. V (Main System Clock Operation) Guaranteed operation range 0.01 Supply voltage V AC Timing Test Points 0.8V 0.8V Test points 0.2V 0.2V R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 447 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS External Main System Clock Timing EXCLK EXCLKL EXCLKH 0.7V (MIN.) EXCLK 0.3V (MAX.) TI Timing TIL0 TIH0 TI000, TI010 TIL5 TIH5 TI51 Interrupt Request Input Timing INTL INTH INTP0, INTP1 RESET Input Timing RESET R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 448 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS (2) Serial interface = 40 to +85C, 1.8 V  V  5.5 V, V = 0 V) (a) UART0 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate 312.5 kbps (b) OCD (UART0)
  • Page 449 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS Analog Characteristics (1) A/D Converter (for Package SSOP Product) = 40 to +85C, 2.3 V  AV  V  5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 4.0 V ...
  • Page 450 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS (3) Operational amplifier 0, 1 = 40 to +85C, 2.2 V  V  5.5 V, 2.2 V  AV  5.5 V, V = 0 V, Output load: R = 47 k, C = 50 pF) Parameter Symbol...
  • Page 451 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS (4) CMP = 40 to +85C, 2.7 V  V  AV  5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 5 40 Input offset voltage IOCMP Input voltage range CMPIN ICMP CMPCOM...
  • Page 452 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS (6) Supply Voltage Rise Time = 40 to +85C, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note Maximum time to rise to 1.8 V (V (MIN.)) LVI default start function stopped is PUP1 : 0 V ...
  • Page 453 R7F0C30x, R7F0C31x CHAPTER 24 ELECTRICAL SPECIFICATIONS (7) LVI = 40 to +85C, V  V  5.5 V, V =0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection Supply voltage level 4.240.1 LVI0 voltage 4.090.1 LVI1 3.930.1 LVI2 3.780.1 LVI3 3.620.1 LVI4...

  • Page 454: Flash Memory Programming Characteristics

    Note chip 1 rewrite the self-programming libraries provided by Renesas Electronics are used When a flash memory programmer is used: 10 to 40 C, during self-programming: 40 to +85 C Operating temperature Note When a product is first written after shipment, “erase  write” and “write only” are both taken as one rewrite.

  • Page 455: Chapter 25 Package Drawings

    0.20 1.725 MAX. 0.125 ± 0.05 1.50 0.25 0.65 0.08 0.22 0.07 0.03 0.15 0.04 0.50 0.60 ± 0.10 ± 1.00 0.20 0.13 0.10 5° 3° 3° 0.325 2012 Renesas Electronics Corporation. All rights reserved. R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 456 R7F0C30x, R7F0C31x CHAPTER 25 PACKAGE DRAWINGS  R7F0C30642ESN, R7F0C30942ESN, R7F0C30742ESN, R7F0C31042ESN, R7F0C30842ESN, R7F0C31142ESN JEITA Package code RENESAS code Previous code MASS(TYP.)[g] P-SOP16-3.9x9.9-1.27 PRSP0016DP-A T16MF-127-DAA 0.15 detail of lead end θ Dimension in Millimeters Referance Symbol Terminal cross section 9.90 9.70 10.10...

  • Page 457: 20-Pin Products

    (T.P. ) at maximum material 1.30±0.10 condition. 1.20 8.10±0.20 6.10±0.10 1.00±0.20 0.15 +0.05 −0.01 0.50 0.13 0.10 +5° 3° −3° 0.25(T. P) 0.60±0.15 0.25 MAX. 0.15 MAX. P20MC-65-CAA-1 2010 Renesas Electronics Corporation. All rights reserved . R01UH0389EJ0120 Rev.1.20 Oct 09, 2014...
  • Page 458 R7F0C30x, R7F0C31x CHAPTER 25 PACKAGE DRAWINGS  R7F0C30662ESN, R7F0C30962ESN, R7F0C30762ESN, R7F0C31062ESN, R7F0C30862ESN, R7F0C31162ESN JEITA Package code RENESAS code Previous code MASS(TYP.)[g] P-SOP20-7.5x12.8-1.27 PRSP0020DP-A T20MR-127-PAB 0.54 detail of lead end θ Dimension in Millimeters Referance Symbol Terminal cross section 12.60 12.80 13.00...

  • Page 459: Chapter 26 Cautions For Wait

    R7F0C30x, R7F0C31x CHAPTER 26 CAUTIONS FOR WAIT CHAPTER 26 CAUTIONS FOR WAIT 26.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.

  • Page 460: Peripheral Hardware That Generates Wait

    R7F0C30x, R7F0C31x CHAPTER 26 CAUTIONS FOR WAIT 26.2 Peripheral Hardware That Generates Wait Table 26-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 26-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Register Access...

  • Page 461: Appendix A Revision History

    R7F0C30x, R7F0C31x APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY A.1 Major Revisions in This Edition Page Description Classification CHAPTER 2 PIN FUNCTIONS p.14 Addition of note to (2) Non-port functions: 20-pin products CHAPTER 4 PORT FUNCTIONS p.41 Modification of error of Table 3-6. Special Function Register List (2/4) p.74 Addition of caution to 4.2.2 Port 3 p.88...

  • Page 462: Revision History Of Preceding Editions

    R7F0C30x, R7F0C31x APPENDIX A REVISION HISTORY A.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/1) Edition Description Chapter Throughout Rev.1.10 Addition of SOP package CHAPTER 1 Addition of descriptions to 1.2 List of Part Numbers OUTLINE CHAPTER 2 PIN...
  • Page 463 R7F0C30x, R7F0C31x User’s Manual: Hardware Publication Date: Rev.1.20 Oct 09, 2014 Published by: Renesas Electronics Corporation...

  • Page 464: Sales Offices

    SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada...
  • Page 465 R7F0C30x, R7F0C31x R01UH0389EJ0120...

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