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Renesas RX24T RX200 Series User Manual

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RX24T Group

32

RENESAS 32-Bit MCU

RX Family / RX200 Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.1.00

Nov 2015

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Summary of Contents for Renesas RX24T RX200 Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
Page 4: General Precautions In The Handling Of Mpu/Mcu Products
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 5: How To Use This Manual
RX Family R01AN1411EJ Hardware Design Guide Examples of register initial setting RX24T Group R01AN2837EJ Initial Setting Examples Examples of applications and sample programs — — Renesas Technical Preliminary report on the specifications of a product, — — Update document, etc.
Page 6: Description Of Registers
2. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. X.X.X ...
Page 7: List Of Abbreviations And Acronyms
3. List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communications Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus Input/Output IrDA Infrared Data Association...
Page 8: Table Of Contents
Contents Features ..............................35 Overview ............................36 Outline of Specifications ........................36 List of Products ............................ 41 Block Diagram ............................. 42 Pin Functions ............................43 Pin Assignments ..........................46 CPU ............................... 53 Features ..............................53 Register Set of the CPU ........................54 2.2.1 General-Purpose Registers (R0 to R15) ..................
Page 9 2.6.1 Exception Vector Table ......................72 2.6.2 Interrupt Vector Table ........................ 73 Operation of Instructions ........................74 2.7.1 Restrictions on RMPA and String-Manipulation Instructions ........... 74 2.7.1.1 Transfer Size and Data Prefetching ................... 74 2.7.1.2 Access to I/O Registers ..................... 74 Number of Cycles ..........................
Page 10 Register Descriptions ......................... 125 7.2.1 Option Function Select Register 0 (OFS0) ................125 7.2.2 Option Function Select Register 1 (OFS1) ................127 7.2.3 Endian Select Register (MDE) ....................128 Usage Note ............................128 7.3.1 Setting Example of Option-Setting Memory ................128 Voltage Detection Circuit (LVDAb) ....................
Page 11 9.3.1 Connecting a Crystal ........................ 165 9.3.2 External Clock Input ......................... 166 9.3.3 Notes on the External Clock Input ................... 166 Oscillation Stop Detection Function ....................167 9.4.1 Oscillation Stop Detection and Operation after Detection ............167 9.4.2 Oscillation Stop Detection Interrupts ..................168 PLL Circuit ............................
Page 12 11.2.5 Operating Power Control Register (OPCCR) ................190 11.3 Reducing Power Consumption by Switching Clock Signals ............. 193 11.4 Module Stop Function ........................193 11.5 Function for Lower Operating Power Consumption ................. 193 11.5.1 Setting Operating Power Control Mode ................... 193 11.6 Low Power Consumption Modes ......................
Page 13 13.5 Hardware Pre-Processing ........................212 13.5.1 Undefined Instruction Exception ....................212 13.5.2 Privileged Instruction Exception ....................212 13.5.3 Access Exceptions ........................212 13.5.4 Floating-Point Exception ......................212 13.5.5 Reset ............................212 13.5.6 Non-Maskable Interrupt ......................213 13.5.7 Interrupt ............................ 213 13.5.8 Unconditional Trap ........................
Page 14 14.4.6 Fast Interrupt ..........................244 14.4.7 Digital Filter ..........................244 14.4.8 External Pin Interrupts ......................244 14.5 Non-maskable Interrupt Operation ....................246 14.6 Return from Power-Down States ....................... 247 14.6.1 Return from Sleep Mode or Deep Sleep Mode ................ 247 14.6.2 Return from Software Standby Mode ..................
Page 15 16.2.1 Region-n Start Page Number Register (RSPAGEn) (n = 0 to 7) ..........266 16.2.2 Region-n End Page Number Register (REPAGEn) (n = 0 to 7) ..........267 16.2.3 Memory-Protection Enable Register (MPEN) ................. 268 16.2.4 Background Access Control Register (MPBAC) ..............269 16.2.5 Memory-Protection Error Status-Clearing Register (MPECLR) ..........
Page 16 17.4.3 Normal Transfer Mode ......................300 17.4.4 Repeat Transfer Mode ......................301 17.4.5 Block Transfer Mode ........................ 302 17.4.6 Chain Transfer .......................... 303 17.4.7 Operation Timing ........................304 17.4.8 Execution Cycles of the DTC ....................307 17.4.9 DTC Bus Mastership Release Timing ..................307 17.5 DTC Setting Procedure ........................
Page 17 19.2.9 P7n Pin Function Select Register (P7nPFS) (n = 0 to 6) ............342 19.2.10 P8n Pin Function Select Register (P8nPFS) (n = 0 to 2) ............343 19.2.11 P9n Pin Function Select Register (P9nPFS) (n = 0 to 6) ............344 19.2.12 PAn Pin Function Select Register (PAnPFS) (n = 0 to 5) ............
Page 18 20.2.27 Timer Cycle Data Registers (TCDRA, TCDRB) ..............412 20.2.28 Timer Cycle Buffer Registers (TCBRA, TCBRB) ..............413 20.2.29 Timer Dead Time Data Registers (TDDRA, TDDRB) ............413 20.2.30 Timer Dead Time Enable Registers (TDERA, TDERB) ............414 20.2.31 Timer Buffer Transfer Set Registers (TBTERA, TBTERB) ............ 415 20.2.32 Timer Waveform Control Registers (TWCRA, TWCRB) ............
Page 19 20.4.3 A/D Converter Activation ......................534 20.5 Operation Timing ..........................536 20.5.1 Input/Output Timing ......................... 536 20.5.2 Interrupt Signal Timing ......................542 20.6 Usage Notes ............................545 20.6.1 Module Stop Function Setting ....................545 20.6.2 Input Clock Restrictions ......................545 20.6.3 Note on Cycle Setting .......................
Page 20 21.2 Register Descriptions ......................... 592 21.2.1 Input Level Control/Status Register 1 (ICSR1) ................ 592 21.2.2 Input Level Control/Status Register 2 (ICSR2) ................ 593 21.2.3 Input Level Control/Status Register 3 (ICSR3) ................ 594 21.2.4 Input Level Control/Status Register 4 (ICSR4) ................ 595 21.2.5 Input Level Control/Status Register 5 (ICSR5) ................
Page 21 22.2.4 Timer Control Register (TCR) ....................650 22.2.5 Timer Counter Control Register (TCCR) ................. 651 22.2.6 Timer Control/Status Register (TCSR) ..................653 22.3 Operation ............................655 22.3.1 Pulse Output ..........................655 22.3.2 External Counter Reset Input ....................656 22.4 Operation Timing ..........................657 22.4.1 TCNT Count Timing ........................
Page 22 23.4.1 Interrupt Sources ........................674 23.4.2 Timing of Compare Match Interrupt Generation ..............674 23.5 Usage Notes ............................675 23.5.1 Setting the Module Stop Function .................... 675 23.5.2 Conflict between CMCNT Counter Writing and Compare Match ........... 675 23.5.3 Conflict between CMCNT Counter Writing and Incrementing ..........675 Independent Watchdog Timer (IWDTa) ..................
Page 23 25.2.10 Smart Card Mode Register (SCMR) ..................717 25.2.11 Bit Rate Register (BRR) ......................719 25.2.12 Modulation Duty Register (MDDR) ..................727 25.2.13 Serial Extended Mode Register (SEMR) .................. 728 25.2.14 Noise Filter Setting Register (SNFR) ..................731 25.2.15 C Mode Register 1 (SIMR1) ....................732 25.2.16 C Mode Register 2 (SIMR2) ....................
Page 24 25.7.3 SSDA Output Delay ......................... 784 25.7.4 SCI Initialization (Simple I C Mode) ..................785 25.7.5 Operation in Master Transmission (Simple I C Mode) ............786 25.7.6 Master Reception (Simple I C Mode) ..................788 25.8 Operation in Simple SPI Mode ......................790 25.8.1 States of Pins in Master and Slave Modes ................
Page 25 26.2.7 C-bus Status Enable Register (ICSER) ................. 822 26.2.8 C-bus Interrupt Enable Register (ICIER) ................824 26.2.9 C-bus Status Register 1 (ICSR1) ................... 826 26.2.10 C-bus Status Register 2 (ICSR2) ................... 829 26.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2) ..............832 26.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2) ..............
Page 26 26.11.3 RIIC Reset and Internal Reset ....................875 26.12 SMBus Operation ..........................876 26.12.1 SMBus Timeout Measurement ....................876 26.12.2 Packet Error Code (PEC) ......................877 26.12.3 SMBus Host Notification Protocol (Notify ARP Master Command) ........877 26.13 Interrupt Sources ..........................878 26.13.1 Buffer Operation for TXI and RXI Interrupts ................
Page 27 27.3.4.1 When Parity is Disabled (SPCR2.SPPE = 0) ..............917 27.3.4.2 When Parity is Enabled (SPCR2.SPPE = 1) ..............921 27.3.5 Transfer Format ........................925 27.3.5.1 CPHA = 0 ........................925 27.3.5.2 CPHA = 1 ........................926 27.3.6 Communications Operating Mode .................... 927 27.3.6.1 Full-Duplex Synchronous Serial Communications (SPCR.TXMD = 0) ......
Page 28 12-Bit A/D Converter (S12ADF) ....................968 29.1 Overview ............................968 29.2 Register Descriptions ......................... 977 29.2.1 A/D Data Registers y (ADDRy) A/D Data Duplication Register (ADDBLDR) A/D Data Duplication Register A (ADDBLDRA) A/D Data Duplication Register B (ADDBLDRB) A/D Internal Reference Voltage Data Register (ADOCDR) ............ 977 29.2.2 A/D Self-Diagnosis Data Register (ADRD) ................
Page 29 29.3.3.2 Basic Operation (With Channel-Dedicated Sample-and-Hold Circuits) ....... 1030 29.3.3.3 Channel Selection and Self-Diagnosis (Without Channel-Dedicated Sample-and-Hold Circuits) ..........1031 29.3.3.4 Channel Selection and Self-Diagnosis (With Channel-Dedicated Sample-and-Hold Circuits) ..........1032 29.3.4 Group Scan Mode ........................1033 29.3.4.1 Basic Operation ......................1033 29.3.4.2 A/D Conversion in Double Trigger Mode ..............
Page 30 30.4.4 Setting the D/A Converter ...................... 1069 Comparator C (CMPC) ......................1070 31.1 Overview ............................1070 31.2 Register Descriptions ........................1073 31.2.1 Comparator Control Register (CMPCTL) ................1073 31.2.2 Comparator Input Select Register (CMPSEL0) ..............1074 31.2.3 Comparator Reference Voltage Select Register (CMPSEL1) ..........1075 31.2.4 Comparator Output Monitor Register (CMPMON) ...............
Page 31 34.3 E2 DataFlash Area and Block Configuration .................. 1092 34.4 Register Descriptions ........................1093 34.4.1 E2 DataFlash Control Register (DFLCTL) ................1093 34.4.2 Flash P/E Mode Entry Register (FENTRYR) ................ 1094 34.4.3 Protection Unlock Register (FPR) ..................1095 34.4.4 Protection Unlock Status Register (FPSR) ................1095 34.4.5 Flash P/E Mode Control Register (FPMCR) ................
Page 32 34.7.4.2 Block Erase ........................1125 34.7.4.3 All-Block Erase ......................1127 34.7.4.4 Blank Check ........................1129 34.7.4.5 Start-Up Area Information Program/Access Window Information Program ....1131 34.7.4.6 Forced Stop of Software Commands ................1132 34.7.5 Interrupt ..........................1132 34.8 Boot Mode ............................1133 34.8.1 Boot Mode (SCI) ........................
Page 33 34.10.9.1 Memory Read ........................ 1155 34.10.9.2 User Area Checksum ..................... 1156 34.10.9.3 Data Area Checksum ..................... 1156 34.10.9.4 User Area Blank Check ....................1156 34.10.9.5 Data Area Blank Check ....................1157 34.10.9.6 Access Window Information Program ................1158 34.10.9.7 Access Window Read ....................1159 34.11 Serial Programmer Operation in Boot Mode (SCI) .................
Page 34 35.10 ROM (Flash Memory for Code Storage) Characteristics ..............1219 35.11 E2 DataFlash Characteristics ......................1221 35.12 Usage Notes ............................. 1222 35.12.1 Connecting VCL Capacitor and Bypass Capacitors ............... 1222 Appendix 1. Port States in Each Processing Mode ................1224 Appendix 2.
Page 35: Features
RX24T Group R01UH0576EJ0100 Rev.1.00 Renesas MCUs Nov 30, 2015 80-MHz 32-bit RX MCUs, built-in FPU, 153.6 DMIPS, 12-bit ADC (equipped with three S/H circuits, double data registers, amplifier, and comparator) 80MHz PWM (three-phase complementary output × 2 channels) Features ■ 32-bit RXv2 CPU core ...
Page 36: Overview
RX24T Group 1. Overview Overview Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type.
Page 37 RX24T Group 1. Overview Table 1.1 Outline of Specifications (2/4) Classification Module/Function Description  Interrupt vectors: 120 Interrupt Interrupt controller (ICUb)  External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)  Non-maskable interrupts: 5 (NMI pin, oscillation stop detection interrupt, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and IWDT interrupt) ...
Page 38 RX24T Group 1. Overview Table 1.1 Outline of Specifications (3/4) Classification Module/Function Description  3 channels (channel 1, 5 and 6: SCIg) Communication Serial communications  SCIg functions interfaces (SCIg) Serial communications modes: Asynchronous, clock synchronous, and smart-card interface Multi-processor function On-chip baud rate generator allows selection of the desired bit rate Choice of LSB-first or MSB-first transfer Average transfer rate clock can be input from TMR timers for SCI5 and SCI6...
Page 39 RX24T Group 1. Overview Table 1.1 Outline of Specifications (4/4) Classification Module/Function Description  Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to FFFF FFFFh. Safety Memory protection unit  Minimum protection unit: 16 bytes (MPU) ...
Page 40 RX24T Group 1. Overview Table 1.2 Comparison of Functions for Different Packages RX24T Group Module/Functions 100 Pins 80 Pins Interrupts External interrupts NMI, IRQ0 to IRQ7 Data transfer controller Available Timers Multi-function timer pulse unit 3 9 channels Port output enable 3 POE0#, POE4#, POE8#, POE10#, POE11#, POE12# 8-bit timer 2 channels ×...
Page 41: List Of Products
8: 128 Kbytes/16 Kbytes/8 Kbytes Group name 4T: RX24T Group Series name RX200 Series Type of memory F: Flash memory version Renesas MCU Renesas semiconductor product Figure 1.1 How to Read the Product Part Number R01UH0576EJ0100 Rev.1.00 Page 41 of 1230 Nov 30, 2015...
Page 42: Block Diagram
RX24T Group 1. Overview Block Diagram Figure 1.2 shows a block diagram. E2 DataFlash IWDTa SCIg × 3 channels RSPIb × 1 channel RIICa × 1 channel POE3b TMR × 2 channels (unit 0) TMR × 2 channels (unit 1) TMR ×...
Page 43: Pin Functions
RX24T Group 1. Overview Pin Functions Table 1.4 lists the pin functions. Table 1.4 Pin Functions (1/3) Classifications Pin Name Description Power supply — Power supply pin. Connect it to the system power supply. Connect this pin to the VSS pin via the 4.7 μF smoothing capacitor used to —...
Page 44 RX24T Group 1. Overview Table 1.4 Pin Functions (2/3) Classifications Pin Name Description  Simple I Serial C mode communications SSCL1, SSCL5, SSCL6 Input/output pins for the I C clock. interface (SCIg) SSDA1, SSDA5, SSDA6 Input/output pins for the I C data.
Page 45 RX24T Group 1. Overview Table 1.4 Pin Functions (3/3) Classifications Pin Name Description I/O ports P00 to P02 3-bit input/output pins. P10, P11 2-bit input/output pins. P20 to P24 5-bit input/output pins. P30 to P33 4-bit input/output pins. P40 to P47 8-bit input/output pins.
Page 46: Pin Assignments
RX24T Group 1. Overview Pin Assignments Figure 1.3 to Figure 1.5 show the pin assignments. Table 1.5 and Table 1.6 show the lists of pins and pin functions. RX24T Group PLQP0100KB-A (100-pin LFQFP) (Upper perspective view) AVCC1 AVCC0 AVSS0 AVSS1 Note: This figure indicates the power supply pins and I /O port pins.
Page 47 RX24T Group 1. Overview RX24T Group PLQP0080JA-A (80-pin LQFP) (Upper perspective view) AVCC1 AVCC0 AVSS0 AVSS1 Note: This figure indicates the power supply pins and I /O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (80-Pin LQFP)”. Figure 1.4 Pin Assignments of the 80-Pin LQFP R01UH0576EJ0100 Rev.1.00...
Page 48 RX24T Group 1. Overview RX24T Group PLQP0080KB-A (80-pin LFQFP) (Upper perspective view) AVCC1 AVCC0 AVSS0 AVSS1 Note: This figure indicates the power supply pins and I /O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (80-Pin LFQFP)”. Figure 1.5 Pin Assignments of the 80-Pin LFQFP R01UH0576EJ0100 Rev.1.00...
Page 49 RX24T Group 1. Overview Table 1.5 List of Pins and Pin Functions (100-Pin LFQFP) (1/2) Power Supply, Clock, System Timers Communications Control I/O Port (MTU, TMR, POE, CAC) (SCIg, RSPI, RIIC) Others IRQ0 MTIOC9D CTS1#, RTS1#, SS1# IRQ5, ADST0 IRQ2, ADST1 FINED POE12# IRQ4, ADST2...
Page 50 RX24T Group 1. Overview Table 1.5 List of Pins and Pin Functions (100-Pin LFQFP) (2/2) Power Supply, Clock, System Timers Communications Control I/O Port (MTU, TMR, POE, CAC) (SCIg, RSPI, RIIC) Others MTIOC4A MTIOC3B POE0# IRQ5 MTIOC3A, MTCLKA, TMO0 SSLA3 MTIOC3C, MTCLKB, TMO6 SSLA2 MTIOC0A, MTCLKC, TMRI6...
Page 51 RX24T Group 1. Overview Table 1.6 List of Pins and Pin Functions (80-Pin LQFP/LFQFP) (1/2) Power Supply, Clock, System Timers Communications Control I/O Port (MTU, TMR, POE, CAC) (SCIg, RSPI, RIIC) Others MTIOC9D CTS1#, RTS1#, SS1# IRQ5, ADST0 IRQ2, ADST1 FINED POE12# IRQ4, ADST2...
Page 52 RX24T Group 1. Overview Table 1.6 List of Pins and Pin Functions (80-Pin LQFP/LFQFP) (2/2) Power Supply, Clock, System Timers Communications Control I/O Port (MTU, TMR, POE, CAC) (SCIg, RSPI, RIIC) Others MTIOC0A, MTCLKC, TMRI6 SSLA1 IRQ6 MTIOC0B, MTCLKD, TMCI6 SSLA0 IRQ7, COMP3 MTIC5U, TMCI2, TMO6...
Page 53: Cpu
RX24T Group 2. CPU The RXv2 instruction set architecture (RXv2) has upward compatibility with the RXv1 instruction set architecture (RXv1).  Adoption of variable-length instruction format As with RXv1, the RXv2 CPU has short formats for frequently used instructions, facilitating the development of efficient programs that take up less memory.
Page 54: Register Set Of The Cpu
RX24T Group 2. CPU Register Set of the CPU The RXv2 CPU has sixteen general-purpose registers, ten control registers, and two accumulator used for DSP instructions. Control register General-purpose register ISP (Interrupt stack pointer) R0 (SP) USP (User stack pointer) INTB (Interrupt table register) PC (Program counter) PSW (Processor status word)
Page 55: General-Purpose Registers (R0 To R15)
RX24T Group 2. CPU 2.2.1 General-Purpose Registers (R0 to R15) This CPU has sixteen 32-bit general-purpose registers (R0 to R15). R0 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW).
Page 56: Interrupt Stack Pointer (Isp)/User Stack Pointer (Usp)
RX24T Group 2. CPU 2.2.2.1 Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) Value after reset: Value after reset: The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP). Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the processor status word (PSW).
Page 57: Processor Status Word (Psw)
RX24T Group 2. CPU 2.2.2.5 Processor Status Word (PSW) — — — — IPL[3:0] — — — — — Value after reset: — — — — — — — — — — — — Value after reset: Symbol Bit Name Description Carry Flag 0: No carry has occurred.
Page 58: Backup Pc (Bpc)
RX24T Group 2. CPU C Flag (Carry Flag) This flag retains the state of the bit after a carry, borrow, or shift-out has occurred. Z Flag (Zero Flag) This flag is set to 1 if the result of an operation is 0; otherwise its value is cleared to 0. S Flag (Sign Flag) This flag is set to 1 if the result of an operation is negative;...
Page 59: Backup Psw (Bpsw)
RX24T Group 2. CPU 2.2.2.7 Backup PSW (BPSW) Undefined Value after reset: The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW.
Page 60: Floating-Point Status Word (Fpsw)
RX24T Group 2. CPU 2.2.2.9 Floating-Point Status Word (FPSW) — — — — — — — — — — Value after reset: — — RM[1:0] Value after reset: Symbol Bit Name Description b1, b0 RM[1:0] Floating-Point Rounding-Mode b1 b0 0 0: Rounding towards the nearest value Setting 0 1: Rounding towards 0 1 0: Rounding towards +∞...
Page 61 RX24T Group 2. CPU Symbol Bit Name Description Floating-Point Error Summary Flag This bit reflects the logical OR of the FU, FZ, FO, and FV flags. Note 1. Writing 0 to the bit clears it. Writing 1 to the bit does not affect its value. Note 2.
Page 62: Accumulator
RX24T Group 2. CPU operation instruction, the bit decides whether the CPU will start handling the exception. When the bit is set to 0, the exception handling is masked; when the bit is set to 1, the exception handling is enabled. FV Flag (Invalid Operation Flag), FO Flag (Overflow Flag), FZ Flag (Division-by-Zero Flag), FU Flag (Underflow Flag), and FX Flag (Inexact Flag) While the exception handling enable bit (Ej) is 0 (exception handling is masked), if any of five floating-point exceptions...
Page 63: Processor Mode
RX24T Group 2. CPU Processor Mode The RXv2 CPU supports two processor modes, supervisor and user. These processor modes and the memory protection function enable the realization of a hierarchical CPU resource protection and memory protection mechanism. Each processor mode imposes a level on rights of access to memory and the instructions that can be executed. Supervisor mode carries greater rights than user mode.
Page 64: Data Types
RX24T Group 2. CPU Data Types The RXv2 CPU can handle four types of data: integer, floating-point, bit, and string. For details, refer to RX Family RXv2 Instruction Set Architecture User's Manual: Software. 2.4.1 Integer An integer can be signed or unsigned. For signed integers, negative values are represented by two's complements. Signed byte (8-bit) integer Unsigned byte (8-bit) integer Signed word (16-bit) integer...
Page 65: Floating-Points
RX24T Group 2. CPU 2.4.2 Floating-Points Floating-point support is for the single-precision floating-point type specified in the IEEE754 standard; operands of this type can be used in eleven floating-point operation instructions: FADD, FCMP, FDIV, FMUL, FSQRT, FSUB, FTOI, FTOU, ITOF, ROUND, and UTOF. Single-precision floating-point S: Sign (1 bit) E: Exponent (8 bits)
Page 66: Strings
RX24T Group 2. CPU 2.4.4 Strings The string data type consists of an arbitrary number of consecutive byte (8-bit), word (16-bit), or longword (32-bit) units. Seven string manipulation instructions are provided for use with strings: SCMPU, SMOVB, SMOVF, SMOVU, SSTR, SUNTIL, and SWHILE.
Page 67: Endian
RX24T Group 2. CPU Endian For the RXv2 CPU, instructions are little endian, but the treatment of data is selectable as little or big endian. 2.5.1 Switching the Endian As arrangements of bytes, this MCU supports both big endian, where the higher-order byte (MSB) is at location 0, and little endian, where the lower-order byte (LSB) is at location 0.
Page 68 RX24T Group 2. CPU Table 2.3 32-Bit Write Operations when Little Endian has been Selected Operation Address Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit of dest to address 0 to address 1 to address 2 to address 3...
Page 69 RX24T Group 2. CPU Table 2.6 16-Bit Read Operations when Big Endian has been Selected Operation Reading Reading Reading Reading Reading Reading Reading Address a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from...
Page 70: Access To I/O Registers
RX24T Group 2. CPU Table 2.10 8-Bit Read Operations when Big Endian has been Selected Operation Reading an 8-bit unit Reading an 8-bit unit Reading an 8-bit unit Reading an 8-bit unit Address of src from address 0 from address 1 from address 2 from address 3 Address 0...
Page 71: Data Arrangement
RX24T Group 2. CPU 2.5.4 Data Arrangement 2.5.4.1 Data Arrangement in Registers Figure 2.6 shows the relation between the sizes of registers and bit numbers. Byte (8-bit) data Word (16-bit) data Longword (32-bit) data Figure 2.6 Data Arrangement in Registers 2.5.4.2 Data Arrangement in Memory Data in memory have three sizes: byte (8-bit), word (16-bit), and longword (32-bit).
Page 72: Vector Table
RX24T Group 2. CPU Vector Table There are two types of vector table: exception and interrupt. Each vector in the vector table consists of four bytes and specifies the address where the corresponding exception handling routine starts. 2.6.1 Exception Vector Table In the exception vector table, the individual vectors for the privileged instruction exception, access exception, undefined instruction exception, floating-point exception, non-maskable interrupt, and reset are allocated to the 124-byte area where the value indicated by the exception table register (EXTB) is used as the starting address (ExtBase).
Page 73: Interrupt Vector Table
RX24T Group 2. CPU 2.6.2 Interrupt Vector Table The address where the interrupt vector table is placed can be adjusted. The table is a 1,024-byte region that contains all vectors for unconditional traps and interrupts and starts at the address (IntBase) specified in the interrupt table register (INTB).
Page 74: Operation Of Instructions
RX24T Group 2. CPU Operation of Instructions 2.7.1 Restrictions on RMPA and String-Manipulation Instructions 2.7.1.1 Transfer Size and Data Prefetching The RMPA instruction and the string-manipulation instructions (SCMPU, SMOVB, SMOVF, SMOVU, SSTR, SUNTIL, and SWHILE instructions) transfer data in longword units to speed up the reading of data from and writing of data to the memory.
Page 75: Number Of Cycles
RX24T Group 2. CPU Number of Cycles 2.8.1 Instruction and Number of Cycle Table 2.13 to Table 2.20 show the number of cycles in operation of each instruction. The listed numbers of cycles for access to memory are the numbers of cycles during no-wait access. The operands in the table below indicate the following meanings.
Page 76 RX24T Group 2. CPU Table 2.14 Number of Cycles for Transfer Instructions Mnemonic Instruction (indicates the common operation when the size is omitted) Number of Cycles  MOV “#IMM, Rd”/“Rs, Rd” Transfer instructions  {MOVU, REVL, REVW} “Rs, Rd” (register-register, immediate- ...
Page 77 RX24T Group 2. CPU Table 2.16 Number of Cycles for Branch Instructions Mnemonic Instruction (indicates the common operation when the size is omitted) Number of Cycles  B Cnd “pcdsp” Branch instructions Branch taken: 3  {BRA, BSR} “pcdsp”/“Rs” Branch not taken: 1 ...
Page 78 RX24T Group 2. CPU Table 2.19 Number of Cycles for String Manipulation Instructions Mnemonic Instruction (indicates the common operation when the size is omitted) Number of Cycles  SCMPU String manipulation instructions* 2+4×floor(n/4)+4×(n%4) n: Number of comparison bytes*  SMOVB n>3?6+3×floor(n/4)+3×(n%4):2+3n n: Number of transfer bytes* ...
Page 79: Numbers Of Cycles For Response To Interrupts
RX24T Group 2. CPU 2.8.2 Numbers of Cycles for Response to Interrupts Table 2.21 lists numbers of cycles taken by processing for response to interrupts. Table 2.21 Numbers of Cycles for Response to Interrupts Type of Interrupt Request/Details of Processing Fast Interrupt Other Interrupts 2 cycles...
Page 80: Operating Modes
RX24T Group 3. Operating Modes Operating Modes Operating Mode Types and Selection There are two types of operating-mode selection: one is be selected by the level on pins at the time of release from the reset state, and the other is selected by software after release from the reset state. Table 3.1 shows the relationship between levels on the mode-setting pins (MD) on release from the reset state and the operating mode selected at that time.
Page 81: Register Descriptions
RX24T Group 3. Operating Modes Register Descriptions 3.2.1 Mode Monitor Register (MDMONR) Address(es): 0008 0000h — — — — — — — — — — — — — — — Value after reset: 0/1* Note 1. This affects the level on the MD pin at the time of release from the reset state. Symbol Bit Name Description...
Page 82: System Control Register 1 (Syscr1)
RX24T Group 3. Operating Modes 3.2.2 System Control Register 1 (SYSCR1) Address(es): 0008 0008h — — — — — — — — — — — — — — — RAME Value after reset: Symbol Bit Name Description RAME RAM Enable 0: The RAM is disabled.
Page 83: Details Of Operating Modes
RX24T Group 3. Operating Modes Details of Operating Modes 3.3.1 Single-Chip Mode In this mode, all I/O ports can be used as general input/output ports, peripheral function input/output, or interrupt input pins. The chip starts up in single-chip mode if the high level is on the MD pin on release from the reset state. 3.3.2 Boot Mode In this mode, the on-chip flash memory modifying program (boot program) stored in a dedicated area within the MCU...
Page 84: Transitions Of Operating Modes
RX24T Group 3. Operating Modes Transitions of Operating Modes 3.4.1 Operating Mode Transitions Determined by the Mode-Setting Pins Figure 3.1 shows operating mode transitions determined by the settings of the MD pin. Reset MD = High RES# = High RES# = Low MD = Low RES# = Low RES# = High...
Page 85: Address Space
RX24T Group 4. Address Space Address Space Address Space This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figure 4.1 shows the memory maps in the respective operating modes.
Page 86 RX24T Group 4. Address Space Single-chip mode 0000 0000h 0000 4000h Reserved area 0008 0000h Peripheral I/O registers 0010 0000h On-chip ROM (E2 DataFlash) (read only) 0010 2000h Reserved area 007F C000h Peripheral I/O registers 007F C500h Reserved area 007F FC00h Peripheral I/O registers 0080 0000h Reserved area...
Page 87: I/O Registers
RX24T Group 5. I/O Registers I/O Registers This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as shown below. Notes on writing to registers are also given below. (1) I/O register addresses (address order) ...
Page 88 RX24T Group 5. I/O Registers  Longword-size I/O registers MOV.L #SFR_ADDR, R1 MOV.L #SFR_DATA, [R1] [R1].L, R1 ;; Next process If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary to read or execute operation for all the registers that were written to.
Page 89: I/O Register Addresses (Address Order)
RX24T Group 5. I/O Registers I/O Register Addresses (Address Order) Table 5.1 List of I/O Registers (Address Order) (1 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 0000h SYSTEM...
Page 90 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (2 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 642Ch Region-5 End Page Number Register REPAGE5 1 ICLK section 16.
Page 91 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (3 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 7071h Interrupt Request Register 113 IR113 2 ICLK section 14.
Page 92 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (4 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 70ADh Interrupt Request Register 173 IR173 2 ICLK section 14.
Page 93 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (5 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 7143h DTC Activation Enable Register 067 DTCER067 2 ICLK section 14.
Page 94 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (6 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 71AEh DTC Activation Enable Register 174 DTCER174 2 ICLK section 14.
Page 95 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (7 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 7302h Interrupt Source Priority Register 002 IPR002 2 ICLK section 14.
Page 96 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (8 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 73A8h Interrupt Source Priority Register 168 IPR168 2 ICLK section 14.
Page 97 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (9 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 8038h IWDT IWDT Count Stop Control Register IWDTCSTPR 2 or 3 PCLKB...
Page 98 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (10 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 823Bh TMR7 Timer Counter Control Register TCCR 2 or 3 PCLKB...
Page 99 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (11 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 900Ch S12AD A/D-Converted Value Addition/Average Count Select ADADC 2 or 3 PCLKB...
Page 100 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (12 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 92D6h S12AD1 A/D Channel Select Register C1 ADANSC1 2 or 3 PCLKB...
Page 101 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (13 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 94EBh S12AD2 A/D Sampling State Register 11 ADSSTR11 2 or 3 PCLKB...
Page 102 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (14 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 A0C8h SCI6 Noise Filter Setting Register SNFR 2 or 3 PCLKB...
Page 103 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (15 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 C02Eh PORTE Port Output Data Register PODR 2 or 3 PCLKB...
Page 104 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (16 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 C0C7h PORT7 Pull-Up Control Register 2 or 3 PCLKB section 18.
Page 105 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (17 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 C174h P64 Pin Function Control Register P64PFS 2 or 3 PCLKB section 19.
Page 106 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (18 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 0008 C298h SYSTEM Voltage Detection Level Select Register LVDLVLR 4 or 5 PCLKB...
Page 107 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (19 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 000C 1208h MTU3 Timer Interrupt Enable Register TIER 8, 16...
Page 108 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (20 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 000C 1292h MTU2 Noise Filter Control Register 2 NFCR2 4 or 5 PCLKA...
Page 109 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (21 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 000C 158Ch MTU9 Timer General Register C TGRC 16, 32...
Page 110 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (22 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 000C 1A4Ah MTU7 Timer A/D Converter Start Request Cycle Set Buffer TADCOBRB 4 or 5 PCLKA...
Page 111 RX24T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (23 / 23) Number of Access Cycles Module Register Number of Reference ICLK  PCLK Address Symbol Register Name Symbol Bits Access Size Section 007F C1C0h FLASH Flash Start-Up Setting Monitor Register FSCMR 2 or 3 FCLK...
Page 112: Resets
RX24T Group 6. Resets 6. Resets Overview The following resets are implemented: RES# pin reset, power-on reset, voltage monitoring 0 reset, voltage monitoring 1 reset, voltage monitoring 2 reset, independent watchdog timer reset, and software reset. Table 6.1 lists the reset names and sources. Table 6.1 Reset Names and Sources Reset Name...
Page 113 RX24T Group 6. Resets The internal state and pins are initialized by a reset. Table 6.2 lists the reset targets to be initialized. Table 6.2 Targets Initialized by Each Reset Source Reset Source Voltage Independent Voltage Voltage RES# Pin Power-On Monitoring 0 Watchdog Monitoring 1...
Page 114: Register Descriptions
RX24T Group 6. Resets Register Descriptions 6.2.1 Reset Status Register 0 (RSTSR0) Address(es): 0008 C290h LVD2R LVD1R LVD0R — — — — PORF Value after reset: Note 1. The value after reset depends on the reset source. Symbol Bit Name Description PORF Power-On Reset Detect Flag...
Page 115: Reset Status Register 1 (Rstsr1)
RX24T Group 6. Resets LVD2RF Flag (Voltage Monitoring 2 Reset Detect Flag) The LVD2RF flag indicates that VCC voltage has fallen below Vdet2. [Setting condition]  When Vdet2-level VCC voltage is detected. [Clearing conditions]  When a reset listed in Table 6.2 occurs. ...
Page 116: Reset Status Register 2 (Rstsr2)
RX24T Group 6. Resets 6.2.3 Reset Status Register 2 (RSTSR2) Address(es): 0008 00C0h IWDTR — — — — — SWRF — Value after reset: Note 1. The value after reset depends on the reset source. Symbol Bit Name Description IWDTRF Independent Watchdog Timer Reset Detect 0: Independent watchdog timer reset not detected.
Page 117: Software Reset Register (Swrr)
RX24T Group 6. Resets 6.2.4 Software Reset Register (SWRR) Address(es): 0008 00C2h SWRR[15:0] Value after reset: Symbol Bit Name Description b15 to b0 SWRR[15:0] Software Reset Writing A501h resets the LSI. These bits are read as 0000h. Note: Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register. R01UH0576EJ0100 Rev.1.00 Page 117 of 1230 Nov 30, 2015...
Page 118: Operation
RX24T Group 6. Resets Operation 6.3.1 RES# Pin Reset This is a reset generated by the RES# pin. When the RES# pin is driven low, all the processing in progress is aborted and the LSI enters a reset state. In order to unfailingly reset the LSI, the RES# pin should be held low for the specified power supply stabilization time at a power-on.
Page 119 RX24T Group 6. Resets 4.7 k (reference value) RES# Vdet0 VPOR External voltage RES# pin Voltage monitoring 0 reset state Power-on reset state POR detection signal (Low is valid) LVD0 enable/disable Set by OFS1.LVDAS signal (Low is valid) Voltage detection 0 signal (Low is valid) tPOR tLVD...
Page 120: Voltage Monitoring 1 Reset And Voltage Monitoring 2 Reset
RX24T Group 6. Resets 6.3.3 Voltage Monitoring 1 Reset and Voltage Monitoring 2 Reset The voltage monitoring 1 reset and voltage monitoring 2 reset are internal resets generated by the voltage monitoring circuit. When the voltage monitoring 1 interrupt/reset enable bit (LVD1RIE) is set to 1 (enabling generation of a reset or interrupt by the voltage detection circuit) and the voltage monitoring 1 circuit mode select bit (LVD1RI) is set to 1 (selecting generation of a reset in response to detection of a low voltage) in the voltage monitoring 1 circuit control register 0 (LVD1CR0), the RSTSR0.LVD1RF flag is set to 1 and the voltage-detection circuit generates a voltage...
Page 121: Independent Watchdog Timer Reset
RX24T Group 6. Resets Vdeti* External voltage RES# pin LVDi valid setting LVCMPCR.LVDiE LVDiCR0.LVDiRN = 0 Voltage detection i signal (Low is valid) RES# pin reset RSTSR0.LVDiRF tLVDi* Internal reset signal LVDiCR0.LVDiRN = 1 Voltage detection i signal (Low is valid) RES# pin reset RSTSR0.LVDiRF tLVDi*...
Page 122: Determination Of Cold/Warm Start
RX24T Group 6. Resets 6.3.6 Determination of Cold/Warm Start By reading the CWSF flag in RSTSR1, the type of reset processing caused can be identified; that is, whether a power-on reset has caused the reset processing (cold start) or a reset signal input during operation has caused the reset processing (warm start).
Page 123: Determination Of Reset Generation Source
RX24T Group 6. Resets 6.3.7 Determination of Reset Generation Source Reading RSTSR0 and RSTSR2 determines which reset was used to execute the reset exception handling. Figure 6.4 shows an example of the flow to identify a reset generation source. Reset exception handling RSTSR2.
Page 124: Option-Setting Memory
RX24T Group 7. Option-Setting Memory Option-Setting Memory Overview Option-setting memory refers to a set of registers that are provided for selecting the state of the microcontroller after a reset. The option-setting memory is allocated in the ROM. Figure 7.1 shows the option-setting memory area. Addresses FFFF FF80h to FFFF FF83h Endian select register (MDE)
Page 125: Register Descriptions
RX24T Group 7. Option-Setting Memory Register Descriptions 7.2.1 Option Function Select Register 0 (OFS0) Address(es): FFFF FF8Ch — — — — — — — — — — — — — — — — Value after reset: The value set by the user* IWDTS IWDTR IWDTTOPS[1:0] IWDTS...
Page 126 RX24T Group 7. Option-Setting Memory The setting in the OFS0 register is ignored in boot mode, and this register functions similarly when it is set to FFFF FFFFh. IWDTSTRT Bit (IWDT Start Mode Select) This bit selects the mode in which the IWDT is activated after a reset (stopped state or activated in auto-start mode). When activated in auto-start mode, the OFS0 register setting for the IWDT is effective.
Page 127: Option Function Select Register 1 (Ofs1)
RX24T Group 7. Option-Setting Memory 7.2.2 Option Function Select Register 1 (OFS1) Address(es): FFFF FF88h — — — — — — — — — — — — — — — — Value after reset: The value set by the user* —...
Page 128: Endian Select Register (Mde)
RX24T Group 7. Option-Setting Memory 7.2.3 Endian Select Register (MDE) Address(es): FFFF FF80h — — — — — — — — — — — — — — — — Value after reset: The value set by the user* — — —...
Page 129: Voltage Detection Circuit (Lvdab)
RX24T Group 8. Voltage Detection Circuit (LVDAb) Voltage Detection Circuit (LVDAb) The voltage detection circuit (LVD) monitors the voltage level input to the VCC pin using a program. Overview In voltage detection 0, the detection voltage can be selected from two levels using option function select register 1 (OFS1).
Page 130 RX24T Group 8. Voltage Detection Circuit (LVDAb) Level selection LVDAS circuit (2 levels) Voltage detection 0 reset signal Analog noise filter VDSEL[1:0] Internal reference voltage  Vdet0 (for detecting Vdet0) Level selection LVD1E circuit (9 levels) LVD1CMPE Voltage detection 1 signal Analog noise filter...
Page 131 RX24T Group 8. Voltage Detection Circuit (LVDAb) Voltage monitoring 1 interrupt/reset circuit Voltage detection 1 circuit The setting of the LVD1DET bit will be 0 LVD1SR register LVD1LVL[3:0] if 0 (undetected) is written in the program. LVD1E Level LVD1RIE LVD1CMPE selection LVD1MON bit LVD1RI...
Page 132: Register Descriptions
RX24T Group 8. Voltage Detection Circuit (LVDAb) Register Descriptions 8.2.1 Voltage Monitoring 1 Circuit Control Register 1 (LVD1CR1) Address(es): 0008 00E0h LVD1IR LVD1IDTSEL — — — — — QSEL [1:0] Value after reset: Symbol Bit Name Description b1, b0 LVD1IDTSEL Voltage Monitoring 1 Interrupt b1 b0 0 0: When VCC ≥...
Page 133: Voltage Monitoring 1 Circuit Status Register (Lvd1Sr)
RX24T Group 8. Voltage Detection Circuit (LVDAb) 8.2.2 Voltage Monitoring 1 Circuit Status Register (LVD1SR) Address(es): 0008 00E1h LVD1M LVD1D — — — — — — Value after reset: Symbol Bit Name Description LVD1DET Voltage Monitoring 1 Voltage Change 0: Not detected R/(W) Detection Flag 1: Vdet1 passage detection...
Page 134: Voltage Monitoring 2 Circuit Control Register 1 (Lvd2Cr1)
RX24T Group 8. Voltage Detection Circuit (LVDAb) 8.2.3 Voltage Monitoring 2 Circuit Control Register 1 (LVD2CR1) Address(es): 0008 00E2h LVD2IR LVD2IDTSEL — — — — — QSEL [1:0] Value after reset: Symbol Bit Name Description b1, b0 LVD2IDTSEL Voltage Monitoring 2 Interrupt b1 b0 0 0: When VCC ≥...
Page 135: Voltage Monitoring 2 Circuit Status Register (Lvd2Sr)
RX24T Group 8. Voltage Detection Circuit (LVDAb) 8.2.4 Voltage Monitoring 2 Circuit Status Register (LVD2SR) Address(es): 0008 00E3h LVD2M LVD2D — — — — — — Value after reset: Symbol Bit Name Description LVD2DET Voltage Monitoring 2 Voltage Change 0: Not detected R/(W) Detection Flag 1: Vdet2 passage detection...
Page 136: Voltage Monitoring Circuit Control Register (Lvcmpcr)
RX24T Group 8. Voltage Detection Circuit (LVDAb) 8.2.5 Voltage Monitoring Circuit Control Register (LVCMPCR) Address(es): 0008 C297h — LVD2E LVD1E — — — — — Value after reset: Symbol Bit Name Description b4 to b0 — Reserved These bits are read as 0. The write value should be 0. LVD1E Voltage Detection 1 Enable 0: Voltage detection 1 circuit disabled...
Page 137: Voltage Detection Level Select Register (Lvdlvlr)
RX24T Group 8. Voltage Detection Circuit (LVDAb) 8.2.6 Voltage Detection Level Select Register (LVDLVLR) Address(es): 0008 C298h — — LVD2LVL[1:0] LVD1LVL[3:0] Value after reset: Symbol Bit Name Description b3 to b0 LVD1LVL[3:0] Voltage Detection 1 Level Select 0 0 0 0: 4.29 V (Standard voltage during drop in voltage) 0 0 0 1: 4.14 V 0 0 1 0: 4.02 V...
Page 138: Voltage Monitoring 1 Circuit Control Register 0 (Lvd1Cr0)
RX24T Group 8. Voltage Detection Circuit (LVDAb) 8.2.7 Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0) Address(es): 0008 C29Ah LVD1R LVD1C LVD1RI LVD1RI — — — — Value after reset: x: Undefined Symbol Bit Name Description LVD1RIE Voltage Monitoring 1 Interrupt/Reset 0: Disabled Enable 1: Enabled...
Page 139: Voltage Monitoring 2 Circuit Control Register 0 (Lvd2Cr0)
RX24T Group 8. Voltage Detection Circuit (LVDAb) 8.2.8 Voltage Monitoring 2 Circuit Control Register 0 (LVD2CR0) Address(es): 0008 C29Bh LVD2R LVD2C LVD2RI LVD2RI — — — — Value after reset: x: Undefined Symbol Bit Name Description LVD2RIE Voltage Monitoring 2 Interrupt/Reset 0: Disabled Enable 1: Enabled...
Page 140: Vcc Input Voltage Monitor
RX24T Group 8. Voltage Detection Circuit (LVDAb) VCC Input Voltage Monitor 8.3.1 Monitoring Vdet0 Monitoring Vdet0 is not possible. 8.3.2 Monitoring Vdet1 After making the following settings, the LVD1SR.LVD1MON flag can be used to monitor the results of comparison by voltage monitor 1.
Page 141: Reset From Voltage Monitor 0
RX24T Group 8. Voltage Detection Circuit (LVDAb) Reset from Voltage Monitor 0 When using the reset from voltage monitor 0, clear the voltage detection 0 circuit start bit (OFS1.LVDAS) to 0 (enabling the voltage monitor 0 reset after a reset). Figure 8.4 shows an example of operations for a voltage monitoring 0 reset.
Page 142: Interrupt And Reset From Voltage Monitoring 1
RX24T Group 8. Voltage Detection Circuit (LVDAb) Interrupt and Reset from Voltage Monitoring 1 Table 8.2 shows the procedures for setting bits related to the voltage monitoring 1 interrupt and voltage monitoring 1 reset. Table 8.3 shows the procedures for stopping bits related to the voltage monitoring 1 interrupt and voltage monitoring 1 reset.
Page 143 RX24T Group 8. Voltage Detection Circuit (LVDAb) Vdet1 Lower limit on VCC voltage (VCCmin) Set to 0 by a program LVD1DET bit LVD1IDTSEL[1:0] bits are set to 10b (when drop and rise are detected) Voltage monitoring 1 interrupt request Set to 0 by a program LVD1DET bit LVD1IDTSEL[1:0] bits are set to 00b (when rise is detected).
Page 144: Interrupt And Reset From Voltage Monitoring 2
RX24T Group 8. Voltage Detection Circuit (LVDAb) Interrupt and Reset from Voltage Monitoring 2 Table 8.4 shows the procedures for setting bits related to the voltage monitoring 2 interrupt and voltage monitoring 2 reset. Table 8.5 shows the procedure for stopping bits related to the voltage monitoring 2 interrupt and voltage monitoring 2 reset.
Page 145 RX24T Group 8. Voltage Detection Circuit (LVDAb) Vdet2 Lower limit on VCC voltage (VCCmin) Set to 0 by a program LVD2DET bit LVD2IDTSEL[1:0] bits are set to 10b (when drop and rise are detected) Voltage monitoring 2 interrupt request Set to 0 by a program LVD2DET bit LVD2IDTSEL[1:0] bits are set to 00b (when rise is detected).
Page 146: Clock Generation Circuit
RX24T Group 9. Clock Generation Circuit Clock Generation Circuit Overview This MCU incorporates a clock generation circuit. Table 9.1 lists the specifications of the clock generation circuit. Figure 9.1 shows a block diagram of the clock generation circuit. Table 9.1 Specifications of Clock Generation Circuit Item Specification...
Page 147 RX24T Group 9. Clock Generation Circuit SCKCR FCK[3:0] FlashIF clock (FCLK) To FlashIF SCKCR ICK[3:0] PLIDIV[1:0] STC[5:0] System clock (ICLK) PLLCR PLLCR To CPU, DTC, ROM, and RAM Frequency Frequency divider circuit PCKA[3:0], PCKB[3:0], divider SCKCR CKSEL[2:0] PCKD[3:0] SCKCR3 Peripheral module clock (PCLKA, PCLKB, PCLKD) 1/16 To peripheral module...
Page 148 RX24T Group 9. Clock Generation Circuit Table 9.2 lists the I/O pins of the clock generation circuit. Table 9.2 I/O Pins of Clock Generation Circuit Pin Name Description XTAL Output These pins are used to connect a crystal. The EXTAL pin can also be used to input an external clock.
Page 149: Register Descriptions
RX24T Group 9. Clock Generation Circuit Register Descriptions 9.2.1 System Clock Control Register (SCKCR) Address(es): 0008 0020h FCK[3:0] ICK[3:0] — — — — — — — — Value after reset: PCKA[3:0] PCKB[3:0] — — — — PCKD[3:0] Value after reset: Symbol Bit Name Description...
Page 150 RX24T Group 9. Clock Generation Circuit Symbol Bit Name Description b31 to b28 FCK[3:0]* FlashIF Clock (FCLK) 0 0 0 0: ×1 Select 0 0 0 1: ×1/2 0 0 1 0: ×1/4 0 0 1 1: ×1/8 0 1 0 0: ×1/16 0 1 0 1: ×1/32 0 1 1 0: ×1/64 Settings other than above are prohibited.
Page 151: System Clock Control Register 3 (Sckcr3)
RX24T Group 9. Clock Generation Circuit 9.2.2 System Clock Control Register 3 (SCKCR3) Address(es): 0008 0026h — — — — — CKSEL[2:0] — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 152: Pll Control Register (Pllcr)
RX24T Group 9. Clock Generation Circuit 9.2.3 PLL Control Register (PLLCR) Address(es): 0008 0028h — — STC[5:0] — — — — — — PLIDIV[1:0] Value after reset: Symbol Bit Name Description b1, b0 PLIDIV[1:0] PLL Input Frequency b1 b0 0 0: ×1 Division Ratio Select 0 1: ×1/2 1 0: ×1/4...
Page 153: Pll Control Register 2 (Pllcr2)
RX24T Group 9. Clock Generation Circuit 9.2.4 PLL Control Register 2 (PLLCR2) Address(es): 0008 002Ah — — — — — — — PLLEN Value after reset: Symbol Bit Name Description PLLEN PLL Stop Control 0: PLL is operating. 1: PLL is stopped. b7 to b1 —...
Page 154: Main Clock Oscillator Control Register (Mosccr)
RX24T Group 9. Clock Generation Circuit 9.2.5 Main Clock Oscillator Control Register (MOSCCR) Address(es): 0008 0032h — — — — — — — MOSTP Value after reset: Symbol Bit Name Description MOSTP Main Clock Oscillator Stop 0: Main clock oscillator is operating. 1: Main clock oscillator is stopped.
Page 155: Low-Speed On-Chip Oscillator Control Register (Lococr)
RX24T Group 9. Clock Generation Circuit 9.2.6 Low-Speed On-Chip Oscillator Control Register (LOCOCR) Address(es): 0008 0034h — — — — — — — LCSTP Value after reset: Symbol Bit Name Description LCSTP LOCO Stop 0: LOCO is operating. 1: LOCO is stopped. b7 to b1 —...
Page 156: Iwdt-Dedicated On-Chip Oscillator Control Register (Ilococr)
RX24T Group 9. Clock Generation Circuit 9.2.7 IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR) Address(es): 0008 0035h — — — — — — — ILCSTP Value after reset: Symbol Bit Name Description ILCSTP IWDT-Dedicated On-Chip 0: IWDT-dedicated on-chip oscillator is operating. Oscillator Stop 1: IWDT-dedicated on-chip oscillator is stopped.
Page 157: Oscillation Stabilization Flag Register (Oscovfsr)
RX24T Group 9. Clock Generation Circuit 9.2.8 Oscillation Stabilization Flag Register (OSCOVFSR) Address(es): 0008 003Ch MOOV — — — — — PLOVF — Value after reset: Symbol Bit Name Description MOOVF Main Clock Oscillation 0: Main clock is stopped Stabilization Flag 1: Oscillation is stable and the clock can be used as the system clock* —...
Page 158: Oscillation Stop Detection Control Register (Ostdcr)
RX24T Group 9. Clock Generation Circuit 9.2.9 Oscillation Stop Detection Control Register (OSTDCR) Address(es): 0008 0040h OSTDI OSTDE — — — — — — Value after reset: Symbol Bit Name Description OSTDIE Oscillation Stop Detection 0: The oscillation stop detection interrupt is disabled. Oscillation stop Interrupt Enable detection is not notified to the POE.
Page 159: Oscillation Stop Detection Status Register (Ostdsr)
RX24T Group 9. Clock Generation Circuit 9.2.10 Oscillation Stop Detection Status Register (OSTDSR) Address(es): 0008 0041h — — — — — — — OSTDF Value after reset: Symbol Bit Name Description OSTDF Oscillation Stop Detection Flag 0: The main clock oscillation stop has not been detected. R/(W) 1: The main clock oscillation stop has been detected.
Page 160: Main Clock Oscillator Wait Control Register (Moscwtcr)
RX24T Group 9. Clock Generation Circuit 9.2.11 Main Clock Oscillator Wait Control Register (MOSCWTCR) Address(es): 0008 00A2h — — — MSTS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 MSTS[4:0] Main Clock Oscillator Wait Time 0 0 0 0 0: Wait time = 2 cycles (0.5 μs) 0 0 0 0 1: Wait time = 1024 cycles (256 μs) 0 0 0 1 0: Wait time = 2048 cycles (512 μs) 0 0 0 1 1: Wait time = 4096 cycles (1.024 ms)
Page 161: Main Clock Oscillator Forced Oscillation Control Register (Mofcr)
RX24T Group 9. Clock Generation Circuit 9.2.12 Main Clock Oscillator Forced Oscillation Control Register (MOFCR) Address(es): 0008 C293h MOSEL MODR — — — — — — Value after reset: Symbol Bit Name Description b4 to b0 — Reserved These bits are read as 0. The write value should be 0. MODRV21 Main Clock Oscillator Drive 0: 1 MHz or higher and lower than 10 MHz...
Page 162: Memory Wait Cycle Setting Register (Memwait)
RX24T Group 9. Clock Generation Circuit 9.2.13 Memory Wait Cycle Setting Register (MEMWAIT) Address(es): 0008 0031h — — — — — — MEMWAIT[1:0] Value after reset: Symbol Bit Name Description b1, b0 MEMWAIT[ Memory Wait Cycle Setting* b1 b0 0 0: No wait states 1:0] 0 1: Wait states (ICLK ≤...
Page 163 RX24T Group 9. Clock Generation Circuit Start Change operating power control mode to high-speed mode Change to 64MHz < ICLK? Change within a range of 32MHz < ICLK  64MHz? MEMWAIT.MEMWAIT[1:0] bits = 10b MEMWAIT.MEMWAIT[1:0] bits = 01b MEMWAIT.MEMWAIT[1:0] bits = 01b? MEMWAIT.MEMWAIT[1:0] bits = 10b? Change ICLK frequency to ...
Page 164 RX24T Group 9. Clock Generation Circuit Start Change within a range of 32MHz < ICLK  64MHz? Change ICLK frequency to a range Change ICLK frequency to 32 MHz or  64MHz and > 32MHz lower MEMWAIT.MEMWAIT[1:0] bits = 01b MEMWAIT.MEMWAIT[1:0] bits = 00b MEMWAIT.MEMWAIT[1:0] bits = 01b? MEMWAIT.MEMWAIT[1:0] bits = 00b?
Page 165: Main Clock Oscillator
RX24T Group 9. Clock Generation Circuit Main Clock Oscillator There are two ways of supplying the clock signal from the main clock oscillator: connecting an oscillator or the input of an external clock signal. 9.3.1 Connecting a Crystal Figure 9.4 shows an example of connecting a crystal. A damping resistor (Rd) should be added, if necessary.
Page 166: External Clock Input
RX24T Group 9. Clock Generation Circuit 9.3.2 External Clock Input Figure 9.6 shows connection of an external clock. Set the MOFCR.MOSEL bit to 1 if operation is to be driven by an external clock. In this case, the XTAL pin will be in the Hi-Z state. EXTAL External clock input XTAL...
Page 167: Oscillation Stop Detection Function
RX24T Group 9. Clock Generation Circuit Oscillation Stop Detection Function 9.4.1 Oscillation Stop Detection and Operation after Detection The oscillation stop detection function is used to detect the main clock oscillator stop and to supply LOCO clock pulses from the low-speed on-chip oscillator as the system clock source instead of the main clock. An oscillation stop detection interrupt request can be generated when an oscillation stop is detected.
Page 168: Oscillation Stop Detection Interrupts
RX24T Group 9. Clock Generation Circuit Start Switch to SCKCR3.CKSEL[2:0] = 000b (LOCO) Setting OSTDCR.OSTDIE = 0 Reading OSTDSR.OSTDF = 1 Setting OSTDSR.OSTDF = 0 OSTDSR.OSTDF = 0 Try again? Switch to SCKCR3.CKSEL[2:0] = 010b (main clock oscillator) Note: On return from the oscillation-stopped state, the factor responsible for stopping the main clock oscillation circuit must be removed on the user system to allow the return of oscillation.
Page 169: Pll Circuit
RX24T Group 9. Clock Generation Circuit PLL Circuit The PLL circuit has a function to multiply the frequency from the oscillator. Internal Clock Clock sources of internal clock signals are the main clock, LOCO clock, PLL clock, and dedicated low-speed clock for the IWDT.
Page 170: Usage Notes
RX24T Group 9. Clock Generation Circuit Usage Notes 9.7.1 Notes on Clock Generation Circuit (1) The frequencies of the system clock (ICLK), peripheral module clocks (PCLKA, PCLKB, and PCLKD), and FlashIF clock (FCLK) supplied to each module can be selected by the SCKCR register. Each frequency should meet the following: Select each frequency that is within the operation guaranteed range of clock cycle time (tcyc) specified in AC characteristics of electrical characteristics.
Page 171: Clock Frequency Accuracy Measurement Circuit (Cac)
RX24T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) Clock Frequency Accuracy Measurement Circuit (CAC) 10.1 Overview The clock frequency accuracy measurement circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock to be used as a measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range.
Page 172: Register Descriptions
RX24T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) Table 10.2 shows the pin configuration of the CAC. Table 10.2 Pin Configuration of CAC Pin Name Function CACREF Input Measurement reference clock input pin 10.2 Register Descriptions 10.2.1 CAC Control Register 0 (CACR0) Address(es): 0008 B000h —...
Page 173: Cac Control Register 1 (Cacr1)
RX24T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.2 CAC Control Register 1 (CACR1) Address(es): 0008 B001h CACRE EDGES[1:0] TCSS[1:0] FMCS[2:0] Value after reset: Symbol Bit Name Description CACREFE CACREF Pin Input Enable 0: CACREF pin input is disabled. 1: CACREF pin input is enabled.
Page 174: Cac Control Register 2 (Cacr2)
RX24T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.3 CAC Control Register 2 (CACR2) Address(es): 0008 B002h DFS[1:0] RCDS[1:0] RSCS[2:0] Value after reset: Symbol Bit Name Description Reference Signal Select 0: CACREF pin input 1: Internal clock (internally generated signal) b3 to b1 RSCS[2:0] Measurement Reference Clock...
Page 175: Cac Interrupt Request Enable Register (Caicr)
RX24T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.4 CAC Interrupt Request Enable Register (CAICR) Address(es): 0008 B003h OVFFC MENDF FERRF OVFIE MENDI FERRI — — Value after reset: Symbol Bit Name Description FERRIE Frequency Error Interrupt Request 0: Frequency error interrupt request is disabled. Enable 1: Frequency error interrupt request is enabled.
Page 176: Cac Status Register (Castr)
RX24T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.5 CAC Status Register (CASTR) Address(es): 0008 B004h — — — — — OVFF MENDF FERRF Value after reset: Symbol Bit Name Description FERRF Frequency Error Flag 0: The clock frequency is within the range corresponding to the settings.
Page 177: Cac Upper-Limit Value Setting Register (Caulvr)
RX24T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.6 CAC Upper-Limit Value Setting Register (CAULVR) Address(es): 0008 B006h Value after reset: CAULVR is a 16-bit readable/writable register that specifies the upper-limit value of the counter used for measuring the frequency.
Page 178: Operation
RX24T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.3 Operation 10.3.1 Measuring Clock Frequency The clock frequency accuracy measurement circuit measures the clock frequency using the CACREF pin input or the internal clock as a reference. Figure 10.2 shows an operating example of the clock frequency accuracy measurement circuit.
Page 179: Digital Filtering Of Signals On The Cacref Pin
RX24T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. Also, the MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt is generated. (5) When the next valid edge is input, the counter value is transferred in CACNTBR and compared with the values of CAULVR and CALLVR.
Page 180: Usage Notes
RX24T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.5 Usage Notes 10.5.1 Module Stop Function Setting CAC operation can be disabled or enabled using module stop control register C (MSTPCRC). The initial setting is for the CAC to be halted. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption.
Page 181: Low Power Consumption
RX24T Group 11. Low Power Consumption Low Power Consumption 11.1 Overview This MCU has several functions for reducing power consumption, by setting clock dividers, stopping modules, changing to low power consumption mode in normal operation, and changing to operating power control mode. Table 11.1 lists the specifications of low power consumption functions, and Table 11.2 lists the conditions to change to low power consumption modes, states of the CPU and peripheral modules, and the method for exiting each mode.
Page 182 RX24T Group 11. Low Power Consumption Table 11.2 Operating Conditions of Each Power Consumption Mode Sleep Mode Deep Sleep Mode Software Standby Mode Entry trigger Control register + instruction Control register + instruction Control register + instruction Exit trigger Interrupt Interrupt Interrupt* After exiting from each mode, CPU...
Page 183 RX24T Group 11. Low Power Consumption Reset state Normal operation mode (Program execution state) WAIT instruction* WAIT instruction* WAIT instruction* SSBY = 0 All interrupts Interrupt* All interrupts MSTPCRA.MSTPA28 = 1 SSBY = 1 SSBY = 0 MSTPCRC.DSLPE = 1 Software standby Sleep mode Deep sleep mode...
Page 184 RX24T Group 11. Low Power Consumption Reset state Software Software Deep sleep mode Deep sleep mode standby mode standby mode Exit the reset state High-speed Middle-speed Sleep mode Sleep mode operating mode operating mode Set the OPCCR register : WAIT instruction : Interrupt Figure 11.2 Operating Modes...
Page 185: Register Descriptions
RX24T Group 11. Low Power Consumption 11.2 Register Descriptions 11.2.1 Standby Control Register (SBYCR) Address(es): 0008 000Ch SSBY — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b13 to b0 —...
Page 186: Module Stop Control Register A (Mstpcra)
RX24T Group 11. Low Power Consumption 11.2.2 Module Stop Control Register A (MSTPCRA) Address(es): 0008 0010h MSTPA MSTPA MSTPA MSTPA MSTPA — — — — — — — — — — — Value after reset: MSTPA MSTPA MSTPA MSTPA MSTPA MSTPA MSTPA —...
Page 187 RX24T Group 11. Low Power Consumption Symbol Bit Name Description MSTPA28 Data Transfer Controller Target module: DTC Module Stop 0: This module clock is enabled 1: This module clock is disabled b31 to b29 — Reserved These bits are read as 1. The write value should be 1. Note: Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
Page 188: Module Stop Control Register B (Mstpcrb)
RX24T Group 11. Low Power Consumption 11.2.3 Module Stop Control Register B (MSTPCRB) Address(es): 0008 0014h MSTPB MSTPB MSTPB MSTPB MSTPB MSTPB — — — — — — — — — — Value after reset: MSTPB MSTPB — — — —...
Page 189: Module Stop Control Register C (Mstpcrc)
RX24T Group 11. Low Power Consumption 11.2.4 Module Stop Control Register C (MSTPCRC) Address(es): 0008 0018h MSTPC DSLPE — — — — — — — — — — — — — — Value after reset: MSTPC — — — — —...
Page 190: Operating Power Control Register (Opccr)
RX24T Group 11. Low Power Consumption 11.2.5 Operating Power Control Register (OPCCR) Address(es): 0008 00A0h OPCM — — — — OPCM[2:0] Value after reset: Symbol Bit Name Description b2 to b0 OPCM[2:0] Operating Power Control 0 0 0: High-speed operating mode Mode Select 0 1 0: Middle-speed operating mode Settings other than above are prohibited.
Page 191 RX24T Group 11. Low Power Consumption Table 11.3 Operating Frequency and Voltage Ranges in Operating Power Control Modes Operating Frequency Range Flash Memory Programming/ Flash Memory Read Frequency Erasure Frequency Operating Power OPCM Operating Control Mode [2:0] Bits Voltage Range ICLK FCLK PCLKD...
Page 192 RX24T Group 11. Low Power Consumption  High-Speed Operating Mode The maximum operating frequency during FLASH read is 80 MHz for ICLK and PCLKA; 40 MHz for PCLKB and PCLKD; 32MHz for FCLK. During FLASH programming/erasure, the operating frequency range is 1 to 32 MHz. Note: When using the FCLK at lower than 4 MHz during programming or erasing the flash memory, the frequency can be set to 1, 2, or 3 MHz.
Page 193: Reducing Power Consumption By Switching Clock Signals
RX24T Group 11. Low Power Consumption 11.3 Reducing Power Consumption by Switching Clock Signals The clock frequency can change by setting the SCKCR.FCK[3:0], ICK[3:0], PCKA[3:0], PCKB[3:0], and PCKD[3:0] bits. The CPU, DTC, ROM, and RAM clocks can be set by the ICK[3:0] bits. The peripheral module clocks can be set by the BCK[3:0], PCKA[3:0], PCKB[3:0], and PCKD[3:0] bits.
Page 194 RX24T Group 11. Low Power Consumption Confirm that the OPCCR.OPCMTSF flag is 0 (transition completed) ↓ Set the OPCCR.OPCM[2:0] bit to 0 (high-speed operating mode) ↓ Confirm that the OPCCR.OPCMTSF flag is 0 (transition completed) ↓ Set the frequency of each clock to lower than the maximum operating frequency for high-speed operating mode ↓...
Page 195: Low Power Consumption Modes
RX24T Group 11. Low Power Consumption 11.6 Low Power Consumption Modes 11.6.1 Sleep Mode 11.6.1.1 Entry to Sleep Mode When the WAIT instruction is executed while the SBYCR.SSBY bit is 0, the CPU enters sleep mode. In sleep mode, the CPU stops operating but the contents of its internal registers are retained.
Page 196: Exit From Sleep Mode
RX24T Group 11. Low Power Consumption 11.6.1.2 Exit from Sleep Mode Exit from sleep mode is initiated by any interrupt, a RES# pin reset, a power-on reset, a voltage monitoring reset, or a reset caused by an IWDT underflow.  Initiated by an interrupt An interrupt initiates exit from sleep mode and the interrupt exception handling starts.
Page 197: Deep Sleep Mode
RX24T Group 11. Low Power Consumption 11.6.2 Deep Sleep Mode 11.6.2.1 Entry to Deep Sleep Mode When a WAIT instruction is executed with the MSTPCRC.DSLPE bit set to 1, the MSTPCRA.MSTPA28 bit set to 1, and the SBYCR.SSBY bit cleared to 0, a transition to deep sleep mode is made.* In deep sleep mode, the CPU and the DTC, ROM, and RAM clocks stop.
Page 198: Exit From Deep Sleep Mode
RX24T Group 11. Low Power Consumption 11.6.2.2 Exit from Deep Sleep Mode Exit from deep sleep mode is initiated by any interrupt, a RES# pin reset, a power-on reset, a voltage monitoring reset, or a reset caused by an IWDT underflow. ...
Page 199: Software Standby Mode
RX24T Group 11. Low Power Consumption 11.6.3 Software Standby Mode 11.6.3.1 Entry to Software Standby Mode When a WAIT instruction is executed with the SBYCR.SSBY bit set to 1, a transition to software standby mode is made. In this mode, the CPU, on-chip peripheral functions stop. However, the contents of the CPU internal registers, RAM data, the states of on-chip peripheral functions, the I/O ports are retained.
Page 200: Exit From Software Standby Mode
RX24T Group 11. Low Power Consumption 11.6.3.2 Exit from Software Standby Mode Exit from software standby mode is initiated by an external pin interrupt (the NMI or IRQ0 to IRQ7), peripheral function interrupts (the IWDT, and voltage monitoring), a RES# pin reset, a power-on reset, a voltage monitoring reset, or an independent watchdog timer reset.
Page 201: Example Of Software Standby Mode Application
RX24T Group 11. Low Power Consumption 11.6.3.3 Example of Software Standby Mode Application Figure 11.3 shows an example of entry to software standby mode by the falling edge of the IRQn pin, and exit from software standby mode by the rising edge of the IRQn pin. In this example, an IRQn interrupt is accepted with the IRQCRi.IRQMD[1:0] bits of the ICU set to 01b (falling edge), and then the IRQCRi.IRQMD[1:0] bits are set to 10b (rising edge).
Page 202: Usage Notes
RX24T Group 11. Low Power Consumption 11.7 Usage Notes 11.7.1 I/O Port States I/O port states are retained in software standby mode. Therefore, the supply current is not reduced if output signals are high level. 11.7.2 Module Stop State of DTC Before setting the MSTPCRA.MSTPA28 bit to 1, set the DTCST.DTCST bit of the DTC to 0 to avoid activating the DTC.
Page 203: Register Write Protection Function
RX24T Group 12. Register Write Protection Function Register Write Protection Function The register write protection function protects important registers from being overwritten for in case a program runs out of control. The registers to be protected are set with the protect register (PRCR). Table 12.1 lists the association between the PRCR bits and the registers to be protected.
Page 204: Register Descriptions
RX24T Group 12. Register Write Protection Function 12.1 Register Descriptions 12.1.1 Protect Register (PRCR) Address(es): 0008 03FEh PRKEY[7:0] — — — — PRC3 — PRC1 PRC0 Value after reset: Symbol Bit Name Function PRC0 Protect Bit 0 Enables writing to the registers related to the clock generation circuit. 0: Write disabled 1: Write enabled PRC1...
Page 205: Exception Handling
RX24T Group 13. Exception Handling Exception Handling 13.1 Exception Events During execution of a program by the CPU, the occurrence of a certain event may cause execution of that program to be suspended and execution of another program to be started. Such kinds of events are called exception events. The RXv2 CPU supports eight types of exceptions.
Page 206: Undefined Instruction Exception
RX24T Group 13. Exception Handling 13.1.1 Undefined Instruction Exception An undefined instruction exception occurs when execution of an undefined instruction (an instruction not implemented) is detected. 13.1.2 Privileged Instruction Exception A privileged instruction exception occurs when execution of a privileged instruction is detected in user mode. Privileged instructions can be executed only in supervisor mode.
Page 207: Exception Handling Procedure
RX24T Group 13. Exception Handling 13.2 Exception Handling Procedure In the exception handling, part of the processing is handled automatically by hardware and part of it is handled by a program (exception handling routine) that has been written by the user. Figure 13.2 shows the processing procedure when an exception other than a reset is accepted.
Page 208 RX24T Group 13. Exception Handling When an exception is accepted, hardware processing by the RXv2 CPU is followed by access to the vector to acquire the address of the branch destination. In the vector, a vector address is allocated to each exception, and the branch destination address of the exception handling routine is written to each vector address.
Page 209: Acceptance Of Exception Events
RX24T Group 13. Exception Handling 13.3 Acceptance of Exception Events When an exception occurs, the CPU suspends the execution of the program and processing branches to the exception handling routine. 13.3.1 Acceptance Timing and Saved PC Value Table 13.1 lists the timing of acceptance and the program counter (PC) value to be saved for each exception event. Table 13.1 Acceptance Timing and Saved PC Value Acceptance...
Page 210: Vector And Site For Saving The Values In The Pc And Psw
RX24T Group 13. Exception Handling 13.3.2 Vector and Site for Saving the Values in the PC and PSW The vector for each type of exception and the site for saving the values of the program counter (PC) and processor status word (PSW) are listed in Table 13.2.
Page 211: Hardware Processing For Accepting And Returning From Exceptions
RX24T Group 13. Exception Handling 13.4 Hardware Processing for Accepting and Returning from Exceptions This section describes the hardware processing for accepting and returning from exceptions other than a reset. (1) Hardware Pre-Processing for Accepting an Exception (a) Saving PSW ...
Page 212: Hardware Pre-Processing
RX24T Group 13. Exception Handling 13.5 Hardware Pre-Processing The hardware pre-processing from reception of each exception request to execution of the associated exception handling routine are explained below. 13.5.1 Undefined Instruction Exception 1. The value of the processor status word (PSW) is saved on the stack (ISP). 2.
Page 213: Non-Maskable Interrupt
RX24T Group 13. Exception Handling 13.5.6 Non-Maskable Interrupt 1. The value of the processor status word (PSW) is saved on the stack (ISP). 2. The processor mode select bit (PM), the stack pointer select bit (U), and the interrupt enable bit (I) in PSW are cleared to 0.
Page 214: Return From Exception Handling Routine
RX24T Group 13. Exception Handling 13.6 Return from Exception Handling Routine Executing the instruction listed in Table 13.3 at the end of the corresponding exception handling routine restores the values of the program counter (PC) and processor status word (PSW) that were saved on the stack or in the control registers (BPC and BPSW) immediately before the exception handling sequence.
Page 215: Interrupt Controller (Icub)
RX24T Group 14. Interrupt Controller (ICUb) Interrupt Controller (ICUb) 14.1 Overview The interrupt controller receives interrupt signals from peripheral modules and external pins, sends interrupts to the CPU, and activates the DTC. Table 14.1 lists the specifications of the interrupt controller, and Figure 14.1 shows a block diagram of the interrupt controller.
Page 216 RX24T Group 14. Interrupt Controller (ICUb) Interrupt controller Voltage monitoring 2 interrupt Clock Voltage monitoring 1 interrupt generation Clock restoration request IWDT underflow/refresh error circuit Clock Oscillation stop detection interrupt restoration Digital filter Detection NMI pin judgment Clock restoration enable level Non-maskable interrupt request IFLTE IFLTC...
Page 217: Register Descriptions
RX24T Group 14. Interrupt Controller (ICUb) 14.2 Register Descriptions 14.2.1 Interrupt Request Register n (IRn) (n = interrupt vector number) Address(es): 0008 7010h to 0008 70FFh — — — — — — — Value after reset: Symbol Bit Name Description Interrupt Status Flag 0: No interrupt request is generated R/(W)
Page 218: Interrupt Request Enable Register M (Ierm) (M = 02H To 1Fh)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.2 Interrupt Request Enable Register m (IERm) (m = 02h to 1Fh) Address(es): 0008 7202h to 0008 721Fh IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Value after reset: Symbol Bit Name Description IEN0 Interrupt Request Enable 0 0: Interrupt request is disabled 1: Interrupt request is enabled...
Page 219: Interrupt Source Priority Register N (Iprn) (N = Interrupt Vector Number)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.3 Interrupt Source Priority Register n (IPRn) (n = interrupt vector number) Address(es): 0008 7300h to 0008 73FFh — — — — IPR[3:0] Value after reset: Symbol Bit Name Description b3 to b0 IPR[3:0] Interrupt Priority Level Select 0 0 0 0: Level 0 (interrupt disabled)* 0 0 0 1: Level 1...
Page 220: Fast Interrupt Set Register (Fir)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.4 Fast Interrupt Set Register (FIR) Address(es): 0008 72F0h FIEN — — — — — — — FVCT[7:0] Value after reset: Symbol Bit Name Description b7 to b0 FVCT[7:0] Fast Interrupt Vector Number Specify the vector number of an interrupt source to be a fast interrupt.
Page 221: Software Interrupt Activation Register (Swintr)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.5 Software Interrupt Activation Register (SWINTR) Address(es): 0008 72E0h — — — — — — — SWINT Value after reset: Symbol Bit Name Description SWINT Software Interrupt Activation This bit is read as 0. Writing 1 issues a software interrupt request. R/(W) Writing 0 to this bit has no effect.
Page 222: Dtc Activation Enable Register N (Dtcern) (N = Interrupt Vector Number)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.6 DTC Activation Enable Register n (DTCERn) (n = interrupt vector number) Address(es): 0008 711Bh to 0008 71FFh — — — — — — — DTCE Value after reset: Symbol Bit Name Description DTCE DTC Activation Enable 0: DTC activation is disabled 1: DTC activation is enabled...
Page 223: Irq Control Register I (Irqcri) (I = 0 To 7)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.7 IRQ Control Register i (IRQCRi) (i = 0 to 7) Address(es): 0008 7500h to 0008 7507h — — — — IRQMD[1:0] — — Value after reset: Symbol Bit Name Description b1, b0 — Reserved These bits are read as 0.
Page 224: Irq Pin Digital Filter Enable Register 0 (Irqflte0)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.8 IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) Address(es): 0008 7510h FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN Value after reset: Symbol Bit Name Description FLTEN0 IRQ0 Digital Filter Enable 0: Digital filter is disabled 1: Digital filter is enabled FLTEN1 IRQ1 Digital Filter Enable...
Page 225: Irq Pin Digital Filter Setting Register 0 (Irqfltc0)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.9 IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) Address(es): 0008 7514h FCLKSEL7[1:0] FCLKSEL6[1:0] FCLKSEL5[1:0] FCLKSEL4[1:0] FCLKSEL3[1:0] FCLKSEL2[1:0] FCLKSEL1[1:0] FCLKSEL0[1:0] Value after reset: Symbol Bit Name Description b1, b0 FCLKSEL0[1:0] IRQ0 Digital Filter Sampling Clock 0 0: PCLK 0 1: PCLK/8 b3, b2...
Page 226: Non-Maskable Interrupt Status Register (Nmisr)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.10 Non-Maskable Interrupt Status Register (NMISR) Address(es): 0008 7580h LVD2S LVD1S IWDTS — — — OSTST NMIST Value after reset: Symbol Bit Name Description NMIST NMI Status Flag 0: NMI pin interrupt is not requested 1: NMI pin interrupt is requested OSTST Oscillation Stop Detection...
Page 227 RX24T Group 14. Interrupt Controller (ICUb)  When the IWDT underflow/refresh error interrupt is generated while this interrupt is enabled at its source. [Clearing condition]  When 1 is written to the NMICLR.IWDTCLR bit LVD1ST Flag (Voltage Monitoring 1 Interrupt Status Flag) This flag indicates the request for voltage monitoring 1 interrupt.
Page 228: Non-Maskable Interrupt Enable Register (Nmier)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.11 Non-Maskable Interrupt Enable Register (NMIER) Address(es): 0008 7581h LVD2E LVD1E IWDTE — — — OSTEN NMIEN Value after reset: Symbol Bit Name Description NMIEN NMI Pin Interrupt Enable 0: NMI pin interrupt is disabled R/(W) 1: NMI pin interrupt is enabled OSTEN...
Page 229: Non-Maskable Interrupt Status Clear Register (Nmiclr)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.12 Non-Maskable Interrupt Status Clear Register (NMICLR) Address(es): 0008 7582h LVD2C LVD1C IWDTC OSTCL NMICL — — — Value after reset: Symbol Bit Name Description NMICLR NMI Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.NMIST flag. R/(W) Writing 0 to this bit has no effect.
Page 230: Nmi Pin Interrupt Control Register (Nmicr)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.13 NMI Pin Interrupt Control Register (NMICR) Address(es): 0008 7583h — — — — NMIMD — — — Value after reset: Symbol Bit Name Description b2 to b0 — Reserved These bits are read as 0. The write value should be 0. NMIMD NMI Detection Set 0: Falling edge...
Page 231: Nmi Pin Digital Filter Setting Register (Nmifltc)
RX24T Group 14. Interrupt Controller (ICUb) 14.2.15 NMI Pin Digital Filter Setting Register (NMIFLTC) Address(es): 0008 7594h — — — — — — NFCLKSEL[1:0] Value after reset: Symbol Bit Name Description b1, b0 NFCLKSEL[1:0] NMI Digital Filter Sampling b1 b0 0 0: PCLK Clock 0 1: PCLK/8...
Page 232: Vector Table
RX24T Group 14. Interrupt Controller (ICUb) 14.3 Vector Table There are two types of interrupts detected by the interrupt controller: maskable interrupts and non-maskable interrupts. When the CPU accepts an interrupt or non-maskable interrupt, it acquires a 4-byte vector address from the vector table. 14.3.1 Interrupt Vector Table The interrupt vector table is placed in the 1024-byte range (4 bytes ...
Page 233 RX24T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (1/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — For an unconditional trap 0000h — — — — — For an unconditional trap 0004h —...
Page 234 RX24T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (2/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — Reserved 00CCh — — — — — Reserved 00D0h — — —...
Page 235 RX24T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (3/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER   S12AD S12ADI 0198h Edge IER0C.IEN6 IPR102 DTCER102   GBADI 019Ch Edge IER0C.IEN7...
Page 236 RX24T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (4/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER   MTU7 TGIA7 0254h Edge IER12.IEN5 IPR149 DTCER149   TGIB7 0258h Edge IER12.IEN6...
Page 237 RX24T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (5/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — Reserved 0320h — — — — — Reserved 0324h — — —...
Page 238: Fast Interrupt Vector Table
RX24T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (6/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — Reserved 03ECh — — — — — Reserved 03F0h — — —...
Page 239: Interrupt Operation
RX24T Group 14. Interrupt Controller (ICUb) 14.4 Interrupt Operation The interrupt controller performs the following processing.  Detecting interrupts  Enabling and disabling interrupts  Selecting interrupt request destinations (CPU interrupt or DTC activation)  Determining priority 14.4.1 Detecting Interrupts Interrupt requests are detected in either of two ways: the detection of edges of the interrupt signal or the detection of a level of the interrupt signal.
Page 240 RX24T Group 14. Interrupt Controller (ICUb) Figure 14.3 to Figure 14.5 show the interrupt signals of the interrupt controller. Note that the timings of the interrupts with interrupt vector numbers 64 to 95 are different from those of other interrupts. For the IRQ pin interrupts with interrupt vector numbers 64 to 79, “internal delay + 2 PCLK cycles”...
Page 241: Operation Of Status Flags For Level-Detected Interrupts
RX24T Group 14. Interrupt Controller (ICUb) 14.4.1.2 Operation of Status Flags for Level-Detected Interrupts Figure 14.5 shows the operation of the interrupt status flag (IR flag) in IRn (n = interrupt vector number) in the case of level detection of an interrupt from a peripheral module or an external pin. The IR flag in IRn remains set to 1 as long as the interrupt signal is asserted.
Page 242: Enabling And Disabling Interrupt Sources
RX24T Group 14. Interrupt Controller (ICUb) 14.4.2 Enabling and Disabling Interrupt Sources Enabling requests from a given interrupt source requires the following settings. 1. In the case of interrupt requests from peripheral modules, setting the interrupt enable bit for the peripheral module to permit the output of interrupt requests from the source 2.
Page 243: Determining Priority
RX24T Group 14. Interrupt Controller (ICUb) Table 14.4 Operation at DTC Activation Remaining Interrupt Number of Request DISEL Transfer Operation per Destination Operations Request Interrupt Request Destination after Transfer DTC transfer  ≠ 0 DTC* Cleared on interrupt acceptance by the CPU CPU interrupt DTC transfer ...
Page 244: Fast Interrupt
RX24T Group 14. Interrupt Controller (ICUb) 14.4.6 Fast Interrupt The fast interrupt is an interrupt for executing a faster interrupt response by the CPU, so only one of the interrupt sources can be assigned. The interrupt priority level of the fast interrupt is 15 (highest) regardless of the setting of the IPR[3:0] bits in IPRn (n = interrupt vector number).
Page 245 RX24T Group 14. Interrupt Controller (ICUb) 3. Set the digital filter sampling clock with the IRQFLTC0.FCLKSELi[1:0] bits.* 4. Make or confirm the I/O port settings. 5. Set the method of detection for the interrupt in the IRQCRi.IRQMD[1:0] bits. 6. Clear the corresponding IRn.IR flag (n = interrupt vector number) to 0 (if edge detection is in use). 7.
Page 246: Non-Maskable Interrupt Operation
RX24T Group 14. Interrupt Controller (ICUb) 14.5 Non-maskable Interrupt Operation There are six types of non-maskable interrupt: the NMI pin interrupt, oscillation stop detection interrupt, IWDT underflow/refresh error, voltage monitoring 1 interrupt, and voltage monitoring 2 interrupt. Non-maskable interrupts are only usable as interrupts for the CPU;...
Page 247: Return From Power-Down States
RX24T Group 14. Interrupt Controller (ICUb) 14.6 Return from Power-Down States The interrupt sources that can be used to return operation from sleep mode, deep sleep mode, or software standby mode are listed in Table 14.3, Interrupt Vector Table. For details, refer to section 11, Low Power Consumption. The following describes how to use an interrupt to return operation from each low power consumption mode.
Page 248: Usage Note
RX24T Group 14. Interrupt Controller (ICUb) 14.7 Usage Note 14.7.1 Note on WAIT Instruction Used with Non-Maskable Interrupt Before executing the WAIT instruction, check to see that all the status flags in NMISR are 0. R01UH0576EJ0100 Rev.1.00 Page 248 of 1230 Nov 30, 2015...
Page 249: Buses
RX24T Group 15. Buses Buses 15.1 Overview Table 15.1 lists the bus specifications, Figure 15.1 shows the bus configuration, and Table 15.2 lists the addresses assigned for each bus. Table 15.1 Bus Specifications Bus Type Description  Connected to the CPU (for instructions) CPU bus Instruction bus ...
Page 250 RX24T Group 15. Buses ICLK synchronization Instruction bus Operand bus Memory bus 1 Memory bus 2 Bus error monitoring section DTC (m) Internal main bus 1 Internal main bus 2 Internal peripheral bus 1 Internal peripheral Internal peripheral Internal peripheral buses 2 and 3 bus 4 bus 6...
Page 251: Description Of Buses
RX24T Group 15. Buses 15.2 Description of Buses 15.2.1 CPU Buses The CPU buses consist of the instruction and operand buses, which are connected to internal main bus 1. As the names suggest, the instruction bus is used to fetch instructions for the CPU, while the operand bus is used for operand access. The instruction bus is 64 bits while the operand bus is 32 bits.
Page 252: Internal Peripheral Buses
RX24T Group 15. Buses Table 15.3 Order of Priority for Bus Masters Priority Internal main buses Bus Master High Note: The above applies when the priority order of the buses is fixed. The priority order of internal main bus 1 and another bus (internal main bus 2) can be toggled by the bus priority control register (BUSPRI) (round-robin method).
Page 253: Write Buffer Function (Internal Peripheral Bus)
RX24T Group 15. Buses Priority order fixed: Internal main bus 1 (R11) (R11) (R11) (R13) (R13) Internal main bus 2 Priority order toggled: (R11) (R12) Internal main bus 1 (R22) Internal main bus 2 (1), (2) : The priority order does not change because the priority of the accepted request is low . Request issued;...
Page 254: Parallel Operation
RX24T Group 15. Buses 15.2.6 Parallel Operation Parallel operation is possible when different bus-master modules are requesting access to different slave modules. For example, if the CPU is fetching an instruction from ROM and an operand from RAM, the DTC is able to handle transfer between peripheral buses at the same time.
Page 255: Restrictions
RX24T Group 15. Buses 15.2.7 Restrictions (1) Prohibition of Access that Spans Areas of Address Space Single access that spans two areas of the address space is prohibited, and operation of such an access is not guaranteed. Setting must be made so that two areas are not accessed at the same time by a single word or longword access. (2) Restrictions in Relation to RMPA and String-Manipulation Instructions The allocation of data to be handled by RMPA or string-manipulation instructions to I/O registers is prohibited, and operation is not guaranteed if this restriction is not observed.
Page 256: Register Descriptions
RX24T Group 15. Buses 15.3 Register Descriptions 15.3.1 Bus Error Status Clear Register (BERCLR) Address(es): 0008 1300h STSCL — — — — — — — Value after reset: Symbol Bit Name Description STSCLR Status Clear 0: Invalid (W)* 1: Bus error status register cleared b7 to b1 —...
Page 257: Bus Error Status Register 1 (Bersr1)
RX24T Group 15. Buses 15.3.3 Bus Error Status Register 1 (BERSR1) Address(es): 0008 1308h — MST[2:0] — — Value after reset: Symbol Bit Name Description Illegal Address Access 0: Illegal address access not made 1: Illegal address access made Timeout 0: Timeout not generated 1: Timeout generated b3, b2...
Page 258: Bus Priority Control Register (Buspri)
RX24T Group 15. Buses 15.3.5 Bus Priority Control Register (BUSPRI) Address(es): 0008 1310h — — — — BPFB[1:0] BPHB[1:0] BPGB[1:0] BPIB[1:0] BPRO[1:0] BPRA[1:0] Value after reset: Symbol Bit Name Description b1, b0 BPRA[1:0] Memory Bus 1 (RAM) Priority R(/W) b1 b0 0 0: The order of priority is fixed.
Page 259 RX24T Group 15. Buses BPGB[1:0] Bits (Internal Peripheral Bus 2 and 3 Priority Control) These bits specify the priority order for internal peripheral buses 2 and 3. When the priority order is fixed, internal main bus 2 has priority over internal main bus 1. When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
Page 260: Bus Error Monitoring Section
RX24T Group 15. Buses 15.4 Bus Error Monitoring Section The bus error monitoring section monitors the individual areas for bus errors, and when a bus error occurs, the error is indicated to the bus master. 15.4.1 Types of Bus Error There are two types of bus error: illegal address access and timeout.
Page 261: Operations When A Bus Error Occurs
RX24T Group 15. Buses 15.4.2 Operations When a Bus Error Occurs When a bus error occurs, the error is indicated to the CPU. Operation is not guaranteed when a bus error occurs.  Bus error indication to the CPU An interrupt is generated. The IERn register in the ICU can specify whether to generate an interrupt in the case of a bus error.
Page 262: Interrupt
RX24T Group 15. Buses 15.5 Interrupt 15.5.1 Interrupt Source An illegal address access error or detection of a timeout leads to a bus error signal for the interrupt controller. Table 15.6 Interrupt Source Name Interrupt Source DTC Activation BUSERR Illegal address access error or timeout Not possible R01UH0576EJ0100 Rev.1.00 Page 262 of 1230...
Page 263: Memory-Protection Unit (Mpu)
RX24T Group 16. Memory-Protection Unit (MPU) Memory-Protection Unit (MPU) 16.1 Overview The RXv2 CPU incorporates a memory-protection unit that checks the addresses of CPU access to the overall address space (0000 0000h to FFFF FFFFh). Access-control information can be set for up to eight regions, and permission for access to each region is in accord with this information.
Page 264 RX24T Group 16. Memory-Protection Unit (MPU) A4 A0 CPU instruction address A4 A0 CPU operand access address Processor mode Access control Background access-control register Start page number register End page number register Region 0 Start page number End page number Access control Region 7 Region 0...
Page 265: Types Of Access Control
RX24T Group 16. Memory-Protection Unit (MPU) 16.1.1 Types of Access Control There are three types of access control information: permission for instruction execution, permission to read operands, and permission to write operands. Violations of these types of access control are only detected when programs are running in user mode.
Page 266: Register Descriptions
RX24T Group 16. Memory-Protection Unit (MPU) 16.2 Register Descriptions 16.2.1 Region-n Start Page Number Register (RSPAGEn) (n = 0 to 7) Address(es): RSPAGE0 0008 6400h, RSPAGE1 0008 6408h, RSPAGE2 0008 6410h, RSPAGE3 0008 6418h, RSPAGE4 0008 6420h, RSPAGE5 0008 6428h, RSPAGE6 0008 6430h, RSPAGE7 0008 6438h RSPN[27:0] Value after reset: RSPN[27:0]...
Page 267: Region-N End Page Number Register (Repagen) (N = 0 To 7)
RX24T Group 16. Memory-Protection Unit (MPU) 16.2.2 Region-n End Page Number Register (REPAGEn) (n = 0 to 7) Address(es): REPAGE0 0008 6404h, REPAGE1 0008 640Ch, REPAGE2 0008 6414h, REPAGE3 0008 641Ch, REPAGE4 0008 6424h, REPAGE5 0008 642Ch, REPAGE6 0008 6434h, REPAGE7 0008 643Ch REPN[27:0] Value after reset: REPN[27:0]...
Page 268: Memory-Protection Enable Register (Mpen)
RX24T Group 16. Memory-Protection Unit (MPU) 16.2.3 Memory-Protection Enable Register (MPEN) Address(es): 0008 6500h — — — — — — — — — — — — — — — — Value after reset: — — — — — — — —...
Page 269: Background Access Control Register (Mpbac)
RX24T Group 16. Memory-Protection Unit (MPU) 16.2.4 Background Access Control Register (MPBAC) Address(es): 0008 6504h — — — — — — — — — — — — — — — — Value after reset: — — — — — — —...
Page 270: Memory-Protection Error Status-Clearing Register (Mpeclr)
RX24T Group 16. Memory-Protection Unit (MPU) 16.2.5 Memory-Protection Error Status-Clearing Register (MPECLR) Address(es): 0008 6508h — — — — — — — — — — — — — — — — Value after reset: — — — — — — —...
Page 271: Memory-Protection Error Status Register (Mpests)
RX24T Group 16. Memory-Protection Unit (MPU) 16.2.6 Memory-Protection Error Status Register (MPESTS) Address(es): 0008 650Ch — — — — — — — — — — — — — — — — Value after reset: — — — — — — —...
Page 272: Data Memory-Protection Error Address Register (Mpdea)
RX24T Group 16. Memory-Protection Unit (MPU) 16.2.7 Data Memory-Protection Error Address Register (MPDEA) Address(es): 0008 6514h DEA[31:0] Value after reset: DEA[31:0] Value after reset: x: Undefined Symbol Bit Name Function b31 to b0 DEA[31:0] Data Memory-Protection Error Address Data memory-protection error address DEA[31:0] Bits (Data Memory-Protection Error Address) These bits retain the address for which operand access generated a memory-protection error.
Page 273: Region Search Address Register (Mpsa)
RX24T Group 16. Memory-Protection Unit (MPU) 16.2.8 Region Search Address Register (MPSA) Address(es): 0008 6520h SA[31:0] Value after reset: SA[31:0] Value after reset: x: Undefined Symbol Bit Name Function b31 to b0 SA[31:0] Region Search Address Address for region searching SA[31:0] Bits (Region Search Address) These bits specify the address for use in comparison with region-start addresses in the region-n start page number registers (RSPAGEn) and region-end addresses in the region-n end page number registers (REPAGEn).
Page 274: Region Invalidation Operation Register (Mpopi)
RX24T Group 16. Memory-Protection Unit (MPU) 16.2.10 Region Invalidation Operation Register (MPOPI) Address(es): 0008 6526h — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Function Region Invalidate Start [Reading] 0: Fixed value for reading [Writing]...
Page 275: Instruction-Hit Region Register (Mhiti)
RX24T Group 16. Memory-Protection Unit (MPU) 16.2.11 Instruction-Hit Region Register (MHITI) Address(es): 0008 6528h — — — — — — — — HITI[7:0] Value after reset: — — — — — — — — — — — — UHACI[2:0] — Value after reset: Symbol Bit Name...
Page 276 RX24T Group 16. Memory-Protection Unit (MPU) UHACI[2:0] Bits (Instruction-Hit Region Access Control Bits in User Mode) These bits hold the user-mode access control bits (REPAGEn.UAC[2:0]) for the region where the instruction memory- protection error was generated. If the error was generated in an overlap between regions, the value stored here is the logical OR of the user-mode access control bits for the corresponding regions (including the background region).
Page 277: Data-Hit Region Register (Mhitd)
RX24T Group 16. Memory-Protection Unit (MPU) 16.2.12 Data-Hit Region Register (MHITD) Address(es): 0008 652Ch — — — — — — — — HITD[7:0] Value after reset — — — — — — — — — — — — UHACD[2:0] — Value after reset Symbol Bit Name...
Page 278 RX24T Group 16. Memory-Protection Unit (MPU) HITD[7:0] Bits (Data-Hit Region) These bits indicate the region where a data memory-protection error was generated or the region that produced a hit in a region search. These bits are set to 0000 0000b for a data memory-protection error generated in the background region. Note: When access to a register of memory protection unit in user mode generates a data memory-protection error, the value in this register is cleared to 0000 0000h.
Page 279: Functions
RX24T Group 16. Memory-Protection Unit (MPU) 16.3 Functions 16.3.1 Memory Protection Memory protection means monitoring, in accord with the access-control information that has been set for the individual access-control regions and the background region, whether or not access by programs running in user mode violates the access-control settings.
Page 280: Flow For Determination Of Access By The Memory-Protection Function
RX24T Group 16. Memory-Protection Unit (MPU) 16.3.4 Flow for Determination of Access by the Memory-Protection Function Figure 16.2 shows the flow of determination in the case of data access and Figure 16.3 shows the flow of determination in the case of instruction access. Data access by the CPU Processor mode? Supervisor mode...
Page 281 RX24T Group 16. Memory-Protection Unit (MPU) Instruction access by the CPU Processor mode? Supervisor mode Permit instruction access User mode Is memory protection enabled? Permit instruction access Is access to an access- control region? Determination in accord with Determination in accord with Access prohibited Access prohibited the access-control information...
Page 282: Procedures For Using Memory Protection
RX24T Group 16. Memory-Protection Unit (MPU) 16.4 Procedures for Using Memory Protection 16.4.1 Setting Access-Control Information Access-control information for the various regions is set in supervisor mode. Settings for up to eight access-control regions are made in the region-n start page number registers (RSPAGEn) and region-n end page number registers (REPAGEn), where n = 0 to 7.
Page 283 RX24T Group 16. Memory-Protection Unit (MPU) When a data memory-protection error is generated Access-exception processing by the CPU saves the address of the instruction that led to the memory-protection error on the stack. Furthermore, the address of the operand for which access led to a memory-protection error is stored in the data memory-protection error address register (MPDEA) and the region information for the region where the memory- protection error was generated is stored in the data-hit region register (MHITD).
Page 284: Data Transfer Controller (Dtca)
RX24T Group 17. Data Transfer Controller (DTCa) Data Transfer Controller (DTCa) This MCU incorporates a data transfer controller (DTC). The DTC is activated by an interrupt request to perform data transfers. 17.1 Overview Table 17.1 lists the specifications of the DTC, and Figure 17.1 shows a block diagram of the DTC. Table 17.1 DTC Specifications Item...
Page 285 RX24T Group 17. Data Transfer Controller (DTCa) Register Vector number control Interrupt controller Activation Activation request control DTC response Bus interface DTCCR DTCVBR response DTCADMOD control DTCST DTCSTS Internal peripheral bus 1 Internal main bus 2 Internal main bus 1 Internal Memory bus 1 Memory bus 2...
Page 286: Register Descriptions
RX24T Group 17. Data Transfer Controller (DTCa) 17.2 Register Descriptions Registers MRA, MRB, SAR, DAR, CRA, and CRB are DTC internal registers, which cannot be directly accessed from the CPU. Values to be set in these DTC internal registers are placed in the RAM area as transfer information. When an activation request is generated, the DTC reads the transfer information from the RAM area and set them in the internal registers.
Page 287: Dtc Mode Register B (Mrb)
RX24T Group 17. Data Transfer Controller (DTCa) 17.2.2 DTC Mode Register B (MRB) Address(es): (inaccessible directly from the CPU) CHNE CHNS DISEL DM[1:0] — — Value after reset: x: Undefined Symbol Bit Name Description b1, b0 — Reserved These bits are read as undefined. The write value should be 0. —...
Page 288: Dtc Transfer Source Register (Sar)
RX24T Group 17. Data Transfer Controller (DTCa) 17.2.3 DTC Transfer Source Register (SAR) Address(es): (inaccessible directly from the CPU) Value after reset: Value after reset: x: Undefined SAR register is used to set the transfer source start address. In full-address mode, 32 bits are valid. In short-address mode, lower 24 bits are valid and upper 8 bits (b31 to b24) are ignored.
Page 289: Dtc Transfer Count Register A (Cra)
RX24T Group 17. Data Transfer Controller (DTCa) 17.2.5 DTC Transfer Count Register A (CRA) Address(es): (inaccessible directly from the CPU)  Normal transfer mode Value after reset:  Repeat transfer mode/block transfer mode CRAH CRAL Value after reset: x: Undefined Symbol Register Name Description...
Page 290: Dtc Transfer Count Register B (Crb)
RX24T Group 17. Data Transfer Controller (DTCa) 17.2.6 DTC Transfer Count Register B (CRB) Address(es): (inaccessible directly from the CPU) Value after reset: x: Undefined CRB register is used to set the block transfer count for block transfer mode. The transfer count is 1, 65535, and 65536 when the set value is 0001h, FFFFh, and 0000h, respectively. The CRB value is decremented (–1) when the final data of a single block size is transferred.
Page 291: Dtc Vector Base Register (Dtcvbr)
RX24T Group 17. Data Transfer Controller (DTCa) 17.2.8 DTC Vector Base Register (DTCVBR) Address(es): DTC.DTCVBR 0008 2404h Value after reset: Value after reset: DTCVBR register is used to set the base address for calculating the DTC vector table address. Writing to the upper 4 bits (b31 to b28) is ignored, and the address of this register is extended by the value specified by b27.
Page 292: Dtc Module Start Register (Dtcst)
RX24T Group 17. Data Transfer Controller (DTCa) 17.2.10 DTC Module Start Register (DTCST) Address(es): DTC.DTCST 0008 240Ch — — — — — — — DTCST Value after reset: Symbol Bit Name Description DTCST DTC Module Start 0: DTC module stop 1: DTC module start b7 to b1 —...
Page 293: Dtc Status Register (Dtcsts)
RX24T Group 17. Data Transfer Controller (DTCa) 17.2.11 DTC Status Register (DTCSTS) Address(es): DTC.DTCSTS 0008 240Eh — — — — — — — VECN[7:0] Value after reset: Symbol Bit Name Description b7 to b0 VECN[7:0] DTC-Activating Vector These bits indicate the vector number for the activation source Number Monitoring when DTC transfer is in progress.
Page 294: Activation Sources
RX24T Group 17. Data Transfer Controller (DTCa) 17.3 Activation Sources The DTC is activated by an interrupt request. Setting the ICU.DTCERn.DTCE bit (n = interrupt vector number) to 1 selects the corresponding interrupt as an activation source for the DTC. For the correspondence between the DTC activation sources and the vector addresses, refer to section 14.3.1, Interrupt Vector Table in section 14, Interrupt Controller (ICUb).
Page 295 RX24T Group 17. Data Transfer Controller (DTCa) Upper: DTCVBR DTC vector table Lower: Vector number  4 Transfer information (1) DTC vector address Transfer information (1) start address Transfer information (2) start address Transfer information (2) Transfer information (n) start address 4 bytes Transfer information (n) 4 bytes...
Page 296: Operation
RX24T Group 17. Data Transfer Controller (DTCa) 17.4 Operation The DTC transfers data in accordance with the transfer information. Storage of the transfer information in the RAM area is required before DTC operation. When the DTC is activated, it reads the DTC vector corresponding to the vector number. Next, the DTC reads transfer information from the transfer information store address pointed by the DTC vector, transfers data, and then writes back the transfer information after the data transfer.
Page 297 RX24T Group 17. Data Transfer Controller (DTCa) Start Match and RRS bit = 1 Compare vector numbers. Match? Mismatch or RRS bit = 0 Read DTC vector Next transfer Read information to be transferred Update transfer information start address CHNE bit = 1? CHNS bit = 0 MD[1:0] bits = 01b? (Repeat transfer mode?)
Page 298: Transfer Information Read Skip Function
RX24T Group 17. Data Transfer Controller (DTCa) Table 17.3 Chain Transfer Conditions First Transfer Second Transfer* CHNE CHNS DISEL Transfer CHNE CHNS DISEL Transfer Counter* Counter* DTC Transfer Other than (1 → 0) — — — — — Ends after the first transfer (1 →...
Page 299: Transfer Information Write-Back Skip Function
RX24T Group 17. Data Transfer Controller (DTCa) 17.4.2 Transfer Information Write-Back Skip Function When the MRA.SM[1:0] bits or the MRB.DM[1:0] bits are set to “address fixed”, a part of transfer information is not written back. This function is performed independently of the setting of short-address mode or full-address mode. Table 17.4 lists transfer information write-back skip conditions and applicable registers.
Page 300: Normal Transfer Mode
RX24T Group 17. Data Transfer Controller (DTCa) 17.4.3 Normal Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single activation source. The transfer count can be set to 1 to 65536. Transfer source addresses and transfer destination addresses can be set to increment, decrement, or fixed independently. This mode enables an interrupt request to the CPU to be generated at the end of specified-count transfer.
Page 301: Repeat Transfer Mode
RX24T Group 17. Data Transfer Controller (DTCa) 17.4.4 Repeat Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single activation source. Specify either transfer source or transfer destination for the repeat area by the MRB.DTS bit. The transfer count can be set to 1 to 256.
Page 302: Block Transfer Mode
RX24T Group 17. Data Transfer Controller (DTCa) 17.4.5 Block Transfer Mode This mode allows single-block data transfer on a single activation source. Specify either transfer source or transfer destination for the block area by the MRB.DTS bit. The block size can be set to 1 to 256 bytes, 1 to 256 words, or 1 to 256 longwords.
Page 303: Chain Transfer
RX24T Group 17. Data Transfer Controller (DTCa) 17.4.6 Chain Transfer Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single activation source. If the MRB.CHNE and CHNS bits are set to 1 and 0, respectively, an interrupt request to the CPU is not generated by completion of specified number of rounds of transfer or by setting the MRB.DISEL bit to 1 (an interrupt request to the CPU is generated each time DTC data transfer is performed), and data transfer has no effect on the interrupt status flag of the activation source.
Page 304: Operation Timing
RX24T Group 17. Data Transfer Controller (DTCa) 17.4.7 Operation Timing Figure 17.9 to Figure 17.13 show examples of DTC operation timing. System clock ICU.IRn DTC activation request DTC access Transfer Data Vector read Transfer information read transfer information write n = Vector number Figure 17.9 Example (1) of DTC Operation Timing (Short-Address Mode, Normal Transfer Mode, Repeat Transfer Mode)
Page 305 RX24T Group 17. Data Transfer Controller (DTCa) System clock ICU.IRn DTC activation request DTC access Data Data Vector read Transfer Transfer Transfer Transfer transfer transfer information read information information information write read write n = Vector number Figure 17.11 Example (3) of DTC Operation Timing (Short-Address Mode, Chain Transfer) System clock ICU.IRn DTC activation request...
Page 306 RX24T Group 17. Data Transfer Controller (DTCa) System clock ICU.IRn DTC activation request Read skip enable DTC access Data Transfer Vector read Transfer Data Transfer transfer information write information read information write transfer n = Vector number Note: When activation sources (vector numbers) of (1) and (2) are the same and the RRS bit = 1, the transfer information read for request (2) is skipped.
Page 307: Execution Cycles Of The Dtc
RX24T Group 17. Data Transfer Controller (DTCa) 17.4.8 Execution Cycles of the DTC Table 17.8 lists the execution cycles of single data transfer of the DTC. For the order of the execution states, refer to section 17.4.7, Operation Timing. Table 17.8 Execution Cycles of the DTC Data Transfer Transfer...
Page 308: Dtc Setting Procedure
RX24T Group 17. Data Transfer Controller (DTCa) 17.5 DTC Setting Procedure Before using the DTC, set the DTC vector base register (DTCVBR). Figure 17.14 shows the procedure to set the DTC. Set the ICU.IERm.IENj bit corresponding to the activation Start source interrupt to 0 and provide the following settings.
Page 309: Examples Of Dtc Usage
RX24T Group 17. Data Transfer Controller (DTCa) 17.6 Examples of DTC Usage 17.6.1 Normal Transfer As an example of DTC usage, its employment in the reception of 128 bytes of data by an SCI is described below. (1) Transfer Information Setting In the MRA register, select a fixed source address (MRA.SM[1:0] bits = 00b), normal transfer mode (MRA.MD[1:0] bits = 00b), and byte-sized transfer (MRA.SZ[1:0] bits = 00b).
Page 310: Chain Transfer When The Counter = 0
RX24T Group 17. Data Transfer Controller (DTCa) 17.6.2 Chain Transfer When the Counter = 0 The second data transfer is performed only when the transfer counter is set to 0 in the first data transfer, and the first data transfer information is repeatedly changed in the second transfer. Repeating this chain transfer enables transfers to be repeated 256 times or more.
Page 311: Interrupt Source
RX24T Group 17. Data Transfer Controller (DTCa) Input circuit Transfer information allocated in the on-chip memory space Input buffer First data transfer Transfer information Chain transfer (counter = 0) Second data transfer Transfer information Upper 8 bits of DAR Figure 17.15 Chain Transfer When the Counter = 0 17.7 Interrupt Source...
Page 312: Low Power Consumption Function
RX24T Group 17. Data Transfer Controller (DTCa) 17.8 Low Power Consumption Function Before making a transition to the module stop state, deep sleep mode, or software standby mode, set the DTCST.DTCST bit to 0 (DTC module stop), and then perform the following. (1) Module Stop Function Writing 1 (transition to the module-stop state is made) to the MSTPCRA.MSTPA28 bit enables the module stop function of the DTC.
Page 313: Usage Notes
RX24T Group 17. Data Transfer Controller (DTCa) 17.9 Usage Notes 17.9.1 Transfer Information Start Address Be sure to set multiples of 4 for the transfer information start addresses in the vector table. Otherwise, such addresses are accessed with their lowest 2 bits regarded as 00b. 17.9.2 Allocating Transfer Information Allocate transfer data in the memory area according to the endian of the area as shown in Figure 17.16.
Page 314: I/O Ports
RX24T Group 18. I/O Ports I/O Ports 18.1 Overview The I/O ports function as a general I/O port, an I/O pin of a peripheral module, or an input pin for an interrupt. Some of the pins are also configurable as an I/O pin of a peripheral module or an input pin for an interrupt. All pins function as input pins immediately after a reset, and pin functions are switched by register settings.
Page 315 RX24T Group 18. I/O Ports Table 18.1 Specifications of I/O Ports Package Package Port Number Number 100 Pins 80 Pins of Pin of Pin PORT0 P00 to P02 P00 to P02 PORT1 P10, P11 P10, P11 PORT2 P20 to P24 P20 to P24 PORT3 P30 to P33...
Page 316 RX24T Group 18. I/O Ports Drive Capacity Port Input Pull-up Open Drain Output High Current Pin 5-V Tolerant Switching ○ ○ ○ ― ― PORTD PD0, PD2 ○ ○ ○ ― Fixed to high drive output ○ ○ ○ ― ―...
Page 317: I/O Port Configuration
RX24T Group 18. I/O Ports 18.2 I/O Port Configuration Port 0: P00 to P02 Port 1: P10, P11 Port 2: P22 to P24 Port 3: P30, P31, P32 , P33 Port 4: P40 to P47 Port 5: P50 to P55 Port 6: P60 , P61 , P62, P63 to P65...
Page 318 RX24T Group 18. I/O Ports Port E: PE2 NMI input signal Reading the port Peripheral modules Figure 18.2 I/O Port Configuration (2) R01UH0576EJ0100 Rev.1.00 Page 318 of 1230 Nov 30, 2015...
Page 319: Register Descriptions
RX24T Group 18. I/O Ports 18.3 Register Descriptions 18.3.1 Port Direction Register (PDR) Address(es): PORT0.PDR 0008 C000h, PORT1.PDR 0008 C001h, PORT2.PDR 0008 C002h, PORT3.PDR 0008 C003h, PORT4.PDR 0008 C004h, PORT5.PDR 0008 C005h, PORT6.PDR 0008 C006h, PORT7.PDR 0008 C007h, PORT8.PDR 0008 C008h, PORT9.PDR 0008 C009h, PORTA.PDR 0008 C00Ah, PORTB.PDR 0008 C00Bh, PORTD.PDR 0008 C00Dh, PORTE.PDR 0008 C00Eh Value after reset: Symbol...
Page 320: Port Output Data Register (Podr)
RX24T Group 18. I/O Ports 18.3.2 Port Output Data Register (PODR) Address(es): PORT0.PODR 0008 C020h, PORT1.PODR 0008 C021h, PORT2.PODR 0008 C022h, PORT3.PODR 0008 C023h, PORT4.PODR 0008 C024h, PORT5.PODR 0008 C025h, PORT6.PODR 0008 C026h, PORT7.PODR 0008 C027h, PORT8.PODR 0008 C028h, PORT9.PODR 0008 C029h, PORTA.PODR 0008 C02Ah, PORTB.PODR 0008 C02Bh, PORTD.PODR 0008 C02Dh, PORTE.PODR 0008 C02Eh Value after reset: Symbol...
Page 321: Port Input Data Register (Pidr)
RX24T Group 18. I/O Ports 18.3.3 Port Input Data Register (PIDR) Address(es): PORT0.PIDR 0008 C040h, PORT1.PIDR 0008 C041h, PORT2.PIDR 0008 C042h, PORT3.PIDR 0008 C043h, PORT4.PIDR 0008 C044h, PORT5.PIDR 0008 C045h, PORT6.PIDR 0008 C046h, PORT7.PIDR 0008 C047h, PORT8.PIDR 0008 C048h, PORT9.PIDR 0008 C049h, PORTA.PIDR 0008 C04Ah, PORTB.PIDR 0008 C04Bh, PORTD.PIDR 0008 C04Dh, PORTE.PIDR 0008 C04Eh Value after reset: x: Undefined...
Page 322: Port Mode Register (Pmr)
RX24T Group 18. I/O Ports 18.3.4 Port Mode Register (PMR) Address(es): PORT0.PMR 0008 C060h, PORT1.PMR 0008 C061h, PORT2.PMR 0008 C062h, PORT3.PMR 0008 C063h, PORT7.PMR 0008 C067h, PORT8.PMR 0008 C068h, PORT9.PMR 0008 C069h, PORTA.PMR 0008 C06Ah, PORTB.PMR 0008 C06Bh, PORTD.PMR 0008 C06Dh, PORTE.PMR 0008 C06Eh Value after reset: Symbol Bit Name...
Page 323: Open Drain Control Register 0 (Odr0)
RX24T Group 18. I/O Ports 18.3.5 Open Drain Control Register 0 (ODR0) Address(es): PORT0.ODR0 0008 C080h, PORT1.ODR0 0008 C082h, PORT2.ODR0 0008 C084h, PORT3.ODR0 0008 C086h, PORT7.ODR0 0008 C08Eh, PORT8.ODR0 0008 C090h, PORT9.ODR0 0008 C092h, PORTA.ODR0 0008 C094h, PORTB.ODR0 0008 C096h, PORTD.ODR0 0008 C09Ah, PORTE.ODR0 0008 C09Ch Value after reset: Symbol Bit Name...
Page 324: Open Drain Control Register 1 (Odr1)
RX24T Group 18. I/O Ports 18.3.6 Open Drain Control Register 1 (ODR1) Address(es): PORT2.ODR1 0008 C085h, PORT7.ODR1 0008 C08Fh, PORT9.ODR1 0008 C093h, PORTA.ODR1 0008 C095h, PORTB.ODR1 0008 C097h, PORTD.ODR1 0008 C09Bh, PORTE.ODR1 0008 C09Dh Value after reset: Symbol Bit Name Description Pm4 Output Type Select 0: CMOS output...
Page 325: Pull-Up Control Register (Pcr)
RX24T Group 18. I/O Ports 18.3.7 Pull-Up Control Register (PCR) Address(es): PORT0.PCR 0008 C0C0h, PORT1.PCR 0008 C0C1h, PORT2.PCR 0008 C0C2h, PORT3.PCR 0008 C0C3h, PORT4.PCR 0008 C0C4h, PORT5.PCR 0008 C0C5h, PORT6.PCR 0008 C0C6h, PORT7.PCR 0008 C0C7h, PORT8.PCR 0008 C0C8h, PORT9.PCR 0008 C0C9h, PORTA.PCR 0008 C0CAh, PORTB.PCR 0008 C0CBh, PORTD.PCR 0008 C0CDh, PORTE.PCR 0008 C0CEh, , Value after reset: Symbol...
Page 326: Drive Capacity Control Register (Dscr)
RX24T Group 18. I/O Ports 18.3.8 Drive Capacity Control Register (DSCR) Address(es): PORT0.DSCR 0008 C0E0h, PORT1.DSCR 0008 C0E1h, PORT2.DSCR 0008 C0E2h, PORT3.DSCR 0008 C0E3h, PORT7.DSCR 0008 C0E7h, PORT8.DSCR 0008 C0E8h, PORT9.DSCR 0008 C0E9h, PORTA.DSCR 0008 C0EAh, PORTB.DSCR 0008 C0EBh, PORTD.DSCR 0008 C0EDh, PORTE.DSCR 0008 C0EEh Value after reset: Symbol Bit Name...
Page 327: Initialization Of The Port Direction Register (Pdr)
RX24T Group 18. I/O Ports 18.4 Initialization of the Port Direction Register (PDR) Initialize reserved bits in the PDR register according to Table 18.3 and Table 18.4.  The blank columns in Table 18.3 and Table 18.4 indicate the bits corresponding to the pins listed in Table 18.1, Specifications of I/O Ports.
Page 328: Handling Of Unused Pins
RX24T Group 18. I/O Ports 18.5 Handling of Unused Pins The configuration of unused pins is listed in Table 18.5. Table 18.5 Unused Pin Configuration Pin Name Description (Always used as mode pins) RES# Connect this pin to VCC via a pull-up resistor. PE2/NMI Connect this pin to VCC via a pull-up resistor.
Page 329: Multi-Function Pin Controller (Mpc)
RX24T Group 19. Multi-Function Pin Controller (MPC) Multi-Function Pin Controller (MPC) 19.1 Overview The multi-function pin controller (MPC) is used to allocate input and output signals for peripheral modules and input interrupt signals to pins from among multiple ports. Table 19.1 shows the allocation of pin functions to multiple pins. The symbols ○ and × in the table indicate whether the pins are or are not present on the given package.
Page 330 RX24T Group 19. Multi-Function Pin Controller (MPC) Table 19.1 Allocation of Pin Functions to Multiple Pins (2 / 6) Package Allocation Module/Function Channel Pin Functions Port 100-pin 80-pin ○ ○ Multi-function timer unit 3 MTU1 MTIOC1A (input/output) ○ MTIOC1B (input/output) ×...
Page 331 RX24T Group 19. Multi-Function Pin Controller (MPC) Table 19.1 Allocation of Pin Functions to Multiple Pins (3 / 6) Package Allocation Module/Function Channel Pin Functions Port 100-pin 80-pin ○ ○ Multi-function timer unit 3 MTCLKA (input) ○ × ○ ○ MTCLKB (input) ○...
Page 332 RX24T Group 19. Multi-Function Pin Controller (MPC) Table 19.1 Allocation of Pin Functions to Multiple Pins (4 / 6) Package Allocation Module/Function Channel Pin Functions Port 100-pin 80-pin ○ ○ 8-bit timer TMR6 TMO6 (output) ○ × ○ × ○ ○...
Page 333 RX24T Group 19. Multi-Function Pin Controller (MPC) Table 19.1 Allocation of Pin Functions to Multiple Pins (5 / 6) Package Allocation Module/Function Channel Pin Functions Port 100-pin 80-pin ○ ○ Serial peripheral interface RSPCKA (input/output) ○ × ○ ○ ○ ×...
Page 334 RX24T Group 19. Multi-Function Pin Controller (MPC) Table 19.1 Allocation of Pin Functions to Multiple Pins (6 / 6) Package Allocation Module/Function Channel Pin Functions Port 100-pin 80-pin ○ 12-bit A/D converter ADTRG0# (input) × ○ ○ ○ × ○ ○...
Page 335: Register Descriptions
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2 Register Descriptions Registers and bits for pins that are not present due to differences according to the package are reserved. Write the value after a reset when writing to such bits. 19.2.1 Write-Protect Register (PWPR) Address(es): 0008 C11Fh B0WI PFSWE...
Page 336: P0N Pin Function Control Register (P0Npfs) (N = 0 To 2)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.2 P0n Pin Function Control Register (P0nPFS) (n = 0 to 2) Address(es): P00PFS 0008 C140h, P01PFS 0008 C141h, P02PFS 0008 C142h — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select...
Page 337: P1N Pin Function Select Register (P1Npfs) (N = 0, 1)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.3 P1n Pin Function Select Register (P1nPFS) (n = 0, 1) Address(es): P10PFS 0008 C148h, P11PFS 0008 C149h — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function.
Page 338: P2N Pin Function Select Register (P2Npfs) (N = 0 To 4)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.4 P2n Pin Function Select Register (P2nPFS) (n = 0 to 4) Address(es): P20PFS 0008 C150h, P21PFS 0008 C151h, P22PFS 0008 C152h, P23PFS 0008 C153h, P24PFS 0008 C154h ASEL ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description...
Page 339: P3N Pin Function Select Register (P3Npfs) (N = 0 To 3)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.5 P3n Pin Function Select Register (P3nPFS) (n = 0 to 3) Address(es): P30PFS 0008 C158h, P31PFS 0008 C159h, P32PFS 0008 C15Ah, P33PFS 0008 C15Bh — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0...
Page 340: P4N Pin Function Select Register (P4Npfs) (N = 0 To 7)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.6 P4n Pin Function Select Register (P4nPFS) (n = 0 to 7) Address(es): P40PFS 0008 C160h, P41PFS 0008 C161h, P42PFS 0008 C162h, P43PFS 0008 C163h, P44PFS 0008 C164h, P45PFS 0008 C165h, P46PFS 0008 C166h, P47PFS 0008 C167h ASEL —...
Page 341: P6N Pin Function Select Register (P6Npfs) (N = 0 To 5)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.8 P6n Pin Function Select Register (P6nPFS) (n = 0 to 5) Address(es): P60PFS 0008 C170h, P61PFS 0008 C171h, P62PFS 0008 C172h, P63PFS 0008 C173h, P64PFS 0008 C174h, P65PFS 0008 C175h ASEL ISEL —...
Page 342: P7N Pin Function Select Register (P7Npfs) (N = 0 To 6)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.9 P7n Pin Function Select Register (P7nPFS) (n = 0 to 6) Address(es): P70PFS 0008 C178h, P71PFS 0008 C179h, P72PFS 0008 C17Ah, P73PFS 0008 C17Bh, P74PFS 0008 C17Ch, P75PFS 0008 C17Dh, P76PFS 0008 C17Eh —...
Page 343: P8N Pin Function Select Register (P8Npfs) (N = 0 To 2)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.10 P8n Pin Function Select Register (P8nPFS) (n = 0 to 2) Address(es): P80PFS 0008 C180h, P81PFS 0008 C181h, P82PFS 0008 C182h — — — — PSEL[4:0] Value after reset: The ASEL bit is set when a pin is used as an analog pin. The pin state cannot be read at this point. Symbol Bit Name Description...
Page 344: P9N Pin Function Select Register (P9Npfs) (N = 0 To 6)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.11 P9n Pin Function Select Register (P9nPFS) (n = 0 to 6) Address(es): P90PFS 0008 C188h, P91PFS 0008 C189h, P92PFS 0008 C18Ah, P93PFS 0008 C18Bh, P94PFS 0008 C18Ch, P95PFS 0008 C18Dh, P96PFS 0008 C18Eh —...
Page 345: Pan Pin Function Select Register (Panpfs) (N = 0 To 5)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.12 PAn Pin Function Select Register (PAnPFS) (n = 0 to 5) Address(es): PA0PFS 0008 C190h, PA1PFS 0008 C191h, PA2PFS 0008 C192h, PA3PFS 0008 C193h, PA4PFS 0008 C194h, PA5PFS 0008 C195h — ISEL —...
Page 346: Pbn Pin Function Select Register (Pbnpfs) (N = 0 To 7)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.13 PBn Pin Function Select Register (PBnPFS) (n = 0 to 7) Address(es): PB0PFS 0008 C198h, PB1PFS 0008 C199h, PB2PFS 0008 C19Ah, PB3PFS 0008 C19Bh, PB4PFS 0008 C19Ch, PB5PFS 0008 C19Dh, PB6PFS 0008 C19Eh, PB7PFS 0008 C19Fh —...
Page 347: Pdn Pin Function Select Register (Pdnpfs) (N = 0 To 7)
RX24T Group 19. Multi-Function Pin Controller (MPC) Table 19.13 Register Settings for Input/Output Pin Function in 80-pin Register/Pin PSEL[4:0] Settings 00000b (Initial value) Hi-Z 00001b MTIOC0D MTIOC0C MTIOC0B MTIOC0A — — — 00101b TMO0 TMCI0 TMRI0 — — — — 00111b —...
Page 348 RX24T Group 19. Multi-Function Pin Controller (MPC) Table 19.14 Register Settings for Input/Output Pin Function in 100-pin Register/Pin PSEL[4:0] Settings 00000b (Initial value) Hi-Z 000001b — — — — — — MTIOC9C MTIOC9A 00101b TMO6 TMO2 TMCI1 TMO0 TMCI0 TMRI0 TMO1 TMRI1 00110b...
Page 349: Pen Pin Function Select Register (Penpfs) (N = 0 To 5)
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.2.15 PEn Pin Function Select Register (PEnPFS) (n = 0 to 5) Address(es): PE0PFS 0008 C1B0h, PE1PFS 0008 C1B1h, PE2PFS 0008 C1B2h, PE3PFS 0008 C1B3h, PE4PFS 0008 C1B4h, PE5PFS 0008 C1B5h — ISEL —...
Page 350 RX24T Group 19. Multi-Function Pin Controller (MPC) Table 19.17 Register Settings for Input/Output Pin Function in 80-pin Register/Pin PSEL[4:0] Settings 00000b (Initial value) Hi-Z 00001b — — — 00010b — MTCLKD MTCLKC 00101b — — — 00110b — — — 00111b POE10# POE11#...
Page 351: Usage Notes
RX24T Group 19. Multi-Function Pin Controller (MPC) 19.3 Usage Notes 19.3.1 Procedure for Specifying Input/Output Pin Function Use the following procedure to specify the input/output pin functions. (1) Clear the port mode register (PMR) to 0 to select the general I/O port function. (2) Specify the assignments of input/output signals for peripheral functions to the desired pins.
Page 352: Note On Using Analog Functions
RX24T Group 19. Multi-Function Pin Controller (MPC) Table 19.18 Register Settings PmnPFS Item PMR.Bn PDR.Bn ASEL ISEL PSEL[4:0] Point to Note After a reset 00000b Pins function as general input port pins after release from the reset state. General input Set the ISEL bit to 1 if these are multiplexed with interrupt inputs.
Page 353: Multi-Function Timer Pulse Unit (Mtu3D)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Multi-Function Timer Pulse Unit (MTU3d) 20.1 Overview This MCU has an on-chip multi-function timer pulse unit (MTU3d), consisting of nine 16-bit timer channels. Table 20.1 shows the specifications of the MTU and Table 20.2 lists the functions of the MTU. Figure 20.1 and Figure 20.2 show block diagrams of the MTU.
Page 354 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.2 MTU Functions (1/2) MTU1 & MTU2 Item MTU0 MTU1 MTU2 (LWA = 1) MTU3 MTU4 MTU5 MTU6 MTU7 MTU9 Count clock PCLKA/1 PCLKA/1 PCLKA/1 MTCLKA PCLKA/1 PCLKA/1 PCLKA/1 PCLKA/1 PCLKA/1 PCLKA/1 PCLKA/2 PCLKA/2...
Page 355 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.2 MTU Functions (2/2) MTU1 & MTU2 Item MTU0 MTU1 MTU2 (LWA = 1) MTU3 MTU4 MTU5 MTU6 MTU7 MTU9 Interrupt sources Seven Four sources Four sources Four sources Five sources Five sources Three Five sources...
Page 356 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Interrupt request signals MTU3: TGIA3 TGIB3 TGIC3 I/O pins TGID3 MTU3: MTIOC3A TCIV3 MTIOC3B MTU4: TGIA4 MTIOC3C TGIB4 MTIOC3D TGIC4 MTU4: MTIOC4A TGID4 MTIOC4B TCIV4 MTIOC4C MTIOC4D Clock input Internal clock: PCLKA PCLKA/2 PCLKA/4 Internal peripheral bus...
Page 357 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Interrupt request signals MTU6: TGIA6 TGIB6 TGIC6 I/O pins TGID6 MTU6 : MTIOC6A TCIV6 MTIOC6B MTIOC6C MTU7: TGIA7 MTIOC6D TGIB7 TGIC7 MTU7 : MTIOC7A TGID7 MTIOC7B TCIV7 MTIOC7C MTIOC7D Interrupt request signals Input pins MTU5: TGIU5...
Page 358 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.3 shows the configuration of pins for the MTU. Table 20.3 Pin Configuration of the MTU Channel Pin Name Function MTCLKA Input External clock A input pin (MTU1 phase counting mode A phase input) MTCLKB Input External clock B input pin (MTU1 phase counting mode B phase input)
Page 359: Register Descriptions
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2 Register Descriptions 20.2.1 Timer Control Register (TCR)  MTU0.TCR, MTU1.TCR, MTU2.TCR, MTU3.TCR, MTU4.TCR, MTU6.TCR, MTU7.TCR, MTU9.TCR Address(es): MTU0.TCR 000C 1300h, MTU1.TCR 000C 1380h, MTU2.TCR 000C 1400h, MTU3.TCR 000C 1200h, MTU4.TCR 000C 1201h, MTU6.TCR 000C 1A00h, MTU7.TCR 000C 1A01h, MTU9.TCR 000C 1580h CCLR[2:0] CKEG[1:0] TPSC[2:0]...
Page 360 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.4 CCLR[2:0] (MTU0, MTU3, MTU4, MTU6, MTU7, MTU9) Bit 7 Bit 6 Bit 5 Channel CCLR[2] CCLR[1] CCLR[0] Description MTU0 TCNT clearing disabled MTU3 TCNT cleared by TGRA compare match/input capture MTU4 TCNT cleared by TGRB compare match/input capture MTU6...
Page 361: Timer Control Register 2 (Tcr2)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.2 Timer Control Register 2 (TCR2)  MTU0.TCR2, MTU3.TCR2, MTU4.TCR2, MTU6.TCR2, MTU7.TCR2, MTU9.TCR2 Address(es): MTU0.TCR2 000C 1328h, MTU3.TCR2 000C 124Ch, MTU4.TCR2 000C 124Dh, MTU6.TCR2 000C 1A4Ch, MTU7.TCR2 000C 1A4Dh, MTU9.TCR2 000C 15A8h —...
Page 362 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  MTU5.TCR2U, MTU5.TCR2V, MTU5.TCR2W Address(es): MTU5.TCR2U 000C 1C85h, MTU5.TCR2V 000C 1C95h, MTU5.TCR2W 000C 1CA5h — — — CKEG[1:0] TPSC2[2:0] Value after reset: Symbol Bit Name Description b2 to b0 TPSC2[2:0] Time Prescaler Select Refer to Table 20.10.
Page 363 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.7 TPSC[2:0], TPSC2[2:0] (MTU1) TCR2 register TCR register Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 Channel TPSC2[2] TPSC2[1] TPSC2[0] TPSC[2] TPSC[1] TPSC[0] Description MTU1 Internal clock: counts on PCLKA/1 Internal clock: counts on PCLKA/4 Internal clock: counts on PCLKA/16 Internal clock: counts on PCLKA/64...
Page 364 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.9 TPSC[2:0], TPSC2[2:0] (MTU3, MTU4, MTU6, MTU7) TCR2 register TCR register Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 Channel TPSC2[2] TPSC2[1] TPSC2[0] TPSC[2] TPSC[1] TPSC[0] Description MTU3 Internal clock: counts on PCLKA/1 MTU4...
Page 365: Timer Mode Register 1 (Tmdr1)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.3 Timer Mode Register 1 (TMDR1)  MTU0.TMDR1, MTU9.TMDR1 Address(es): MTU0.TMDR1 000C 1301h, MTU9.TMDR1 000C 1581h — MD[3:0] Value after reset:  MTU1.TMDR1, MTU2.TMDR1 Address(es): MTU1.TMDR1 000C 1381h, MTU2.TMDR1 000C 1401h — —...
Page 366 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.11 Operating Mode Setting by MD[3:0] Bits (MTU0 to MTU4, MTU6, MTU7, and MTU9) Bit 3 Bit 2 Bit 1 Bit 0 MD[3] MD[2] MD[1] MD[0] Description     ...
Page 367: Timer Mode Registers 2 (Tmdr2A, Tmdr2B)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (MTU7.TMDR1) should be set to 0. In MTU1 and MTU2, which have no TGRD, this bit is reserved. It is read as 0. The write value should be 0. Refer to Figure 20.49 for an illustration of the Tb interval in complementary PWM mode. BFE Bit (Buffer Operation E) This bit specifies whether to operate MTU0.TGRE and MTU0.TGRF, and MTU9.TGRE and MTU9.TGRF in the normal way or to use them together for buffer operation.
Page 368: Timer Mode Register 3 (Tmdr3)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.5 Timer Mode Register 3 (TMDR3) Address(es): MTU1.TMDR3 000C 1391h PHCKS — — — — — — Value after reset: Symbol Bit Name Description MTU1/MTU2 Combination 0: 16-bit access is enabled. Longword Access Control 1: 32-bit access is enabled.
Page 369: Timer I/O Control Register (Tior)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.6 Timer I/O Control Register (TIOR)  MTU0.TIORH, MTU1.TIOR, MTU2.TIOR, MTU3.TIORH, MTU4.TIORH, MTU6.TIORH, MTU7.TIORH, MTU9.TIORH Address(es): MTU0.TIORH 000C 1302h, MTU1.TIOR 000C 1382h, MTU2.TIOR 000C 1402h, MTU3.TIORH 000C 1204h, MTU4.TIORH 000C 1206h, MTU6.TIORH 000C 1A04h, MTU7.TIORH 000C 1A06h, MTU9.TIORH 000C 1582h IOB[3:0] IOA[3:0] Value after reset:...
Page 370 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  MTU0.TIORL, MTU3.TIORL, MTU4.TIORL, MTU6.TIORL, MTU7.TIORL, MTU9.TIORL Address(es): MTU0.TIORL 000C 1303h, MTU3.TIORL 000C 1205h, MTU4.TIORL 000C 1207h, MTU6.TIORL 000C 1A05h, MTU7.TIORL 000C 1A07h, MTU9.TIORL 000C 1583h IOD[3:0] IOC[3:0] Value after reset: Symbol Bit Name Description b3 to b0...
Page 371 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.13 TIORH (MTU0) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU0.TGRB Function MTIOC0B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 372 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.15 TIOR (MTU1) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU1.TGRB Function MTIOC1B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 373 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.17 TIORH (MTU3) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU3.TGRB Function MTIOC3B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 374 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.19 TIORH (MTU4) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU4.TGRB Function MTIOC4B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 375 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.21 TIORH (MTU6) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU6.TGRB Function MTIOC6B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 376 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.23 TIORH (MTU7) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU7.TGRB Function MTIOC7B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 377 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.25 TIORH (MTU9) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU9.TGRB Function MTIOC9B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 378 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.27 TIORH (MTU0) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA[3] IOA[2] IOA[1] IOA[0] MTU0.TGRA Function MTIOC0A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 379 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.29 TIOR (MTU1) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA[3] IOA[2] IOA[1] IOA[0] MTU1.TGRA Function MTIOC1A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 380 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.31 TIORH (MTU3) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA[3] IOA[2] IOA[1] IOA[0] MTU3.TGRA Function MTIOC3A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 381 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.33 TIORH (MTU4) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA[3] IOA[2] IOA[1] IOA[0] MTU4.TGRA Function MTIOC4A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 382 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.35 TIORH (MTU6) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA[3] IOA[2] IOA[1] IOA[0] MTU6.TGRA Function MTIOC6A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 383 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.37 TIORH (MTU7) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA[3] IOA[2] IOA[1] IOA[0] MTU7.TGRA Function MTIOC7A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 384 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.39 TIORH (MTU9) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA[3] IOA[2] IOA[1] IOA[0] MTU9.TGRA Function MTIOC9A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match. Initial output is low.
Page 385 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.41 TIORU, TIORV, and TIORW (MTU5) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description MTU5.TGRU, MTU5.TGRV, IOC[4] IOC[3] IOC[2] IOC[1] IOC[0] MTU5.TGRW Function MTIC5U, MTIC5V, MTIC5W Pin Function Output compare register No function Setting prohibited...
Page 386: Timer Compare Match Clear Register (Tcntcmpclr)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.7 Timer Compare Match Clear Register (TCNTCMPCLR) Address(es): MTU5.TCNTCMPCLR 000C 1CB6h CMPCL CMPCL CMPCL — — — — — Value after reset: Symbol Bit Name Description CMPCLR5W TCNT Compare Clear 5W 0: Disables MTU5.TCNTW to be cleared to 0000h at MTU5.TCNTW and MTU5.TGRW compare match or input capture 1: Enables MTU5.TCNTW to be cleared to 0000h at...
Page 387: Timer Interrupt Enable Register (Tier)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.8 Timer Interrupt Enable Register (TIER)  MTU1.TIER, MTU2.TIER Address(es): MTU1.TIER 000C 1384h, MTU2.TIER 000C 1404h TTGE — TCIEU TCIEV — — TGIEB TGIEA Value after reset:  MTU0.TIER, MTU3.TIER, MTU6.TIER, MTU9.TIER Address(es): MTU0.TIER 000C 1304h, MTU3.TIER 000C 1208h, MTU6.TIER 000C 1A08h, MTU9.TIER 000C 1584h TTGE —...
Page 388 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) TGIEA and TGIEB Bits (TGR Interrupt Enable A and B) Each bit enables or disables interrupt requests (TGIn) (n = A, B). TGIEC and TGIED Bits (TGR Interrupt Enable C and D) Each bit enables or disables an interrupt request (TGIn) (n = C, D).
Page 389 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) TTGE2 Bit (A/D Converter Start Request Enable 2) Each bit enables or disables A/D converter start requests by compare match between MTU0.TCNT and MTU0.TGRE, and MTU9.TCNT and MTU9.TGRE.  MTU5.TIER Address(es): MTU5.TIER 000C 1CB2h TGIE5 TGIE5V TGIE5 —...
Page 390: Timer Status Register (Tsr)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.9 Timer Status Register (TSR)  MTU1.TSR, MTU2.TSR Address(es): MTU1.TSR 000C 1385h, MTU2.TSR 000C 1405h TCFD — — — — — — — Value after reset:  MTU3.TSR, MTU4.TSR, MTU6.TSR, MTU7.TSR Address(es): MTU3.TSR 000C 122Ch, MTU4.TSR 000C 122Dh, MTU6.TSR 000C 1A2Ch, MTU7.TSR 000C 1A2Dh TCFD —...
Page 391: Timer Buffer Operation Transfer Mode Register (Tbtm)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.10 Timer Buffer Operation Transfer Mode Register (TBTM)  MTU0.TBTM, MTU9.TBTM Address(es): MTU0.TBTM 000C 1326h, MTU9.TBTM 000C 15A6h — — — — — TTSE TTSB TTSA Value after reset:  MTU3.TBTM, MTU4.TBTM, MTU6.TBTM, MTU7.TBTM Address(es): MTU3.TBTM 000C 1238h, MTU4.TBTM 000C 1239h, MTU6.TBTM 000C 1A38h, MTU7.TBTM 000C 1A39h —...
Page 392: Timer Input Capture Control Register (Ticcr)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.11 Timer Input Capture Control Register (TICCR) Address(es): MTU1.TICCR 000C 1390h — — — — I2BE I2AE I1BE I1AE Value after reset: Symbol Bit Name Description I1AE Input Capture Enable 0: Does not include the MTIOC1A pin in the MTU2.TGRA input capture conditions 1: Includes the MTIOC1A pin in the MTU2.TGRA input capture conditions...
Page 393: Timer Synchronous Clear Register (Tsycr)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.12 Timer Synchronous Clear Register (TSYCR) Address(es): MTU6.TSYCR 000C 1A50h CE0A CE0B CE0C CE0D CE1A CE1B CE2A CE2B Value after reset: Symbol Bit Name Description CE2B Clear Enable 2B 0: Disables counter clearing by the MTU2.TGIB2 interrupt generation timing. 1: Enables counter clearing by the MTU2.TGIB2 interrupt generation timing.
Page 394: Timer Counter (Tcnt)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.13 Timer Counter (TCNT) Address(es): MTU0.TCNT 000C 1306h, MTU1.TCNT 000C 1386h, MTU2.TCNT 000C 1406h, MTU3.TCNT 000C 1210h, MTU4.TCNT 000C 1212h, MTU5.TCNTU 000C 1C80h, MTU5.TCNTV 000C 1C90h, MTU5.TCNTW 000C 1CA0h, MTU6.TCNT 000C 1A10h, MTU7.TCNT 000C 1A12h, MTU9.TCNT 000C 1586h Value after reset: Note: TCNT must not be accessed in 8 bits;...
Page 395: Timer General Register (Tgr)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.15 Timer General Register (TGR) Address(es): MTU0.TGRA 000C 1308h, MTU0.TGRB 000C 130Ah, MTU0.TGRC 000C 130Ch, MTU0.TGRD 000C 130Eh, MTU0.TGRE 000C 1320h, MTU0.TGRF 000C 1322h, MTU1.TGRA 000C 1388h, MTU1.TGRB 000C 138Ah, MTU2.TGRA 000C 1408h, MTU2.TGRB 000C 140Ah, MTU3.TGRA 000C 1218h, MTU3.TGRB 000C 121Ah, MTU3.TGRC 000C 1224h, MTU3.TGRD 000C 1226h, MTU3.TGRE 000C 1272h MTU4.TGRA 000C 121Ch, MTU4.TGRB 000C 121Eh, MTU4.TGRC 000C 1228h, MTU4.TGRD 000C 122Ah, MTU4.TGRE 000C 1274h, MTU4.TGRF 000C 1276h,...
Page 396: Timer Start Registers (Tstra, Tstrb, Tstr)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.17 Timer Start Registers (TSTRA, TSTRB, TSTR)  MTU.TSTRA (for MTU0, MTU1, MTU2, MTU3, MTU4, and MTU9 Address(es): MTU.TSTRA 000C 1280h CST4 CST3 — CST9 — CST2 CST1 CST0 Value after reset: Symbol Bit Name Description...
Page 397 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  MTU.TSTRB (for MTU6 and MTU7) Address(es): MTU.TSTRB 000C 1A80h CST7 CST6 — — — — — — Value after reset: Symbol Bit Name Description b5 to b0 — Reserved These bits are read as 0. The write value should be 0. CST6 Counter Start 6 0: MTU6.TCNT counting is stopped...
Page 398: Timer Synchronous Registers (Tsyra, Tsyrb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.18 Timer Synchronous Registers (TSYRA, TSYRB)  MTU.TSYRA (for MTU0 to MTU4 and MTU9) Address(es): MTU.TSYRA 000C 1281h SYNC4 SYNC3 — — SYNC9 SYNC2 SYNC1 SYNC0 Value after reset: Symbol Bit Name Description SYNC0 Timer Synchronous...
Page 399 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  MTU.TSYRB (for MTU6 and MTU7) Address(es): MTU.TSYRB 000C 1A81h SYNC7 SYNC6 — — — — — — Value after reset: Symbol Bit Name Description b5 to b0 — Reserved These bits are read as 0. The write value should be 0. SYNC6 Timer Synchronous 0: MTU6.TCNT operates independently (TCNT setting/clearing is not...
Page 400: Timer Counter Synchronous Start Register (Tcsystr)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.19 Timer Counter Synchronous Start Register (TCSYSTR) Address(es): MTU.TCSYSTR 000C 1282h SCH0 SCH1 SCH2 SCH3 SCH4 SCH9 SCH6 SCH7 Value after reset: Symbol Bit Name Description SCH7 Synchronous Start 7 0: Does not specify synchronous start for MTU7.TCNT R/(W)* 1: Specifies synchronous start for MTU7.TCNT SCH6...
Page 401 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) SCH3 Bit (Synchronous Start 3) This bit controls synchronous start of MTU3.TCNT. [Clearing condition]  When 1 is set to the TSTRA.CST3 bit while SCH3 = 1 SCH2 Bit (Synchronous Start 2) This bit controls synchronous start of MTU2.TCNT.
Page 402: Timer Read/Write Enable Registers (Trwera, Trwerb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.20 Timer Read/Write Enable Registers (TRWERA, TRWERB) Address(es): MTU.TRWERA 000C 1284h, MTU.TRWERB 000C 1A84h — — — — — — — Value after reset: Symbol Bit Name Description Read/Write Enable 0: Read/write access to the registers is disabled 1: Read/write access to the registers is enabled b7 to b1 —...
Page 403: Timer Output Master Enable Registers (Toera, Toerb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.21 Timer Output Master Enable Registers (TOERA, TOERB)  MTU.TOERA Address(es): MTU.TOERA 000C 120Ah — — OE4D OE4C OE3D OE4B OE4A OE3B Value after reset: Symbol Bit Name Description OE3B Master Enable MTIOC3B 0: MTU output is disabled* 1: MTU output is enabled OE4A...
Page 404 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  MTU.TOERB Address(es): MTU.TOERB 000C 1A0Ah — — OE7D OE7C OE6D OE7B OE7A OE6B Value after reset: Symbol Bit Name Description OE6B Master Enable MTIOC6B 0: MTU output is disabled* 1: MTU output is enabled OE7A Master Enable MTIOC7A 0: MTU output is disabled*...
Page 405: Timer Output Control Registers 1 (Tocr1A, Tocr1B)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.22 Timer Output Control Registers 1 (TOCR1A, TOCR1B) Address(es): MTU.TOCR1A 000C 120Eh, MTU.TOCR1B 000C 1A0Eh — PSYE — — TOCL TOCS OLSN OLSP Value after reset: Symbol Bit Name Description OLSP Output Level Select P* Refer to Table 20.42.
Page 406 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.42 Output Level Select Function Bit 0 Function Compare Match Output OLSP Initial Output Active Level Up-Counting Down-Counting High level Low level Low level High level Low level High level High level Low level Table 20.43 Output Level Select Function...
Page 407: Timer Output Control Registers 2 (Tocr2A, Tocr2B)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.23 Timer Output Control Registers 2 (TOCR2A, TOCR2B) Address(es): MTU.TOCR2A 000C 120Fh, MTU.TOCR2B 000C 1A0Fh BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Value after reset: Symbol Bit Name Description OLS1P Output Level Select 1P* This bit selects the output level on MTIOC3B or MTIOC6B in reset-synchronized PWM mode and complementary PWM mode.
Page 408 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.45 MTIOCmD Output Level Select Function Bit 1 Function Compare Match Output OLS1N Initial Output Active Level Up-Counting Down-Counting High level Low level High level Low level Low level High level Low level High level m = 3, 6...
Page 409 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.50 Setting of TOCR2j.BF[1:0] Bits Bit 7 Bit 6 Description BF[1] BF[0] Complementary PWM Mode Reset-Synchronized PWM Mode Does not transfer data from the buffer register (TOLBRj) Does not transfer data from the buffer register to TOCR2j.
Page 410: Timer Output Level Buffer Registers (Tolbra, Tolbrb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.24 Timer Output Level Buffer Registers (TOLBRA, TOLBRB) Address(es): MTU.TOLBRA 000C 1236h, MTU.TOLBRB 000C 1A36h — — OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Value after reset: Symbol Bit Name Description OLS1P Output Level Select 1P Specify the buffer value to be transferred to the OLS1P bit in TOCR2j.
Page 411: Timer Gate Control Registers (Tgcra, Tgcrb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.25 Timer Gate Control Registers (TGCRA, TGCRB) Address(es): MTU.TGCRA 000C 120Dh, MTU.TGCRB 000C 1A0Dh — Value after reset: Symbol Bit Name Description Output Phase Switch These bits turn on or off the positive-phase/negative-phase output.
Page 412: Timer Subcounters (Tcntsa, Tcntsb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) BDC Bit (Brushless DC Motor) This bit selects whether to make the functions of TGCRA and TGCRB effective or ineffective. Table 20.51 Output Level Select Function Bit 2 Bit 1 Bit 0 Function MTIOC3B, MTIOC4A,...
Page 413: Timer Cycle Buffer Registers (Tcbra, Tcbrb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.28 Timer Cycle Buffer Registers (TCBRA, TCBRB) Address(es): MTU.TCBRA 000C 1222h, MTU.TCBRB 000C 1A22h Value after reset: Note: TCBRA and TCBRB must not be accessed in 8 bits; it should be accessed in 16 bits. TCBRA and TCBRB are 16-bit readable/writable registers, used only in complementary PWM mode, that function as buffer registers for TCDRA and TCDRB.
Page 414: Timer Dead Time Enable Registers (Tdera, Tderb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.30 Timer Dead Time Enable Registers (TDERA, TDERB) Address(es): MTU.TDERA 000C 1234h, MTU.TDERB 000C 1A34h — — — — — — — TDER Value after reset: Symbol Bit Name Description TDER Dead Time Enable 0: No dead time is generated R/(W) 1: Dead time is generated*...
Page 415: Timer Buffer Transfer Set Registers (Tbtera, Tbterb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.31 Timer Buffer Transfer Set Registers (TBTERA, TBTERB) Address(es): MTU.TBTERA 000C 1232h, MTU.TBTERB 000C 1A32h — — — — — — BTE[1:0] Value after reset: Symbol Bit Name Description b1, b0 BTE[1:0] Buffer Transfer Disable and These bits enable or disable transfer from the buffer registers* Interrupt Skipping Link Setting...
Page 416: Timer Waveform Control Registers (Twcra, Twcrb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.32 Timer Waveform Control Registers (TWCRA, TWCRB) Address(es): MTU.TWCRA 000C 1260h, MTU.TWCRB 000C 1A60h — — — — — Value after reset: Symbol Bit Name Description Waveform Retain Enable 0: Initial values specified in TOCR1A and TOCR2A (TOCR1B and R/(W)* TOCR2B) are output 1: Initial output is inhibited...
Page 417 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) SCC Bit (Synchronous Clearing Control) The setting of this bit selects whether MTU6.TCNT and MTU7.TCNT are or are not cleared when counter-synchronous clearing is generated for MTU0, MTU1, MTU2–MTU6, MTU7 in complementary PWM mode. Make the complementary PWM mode settings for MTU6 and MTU7 when this function is in use.
Page 418: Noise Filter Control Register N (Nfcrn) (N = 0 To 4, 6, 7, 9, C)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.33 Noise Filter Control Register n (NFCRn) (n = 0 to 4, 6, 7, 9, C)  MTU0.NFCR0, MTU1.NFCR1, MTU2.NFCR2, MTU3.NFCR3, MTU4.NFCR4, MTU6.NFCR6, MTU7.NFCR7, MTU9.NFCR9 Address(es): MTU0.NFCR0 000C 1290h, MTU1.NFCR1 000C 1291h, MTU2.NFCR2 000C 1292h, MTU3.NFCR3 000C 1293h, MTU4.NFCR4 000C 1294h, MTU6.NFCR6 000C 1A93h, MTU7.NFCR7 000C 1A94h, MTU9.NFCR9 000C 1296h —...
Page 419 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) NFCS[1:0] Bits (Noise Filter Clock Select) These bits set the sampling interval for the noise filters. When setting the NFCS[1:0] bits, wait for two cycles of the selected sampling interval before setting the input-capture function. When the NFCS[1:0] bits are set to 11b, i.e. selecting the external clock as the source to drive counting, wait for two cycles of the external clock before setting the input capture function.
Page 420: Noise Filter Control Register 5 (Nfcr5)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.34 Noise Filter Control Register 5 (NFCR5) Address(es): MTU5.NFCR5 000C 1A95h NFWE — — NFCS[1:0] — NFVEN NFUEN Value after reset: Symbol Bit Name Description NFUEN Noise Filter U Enable 0: The noise filter for the MTIOC5U pin is disabled. 1: The noise filter for the MTIOC5U pin is enabled.
Page 421: Timer A/D Converter Start Request Control Register (Tadcr)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.35 Timer A/D Converter Start Request Control Register (TADCR)  MTU4.TADCR Address(es): MTU4.TADCR 000C 1240h BF[1:0] — — — — — — UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Value after reset: Symbol Bit Name Description...
Page 422 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.53 Setting of Transfer Timing by TADCR.BF[1:0] Bits (MTU4) Bit 15 Bit 14 Description In Complementary PWM In Reset-Synchronized BF[1] BF[0] Mode PWM Mode In PWM Mode 1 In Normal Mode Data is not transferred from Data is not transferred from Data is not transferred from...
Page 423 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  MTU7.TADCR Address(es): MTU7.TADCR 000C 1A40h BF[1:0] — — — — — — UT7AE DT7AE UT7BE DT7BE ITA6AE ITA7VE ITB6AE ITB7VE Value after reset: Symbol Bit Name Description ITB7VE TCIV7 Interrupt Skipping Link 0: A/D converter start request signal TRG7BN and TCI7V Enable* interrupt skipping 1 are not linked...
Page 424 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.54 Setting of Transfer Timing by TADCR.BF[1:0] Bits (MTU7) Bit 15 Bit 14 Description In Complementary PWM In Reset-Synchronized BF[1] BF[0] Mode PWM Mode In PWM Mode 1 In Normal Mode Data is not transferred from Data is not transferred from Data is not transferred from...
Page 425: Timer A/D Converter Start Request Cycle Set Registers (Tadcora, Tadcorb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.36 Timer A/D Converter Start Request Cycle Set Registers (TADCORA, TADCORB) Address(es): MTU4.TADCORA 000C 1244h, MTU4.TADCORB 000C 1246h, MTU7.TADCORA 000C 1A44h, MTU7.TADCORB 000C 1A46h Value after reset: Note: TADCORA and TADCORB must not be accessed in 8 bits; it should be accessed in 16 bits. Note 1.
Page 426: Timer Interrupt Skipping Mode Registers (Titmra, Titmrb)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.38 Timer Interrupt Skipping Mode Registers (TITMRA, TITMRB) Address(es): MTU.TITMRA 000C 123Ah, MTU.TITMRB 000C 1A3Ah — — — — — — — TITM Value after reset: Symbol Bit Name Description TITM Interrupt Skipping Function Select Selects one of the two types of interrupt skipping functions shown in Table 20.55.
Page 427: Timer Interrupt Skipping Set Registers 1 (Titcr1A, Titcr1B)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.39 Timer Interrupt Skipping Set Registers 1 (TITCR1A, TITCR1B)  MTU.TITCR1A Address(es): MTU.TITCR1A 000C 1230h T3AEN T3ACOR[2:0] T4VEN T4VCOR[2:0] Value after reset: Symbol Bit Name Description b2 to b0 T4VCOR[2:0] TCIV4 Interrupt Skipping Count These bits specify the TCIV4 interrupt skipping count within Setting the range from 0 to 7.*...
Page 428 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.56 Setting of Interrupt Skipping Count by T4VCOR[2:0] Bits Bit 2 Bit 1 Bit 0 T4VCOR[2] T4VCOR[1] T4VCOR[0] Description Does not skip TCIV4 interrupts. Sets the TCIV4 interrupt skipping count to 1. Sets the TCIV4 interrupt skipping count to 2.
Page 429 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.59 Setting of Interrupt Skipping Count by T6ACOR[2:0] Bits Bit 6 Bit 5 Bit 4 T6ACOR[2] T6ACOR[1] T6ACOR[0] Description Does not skip TGIA6 interrupts. Sets the TGIA6 interrupt skipping count to 1. Sets the TGIA6 interrupt skipping count to 2.
Page 430: Timer Interrupt Skipping Counters 1 (Titcnt1A, Titcnt1B)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.40 Timer Interrupt Skipping Counters 1 (TITCNT1A, TITCNT1B)  MTU.TITCNT1A Address(es): MTU.TITCNT1A 000C 1231h — T3ACNT[2:0] — T4VCNT[2:0] Value after reset: Symbol Bit Name Description b2 to b0 T4VCNT[2:0] TCIV4 Interrupt Counter While the T4VEN bit in TITCR1A is set to 1, the count in these bits is incremented every time a TCIV4 interrupt occurs.
Page 431 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  MTU.TITCNT1B Address(es): MTU.TITCNT1B 000C 1A31h — T6ACNT[2:0] — T7VCNT[2:0] Value after reset: Symbol Bit Name Description b2 to b0 T7VCNT[2:0] TCIV7 Interrupt Counter While the T7VEN bit in TITCR1B is set to 1, the count in these bits is incremented every time a TCIV7 interrupt occurs.
Page 432: Timer Interrupt Skipping Set Registers 2 (Titcr2A, Titcr2B)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.41 Timer Interrupt Skipping Set Registers 2 (TITCR2A, TITCR2B)  MTU.TITCR2A Address(es): MTU.TITCR2A 000C 123Bh — — — — — TRG4COR[2:0] Value after reset: Symbol Bit Name Description b2 to b0 TRG4COR[2:0] TRG4AN/TRG4BN Interrupt These bits specify the TRG4AN/TRG4BN interrupt skipping Skipping Count Setting...
Page 433 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  MTU.TITCR2B Address(es): MTU.TITCR2B 000C 1A3Bh — — — — — TRG7COR[2:0] Value after reset: Symbol Bit Name Description b2 to b0 TRG7COR[2:0] TRG7AN/TRG7BN Interrupt These bits specify the TRG7AN/TRG7BN interrupt skipping Skipping Count Setting count within the range from 0 to 7.
Page 434: Timer Interrupt Skipping Counters 2 (Titcnt2A, Titcnt2B)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.42 Timer Interrupt Skipping Counters 2 (TITCNT2A, TITCNT2B)  MTU.TITCNT2A Address(es): MTU.TITCNT2A 000C 123Ch — — — — — TRG4CNT[2:0] Value after reset: Symbol Bit Name Description b2 to b0 TRG4CNT[2:0] TRG4AN/TRG4BN These bits start counting from the value set in TRG4COR[2:0] Interrupt Counter and the count decrements every time TRG4AN or TRG4BN is...
Page 435: A/D Conversion Start Request Select Register 0 (Tadstrgr0)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  MTU.TITCNT2B Address(es): MTU.TITCNT2B 000C 1A3Ch — — — — — TRG7CNT[2:0] Value after reset: Symbol Bit Name Description b2 to b0 TRG7CNT[2:0] TRG7AN/TRG7BN These bits start counting from the value set in TRG7COR[2:0] Interrupt Counter and the count decrements every time TRG7AN or TRG7BN is generated.
Page 436: A/D Conversion Start Request Select Register 1 (Tadstrgr1)
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.44 A/D Conversion Start Request Select Register 1 (TADSTRGR1) Address(es): MTU.TADSTRGR1 000C 1D32h — — — TADSTRS1[4:0] Value after reset: Symbol Bit Name Description b4 to b0 TADSTRS1[4:0] A/D Conversion Start Request These bits select the A/D conversion start request for Select for ADSM1 Pin Output generating the frame synchronization signal to be output from...
Page 437: Bus Master Interface
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.2.45 Bus Master Interface The timer counters (MTU0.TCNT to MTU7.TCNT, and MTU9.TCNT), general registers (MTU0.TGRn to MTU7.TGRn, and MTU9.TGRn), timer subcounters (TCNTSA and TCNTSB), timer cycle buffer registers (TCBRA and TCBRB), timer dead time data registers (TDDRA and TDDRB), timer cycle data registers (TCDRA and TCDRB), timer A/D converter start request control registers (MTU4.TADCR and MTU7.TADCR), timer A/D converter start request cycle set registers (MTU4.TADCORA, MTU4.TADCORB, MTU7.TADCORA, and MTU7.TADCORB), and timer A/D converter start request cycle set buffer registers (MTU4.TADCOBRA, MTU4.TADCOBRB,...
Page 438: Counter Operation
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3 Operation 20.3.1 Basic Functions Each channel has TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR register can be used as an input capture register or an output compare register. (1) Counter Operation When one of bits CST0 to CST4 and CST9 in the TSTRA register, bits CST6 and CST7 in the TSTRB register, and bits CSTU5, CSTV5, and CSTW5 in the MTU5.TSTR register is set to 1, TCNT for the corresponding channel begins...
Page 439 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (b) Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the TCNT counters are all designated as free-running counters. When the relevant bit in TSTRA, TSTRB, or MTU5.TSTR is set to 1, the corresponding TCNT counter starts up-count operation as a free- running counter.
Page 440 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (2) Waveform Output by Compare Match Upon compare match, low, high, or toggle output from the corresponding pin can be performed. (a) Example of Procedure for Setting Waveform Output by Compare Match Figure 20.8 shows an example of the procedure for setting waveform output by compare match Output selection [1] Enable TOERA output when outputting a...
Page 441 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (b) Examples of Waveform Output Operation Figure 20.9 shows an example of low output and high output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that high is output by compare match A and low is output by compare match B.
Page 442: Input Capture Function
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the MTIOCnm pin (n = 0 to 4, 6, 7, 9; m = A to D) input edge.
Page 443 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (b) Example of Input Capture Operation Figure 20.12 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the MTIOCnA pin input capture input edge, the falling edge has been selected as the MTIOCnB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 444: Synchronous Operation
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be modified simultaneously (synchronous setting). In addition, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR.
Page 445 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (2) Example of Synchronous Operation Figure 20.14 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for MTU0 to MTU 2, MTU0.TGRB compare match has been set as the counter clearing source in MTU0, and synchronous clearing has been set for the counter clearing source in MTU1 and MTU2.
Page 446: Buffer Operation
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.3 Buffer Operation Buffer operation, provided for MTU0, MTU3, MTU4, MTU6, MTU7, and MTU9, enables TGRC and TGRD to be used as buffer registers. In MTU0 and MTU9, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 447 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  When TGR is an input capture register When an input capture occurs, the value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the buffer register. This operation is illustrated in Figure 20.16.
Page 448 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) TCNT value MTU0.TGRB 0520h 0450h 0200h MTU0.TGRA Time 0000h 0450h 0520h MTU0.TGRC 0200h Transfer 0200h 0450h MTU0.TGRA MTIOC0A Figure 20.18 Example of Buffer Operation (1) (b) When TGR is an Input Capture Register Figure 20.19 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC.
Page 449 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (3) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for MTU0 and MTU9 or in PWM mode 1 for MTU3, MTU4, MTU6, and MTU7 by setting the buffer operation transfer mode registers (MTUn.TBTM (n = 0, 3, 4, 6, 7, 9)).
Page 450: Cascaded Operation
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.4 Cascaded Operation In cascaded operation, two 16-bit counters in different channels are used together as a 32-bit counter. There are two functions for connecting MTU1 and MTU2 to use as a 32-bit counter: cascade connection to be set when the MTU1.TMDR3.LWA bit is 0, and cascade connection 32-bit phase counting mode to be set when the MTU1.TMDR3.LWA bit is 1.
Page 451 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (1) Example of Cascaded Operation Setting Procedure Figure 20.21 shows an example of the cascaded operation setting procedure. Cascaded operation Set cascading [1] Set bits TPSC[2:0] in TCR to 111b in MTU1 to select MTU2.TCNT overflow/underflow counting.
Page 452 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (3) Cascaded Operation Example (b) Figure 20.23 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the I2AE bit in TICCR has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the MTU1.TIOR.IOA[3:0] bits have selected the MTIOC1A rising edge for the input capture timing while the MTU2.TIOR.IOA[3:0] bits have selected the MTIOC2A rising edge for the input capture timing.
Page 453 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (4) Cascaded Operation Example (c) Figure 20.24 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE and I1AE bits have been set to 1 to include the MTIOC2A and MTIOC1A pins in the MTU1.TGRA and MTU2.TGRA input capture conditions, respectively.
Page 454 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (5) Cascaded Operation Example (d) Figure 20.25 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE bit has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the IOA[3:0] bits in MTU1.TIOR have selected occurrence of MTU0.TGRA compare match or input capture for the input capture timing while the IOA[3:0] bits in MTU2.TIOR have selected the MTIOC2A rising edge for the input capture timing.
Page 455: Pwm Modes
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.5 PWM Modes PWM modes are provided to output PWM waveforms from the external pins. The output level can be selected as low, high, or toggle output in response to a compare match of each TGR. PWM waveforms in the range of 0% to 100% duty cycle can be output according to the TGR settings.
Page 456 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (b) PWM Mode 2 PWM waveform output is generated using one TGR as the cycle register and the others as duty registers. The level specified in TIOR is output at compare matches. Upon counter clearing by a cycle register compare match, the initial value set in TIOR is output from each pin.
Page 457 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (1) Example of PWM Mode Setting Procedure Figure 20.26 shows an example of the PWM mode setting procedure. PWM mode [1] Enable TOERA output when outputting a waveform from the MTIOC pin of MTU3 and MTU4.
Page 458 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Figure 20.28 shows an example of operation in PWM mode 2. In this example, synchronous operation is designated for MTU0 and MTU1, MTU1.TGRB compare match is set as the TCNT clearing source, and low is set as the initial output value and high as the output value for the other TGR registers (MTU0.TGRA to MTU0.TGRD and MTU1.TGRA), outputting 5-phase PWM waveforms.
Page 459 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Figure 20.29 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode 1. In this example, TGRA compare match is set as the TCNT clearing source, a low level is set as the initial output value and output value for TGRA, and a high level is set as the output value for TGRB.
Page 460: Phase Counting Mode
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.6 Phase Counting Mode There are two phase counting modes: 16-bit phase counting mode in which MTU1 and MTU2 operate independently, and cascade connection 32-bit phase counting mode in which MTU1 and MTU2 are cascaded. In phase counting mode, the phase difference between two external input clocks is detected and the corresponding TCNT is incremented or decremented.
Page 461 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (1) Example of 16-Bit Phase Counting Mode Setting Procedure Figure 20.30 shows an example of the phase counting mode setting procedure. 16-bit phase counting mode [1] Set the TMDR3.LWA bit of MTU1 to 0. Set the TMDR1.MD[3:0] bits to select the 16-bit select phase phase counting mode.
Page 462 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (2) Examples of 16-Bit Phase Counting Mode Operation In phase counting mode, TCNT is incremented or decremented according to the phase difference between two external clocks. There are five modes according to the count conditions. Each mode operates under the condition PHCKSEL = 1, which means the phase clock for MTU1 is input from MTCLKA or MTCLKB and that for MTU2 is input from MTCLKC or MTCLKD.
Page 463 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (b) Phase Counting Mode 2 Figure 20.32 to Figure 20.34 show the examples of operation in phase counting mode 2 and Table 20.69 summarizes the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2)
Page 464 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.69 Up-Counting and Down-Counting Conditions in Phase Counting Mode 2 MTCLKA (MTU1) MTCLKB (MTU1) PCB[1:0] MTCLKC (MTU2) MTCLKD (MTU2) Operation High Not counted (Don’t care) High Up-counting High High Down-counting High Not counted (Don’t care) Down-counting High...
Page 465 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Phase Counting Mode 3 Figure 20.35 to Figure 20.37 show the examples of operation in phase counting mode 3 and Table 20.70 summarizes the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value...
Page 466 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2 TCNT value Down-counting Up-counting Time Figure 20.37 Example of Operation in Phase Counting Mode 3 (When MTUn.TCR2.PCB[1:0] = 1xb (n = 1, 2)) Table 20.70 Up-Counting and Down-Counting Conditions in Phase Counting Mode 3 MTCLKA (MTU1) MTCLKB (MTU1)
Page 467 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (d) Phase Counting Mode 4 Figure 20.38 shows an example of operation in phase counting mode 4, and Table 20.71 summarizes the TCNT up- counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value...
Page 468 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (e) Phase Counting Mode 5 Figure 20.39 and Figure 20.40 show the examples of operation in phase counting mode 5 and Table 20.72 summarizes the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2)
Page 469 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.72 Up-Counting and Down-Counting Conditions in Phase Counting Mode 5 MTCLKA (MTU1) MTCLKB (MTU1) PCB[1:0] MTCLKC (MTU2) MTCLKD (MTU2) Operation High Not counted (Don’t care) High Up-counting High Not counted (Don’t care) High Up-counting High...
Page 470 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (3) 16-Bit Phase Counting Mode Application Example Figure 20.41 shows an example in which MTU1 is in phase counting mode, and MTU1 is coupled with MTU0 to input 2-phase encoder pulses of a servo motor in order to detect position or speed. MTU1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to MTCLKA and MTCLKB.
Page 471: Cascade Connection 32-Bit Phase Counting Mode
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.6.2 Cascade Connection 32-Bit Phase Counting Mode When MTU1 is set to phase counting mode by setting MTU1.TMDR3.LWA = 1, MTU1 and MTU2 are connected to operate in cascade connection 32-bit phase counting mode. When this mode is used, the TCR, TCR2, TIOR, TIER, TGR, and TSR registers are controlled by MTU1 and the settings of MTU2 are disabled.
Page 472: Reset-Synchronized Pwm Mode
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, six phases of positive and negative PWM waveforms (12 phases in total) that share a common wave transition point can be output by combining MTU3 and MTU4 and MTU6 and MTU7. When set for reset-synchronized PWM mode, the MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B, MTIOC4D, MTIOC6B, MTIOC6D, MTIOC7A, MTIOC7C, MTIOC7B, and MTIOC7D pins function as PWM output pins and timer counters 3 and 6 (MTU3.TCNT and MTU6.TCNT) functions as an up-counter.
Page 473 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (1) Example of Procedure for Setting Reset-Synchronized PWM Mode Figure 20.43 shows an example of procedure for setting the reset-synchronized PWM mode. [1] Clear the TSTRA.CST3 (TSTRB.CST6) and TSTRA.CST4 Reset-synchronized (TSTRB.CST7) bits to 0 to stop the TCNT count operation. PWM mode Specify the reset-synchronized PWM mode while MTU3.TCNT (MTU6.TCNT) and MTU4.TCNT (MTU7.TCNT) are stopped.
Page 474 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (2) Example of Reset-Synchronized PWM Mode Operation Figure 20.44 shows an example of operation in the reset-synchronized PWM mode. MTU3.TCNT and MTU4.TCNT (MTU6.TCNT and MTU7.TCNT) operate as up-counters. The counters are cleared when a compare match occurs between MTU3.TCNT (MTU6.TCNT) and MTU3.TGRA (MTU6.TGRA), and then begin incrementing from 0000h.
Page 475: Complementary Pwm Mode
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.8 Complementary PWM Mode In complementary PWM mode, dead time can be set for PWM waveforms to be output. The dead time is the period during which the upper and lower arm transistors are set to the inactive level in order to prevent short-circuiting of the arms.
Page 476 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.76 Register Settings for Complementary PWM Mode (1/2) Channel Counter/ Register Description Read/Write from CPU MTU3 TCNT Starts up-counting from the value set in the dead time Maskable by TRWERA setting* register TGRA Set MTU3.TCNT upper limit value (1/2 carrier cycle + dead...
Page 477 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.77 Register Settings for Complementary PWM Mode (2/2) Channel Counter/ Register Description Read/Write from CPU Timer dead time data register A Set MTU4.TCNT and MTU3.TCNT offset value (dead Maskable by TRWERA setting* (TDDRA) time value) Timer dead time data register B...
Page 478 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) MTU3. TCBRA TGRC MTU3. TDDRA TCDRA TGRA MTIOC3A Comparator Match signal MTIOC3B MTIOC3D MTU3. MTU4. TCNTSA TCNT TCNT MTIOC4A MTIOC4B MTIOC4C Comparator MTIOC4D Match signal External cutoff input POE0# MTU3. MTU4. MTU4. POE4# TGRB TGRA...
Page 479 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) MTU6. TCBRB TGRC MTU6. TDDRB TCDRB TGRA MTIOC6A Match Comparator signal MTIOC6B MTIOC6D MTU6. MTU7. TCNTSB TCNT TCNT MTIOC7A MTIOC7B MTIOC7C Comparator MTIOC7D Match signal External cutoff input POE0# MTU7. MTU6. MTU7. POE4# TGRB TGRB...
Page 480 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (1) Example of Complementary PWM Mode Setting Procedure Figure 20.47 shows an example of the complementary PWM mode setting procedure. [1] Clear the TSTRA.CST3 (TSTRB.CST6) and TSTRA.CST4 (TSTRB.CST7) bits to 0 to stop the TCNT count operation.
Page 481 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (2) Outline of Complementary PWM Mode Operation In complementary PWM mode, six phases (three positive and three negative) PWM waveforms can be output. Figure 20.48 illustrates counter operation in complementary PWM mode (MTU3 and MTU4), and Figure 20.49 shows an example of operation in complementary PWM mode.
Page 482 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (b) Register Operation In complementary PWM mode, nine registers (compare registers, buffer registers, and temporary registers) are used to control the duty ratio for the PWM output. Figure 20.49 shows an example of operation in complementary PWM mode (MTU3 and MTU4).
Page 483 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Transfer from temporary Transfer from temporary MTU3.TCNT register register MTU4.TCNT to compare register to compare register TCNTSA MTU3.TGRA TCNTSA TCDRA MTU3.TCNT MTU4.TGRA MTU4.TCNT MTU4.TGRC TDDRA 0000h Buffer register 6400h 0080h MTU4.TGRC 0080h Temporary register 6400h Compare register...
Page 484 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Initial Setting In complementary PWM mode, there are nine registers that require initial setting. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with MTU3.TMDR1.MD[3:0] (MTU6.TMDR1.MD[3:0]) bits, initial values should be set in the following registers.
Page 485 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (e) Dead Time Setting In complementary PWM mode, dead time can be set for PWM output. The dead time is set in the timer dead time data register (TDDRA or TDDRB). The value set in TDDRA (TDDRB) is used as the MTU3.TCNT (MTU6.TCNT) counter start value and creates a non-overlapping interval between MTU3.TCNT (MTU6.TCNT) and MTU4.TCNT (MTU7.TCNT).
Page 486 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (g) PWM Cycle Setting In complementary PWM mode, the PWM cycle is set in two registers—MTU3.TGRA (MTU6.TGRA), in which the MTU3.TCNT (MTU6.TCNT) upper limit value is set, and TCDRA (TCDRB), in which the MTU4.TCNT (MTU7.TCNT) upper limit value is set.
Page 487 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (h) Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five registers (PWM duty and PWM cycle registers) that have buffer registers and can be updated during operation.
Page 488 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Figure 20.52 Example of Data Updating in Complementary PWM Mode (MTU3 and MTU4) R01UH0576EJ0100 Rev.1.00 Page 488 of 1230 Nov 30, 2015...
Page 489 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of the OLSN and OLSP bits in the TOCR1A (TOCR1B) register or the OLS1N to OLS3N and OLS1P to OLS3P bits in the TOCR2A register (TOCR2B). This initial output is the non-active level of the PWM output and continues from when complementary PWM mode is set with the MTU3.TMDR1 (MTU6.TMDR1) until MTU4.TCNT (MTU7.TCNT) exceeds the value set in the TDDRA (TDDRB) register.
Page 490 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Timer output control register settings TOCR1A.OLSN bit = 0 (initial output: high; active level: low) TOCR1A.OLSP bit = 0 (initial output: high; active level: low) MTU3.TCNT MTU4.TCNT MTU3.TCNT value MTU4.TCNT TCNTSA MTU3.TCNT MTU4.TCNT TDDRA MTU4.TGRA...
Page 491 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Method for Generating PWM Output in Complementary PWM Mode In complementary PWM mode, six phases (three positive and three negative) PWM waveforms can be output. Dead time can be set for PWM waveforms to be output. A PWM waveform is generated by output of the level selected in the timer output control register in the event of a compare match between a counter and a compare register.
Page 492 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) T1 interval T2 interval T1 interval Counter for generating MTU3.TGRA a turn-off timing Counter for generating TEMP2 a turn-on timing TCDRA MTU4.TGRA TDDRA 0000h Don't care Positive-phase output Negative-phase output Output waveform is active-low. Buffer operation is set for transfer at the crest or trough.
Page 493 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 0% and 100% Duty Ratio Output in Complementary PWM Mode In complementary PWM mode, 0% and 100% duty PWM output can be output as required. Figure 20.58 to Figure 20.62 show output examples. A 100% duty waveform is output when the compare register value is set to 0000h.
Page 494 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) T1 interval T2 interval T1 interval Counter for generating MTU3.TGRA a turn-off timing TEMP2 Counter for generating a turn-on timing TCDRA MTU4.TGRA TDDRA 0000h 0% duty ratio output Positive-phase Don't care output 100% duty ratio output Negative-phase output...
Page 495 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) T1 interval T2 interval T1 interval Counter for generating a turn-off timing MTU3.TGRA Counter for generating MTU4.TGRA a turn-on timing TCDRA MTU3.TCNT MTU4.TCNT TDDRA 0000h Don't care 0% duty ratio output Positive-phase output 100% duty ratio output Negative-phase...
Page 496 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (m) Counter Clearing by Another Channel In complementary PWM mode, MTU3.TCNT, MTU4.TCNT, and TCNTSA (MTU6.TCNT, MTU7.TCNT, and TCNTSB) can be cleared by another channel source when a mode for synchronization with another channel is specified through the TSYRA (TSYRB) register and synchronous clearing is selected with MTU3.TCR.CCLR[2:0] (MTU6.TCR.CCLR[2:0]) bits.
Page 497 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCRA (TWCRB) to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval (Tb2 interval) at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing.
Page 498: Pwm Mode
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode. An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in Figure 20.66.
Page 499 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figure 20.67 to Figure 20.70 show examples of output waveform control in which MTU3 and MTU4 operate in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCRA is set to 1.
Page 500 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Synchronous clearing WRE bit = 1 MTU3.TCNT MTU4.TCNT MTU3.TGRA TCNTSA TCDRA MTU3.TGRB MTU3.TCNT MTU4.TCNT TDDRA 0000h Positive- phase output Negative-phase output (Output waveform is active-low) Figure 20.69 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 20.65;...
Page 501 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (o) Suppressing Synchronous Counter Clearing for MTU0 to MTU2, and MTU6 and MTU7 In MTU6 and MTU7, setting the SCC bit in TWCRB to 1 suppresses synchronous counter clearing caused by MTU0 to MTU2.
Page 502 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  Example of Procedure for Suppressing Synchronous Counter Clearing for MTU0 to MTU2, and MTU6 and MTU7 An example of the procedure for suppressing synchronous counter clearing for MTU0 to MTU2, and MTU6 and MTU7 is shown in Figure 20.72.
Page 503 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d)  Examples of Suppression of Synchronous Counter Clearing for MTU 0 to MTU2, and MTU6 and MTU7 Figure 20.73 to Figure 20.76 show examples of operation in which MTU6 and MTU7 operate in complementary PWM mode and synchronous counter clearing for MTU 0 to MTU2, and MTU6 and MTU7 is suppressed by setting the SCC bit in TWCRB in MTU6 and MTU7 to 1.
Page 504 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) WRE bit = 1 Synchronous clearing for MTU6.TCNT SCC bit = 1 MTU0 to MTU2 and MTU6 and MTU7 MTU7.TCNT TCNTSA MTU6.TGRA TCDRB MTU6.TGRB MTU6. TCNT MTU7. TCNT Counters are not cleared TDDRB 0000h Positive-phase...
Page 505 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (p) Counter Clearing by MTU3.TGRA (MTU6.TGRA) Compare Match In complementary PWM mode, MTU3.TCNT, MTU4.TCNT, and TCNTSA (MTU6.TCNT, MTU7.TCNT, and TCNTSB) can be cleared by MTU3.TGRA (MTU6.TGRA) compare match when the TWCRA.CCE (TWCRB.CCE) bit. Figure 20.77 illustrates an operation example.
Page 506 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (q) Example of Waveform Output for Driving AC Synchronous Motor (Brushless DC Motor) In complementary PWM mode, a brushless DC motor can easily be controlled using the TGCRA (TGCRB) register. Figure 20.78 to Figure 20.81 show examples of brushless DC motor driving waveforms when MTU3 and MTU4 are used.
Page 507 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) External input MTIOC0A pin MTIOC0B pin MTIOC0C pin 6-phase output MTIOC3B pin MTIOC3D pin MTIOC4A pin MTIOC4C pin MTIOC4B pin MTIOC4D pin ■ When TGCRA (TGCRB).BDC = 1, TGCRA (TGCRB).N = 1, TGCRA (TGCRB).P = 1, TGCRA (TGCRB).FB = 0, and output active level = high Figure 20.79 Example of Output Phase Switching by External Input (2)
Page 508 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) A/D Converter Start Request Setting In complementary PWM mode, an A/D converter start request can be issued using MTU3.TGRA (MTU6.TGRA) compare match, MTU4.TCNT (MTU7.TCNT) underflow (trough), or compare match on a channel other than MTU3 and MTU4 (MTU6 and MTU7).
Page 509 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Tb1 interval Tb2 interval Tb1 interval Tb2 interval Tb1 interval MTU3.TGRA TCNTSA TCDRA MTU3. TCNT MTU4. TCNT MTU4.TGRB TDDRA Buffer A modified MTU4.TGRD 1111h 1211h (buffer A) Buffer B modified MTU4.TGRF 1210h 1110h (buffer B) Temp3A...
Page 510 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) MTU3.TGRA TCNTSA TCDRA MTU3. TCNT MTU4. TCNT MTU4.TGRB TDDRA Buffer A modified MTU4.TGRD 1111h 1211h (buffer A) Buffer B modified MTU4.TGRF 1110h 1210h (buffer B) Temp3A 1111h 1211h (temporary A) Temp3B 1110h 1210h (temporary B) MTU4.TGRB...
Page 511 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (3) Interrupt Skipping Function 1 in Complementary PWM Mode Interrupts TGIA3 (TGIA6) (at the crest) and TCIV4 (TCIV7) (at the trough) in MTU3 and MTU4 (MTU6 and MTU7) can be skipped up to seven times by making settings in the TITCR1A (TITCR1B) register. Transfers from a buffer register to a temporary register or a compare register can be skipped in coordination with interrupt skipping by making settings in the TBTERA (TBTERB) register.
Page 512 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) MTU3.TCNT MTU4.TCNT TCNTSA MTU3.TCNT MTU4.TCNT Period during Period during Period during Period during which skipping which skipping which skipping which skipping count can be count can be count can be count can be changed changed changed...
Page 513 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Buffer Transfer Control Linked with Interrupt Skipping In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the BTE[1:0] bits in the TBTERA (TBTERB) register. Figure 20.88 shows an example of operation when buffer transfer is disabled (BTE[1:0] = 01b).
Page 514 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) MTU3.TCNT MTU4.TCNT (1) When the buffer register is modified within one carrier cycle after a TGIA3 interrupt TCNTSA TGIA3 generated TGIA3 generated MTU3. TCNT MTU4. TCNT Timing for modifying Timing for modifying the buffer register the buffer register Buffer transfer-enabled period...
Page 515 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) MTU3.TCNT MTU4.TCNT TCNTSA Skipping counter TITCNT1A.T3ACNT[2:0] bits Skipping counter TITCNT1A.T4VCNT[2:0] bits Buffer transfer-enabled period (TITCNT1A.T3AEN bit is set to 1) Buffer transfer-enabled period (TITCNT1A.T4VEN bit is set to 1) Buffer transfer-enabled period (TITCNT1A.T3AEN and T4VEN bits are set to 1) Note: The skipping count is set to three.
Page 516 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (4) Complementary PWM Mode Output Protection Functions The following output protection functions are provided for complementary PWM mode. (a) Register and Counter Miswrite Prevention Function Access from the CPU to the mode registers, control registers, compare registers, and counters can be enabled or disabled by setting the RWE bit in the TRWERA (TRWERB) register.
Page 517: A/D Converter Start Request Delaying Function
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.9 A/D Converter Start Request Delaying Function A/D converter start requests can be issued in MTU4 or MTU7 by making settings in the timer A/D converter start request control register (MTU4.TADCR or MTU7.TADCR), timer A/D converter start request cycle set registers (MTU4.TADCORA and MTU4.TADCORB, or MTU7.TADCORA and MTU7.TADCORB), and timer A/D converter start request cycle set buffer registers (MTU4.TADCOBRA and MTU4.TADCOBRB, or MTU7.TADCOBRA and MTU7.TADCOBRB).
Page 518 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (2) Basic Example of A/D Converter Start Request Delaying Function Operation Figure 20.92 shows a basic example of A/D converter start request signal (TRG4AN (TRG7AN)) operation when the trough of MTU4.TCNT (MTU7.TCNT) is specified for the buffer transfer timing and an A/D converter start request signal is output during MTU4.TCNT (MTU7.TCNT) down-counting.
Page 519 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (4) Buffer Transfer The data in the timer A/D converter start request cycle set registers (MTU4.TADCORA and MTU4.TADCORB, or MTU7.TADCORA and MTU7.TADCORB) is updated by writing data to the timer A/D converter start request cycle set buffer registers (MTU4.TADCOBRA and MTU4.TADCOBRB, or MTU7.TADCOBRA and MTU7.TADCOBRB).
Page 520 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (5) A/D Converter Start Request Delaying Function Linked with Interrupt Skipping Function 1 In complementary PWM mode, A/D converter start requests (TRG4AN and TRG4BN (TRG7AN and TRG7BN)) can be issued in coordination with interrupt skipping 1 by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE (ITA6AE, ITA7VE, ITB6AE, and ITB7VE) bits in the MTU4.TADCR (MTU7.TADCR) register.
Page 521 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) MTU4. TCNT MTU4.TADCORA TGIA3 interrupt skipping counter TCIV4 interrupt skipping counter TGIA3 A/D request- enabled period TCIV4 A/D request- enabled period A/D converter start request (TRG4AN) When linked with TGIA3 and TCIV4 interrupt skipping When linked with TGIA3 interrupt skipping...
Page 522 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (6) A/D Converter Start Request Delaying Function Linked with Interrupt Skipping Function 2 By setting the TITM bit to 1 in the TITMRA (TITMRB) register, the counter starts down-counting from the value (0 to 7) set in the TRG4COR[2:0] (TRG7COR[2:0]) bits in TITCR2A (TITCR2B) register every time an A/D converter start trigger (TRG4AN or TRG4BN (TRG7AN or TRG7BN)) is generated.
Page 523: Synchronous Operation Of Mtu0 To Mtu4, Mtu6, Mtu7, And Mtu9
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.10 Synchronous Operation of MTU0 to MTU4, MTU6, MTU7, and MTU9 (1) Synchronous Counter Start for MTU0 to MTU4, MTU6, MTU7, and MTU9 The counters in MTU0 to MTU4, MTU6, MTU7, and MTU9 can be started synchronously by making the TCSYSTR settings.
Page 524 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (2) Synchronous Counter Clearing for MTU6 and MTU7 The counters in MTU6 and MTU7 can be cleared by the TGImn interrupt generation timing (m = A to D; n = 0 to 2) through the TSYCR setting.
Page 525 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) TSYCR MTU0.TCNT Compare match between MTU0.TCNT and TGR value MTU0.TGRD MTU0. MTU0.TGRB TCNT MTU0.TGRC MTU0.TGRA 0000h Time MTU7.TCNT value MTU7. TCNT 0000h Time Figure 20.102 Example of Synchronous Counter Clearing for MTU6 and MTU7 (2) R01UH0576EJ0100 Rev.1.00 Page 525 of 1230 Nov 30, 2015...
Page 526: External Pulse Width Measurement
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.11 External Pulse Width Measurement The pulse widths of up to three external input lines can be measured in MTU5. When the IOC[4:0] bits in MTU5.TIORU, MTU5.TIORV, MTU5.TIORW are set for pulse width measurement, the pulse width of the signal input to the MTIC5U, MTIC5V, and MTIC5W pins are measured.
Page 527: Dead Time Compensation
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.12 Dead Time Compensation Figure 20.105 shows an example of the motor control circuit used to feed back a delay in the dead time (delay between complementary PWM output and inverter output) to MTU5. The MTU5 external pulse measurement function allows the delay between the complementary PWM output and inverter output to be measured and reflected in the duty ratio, which can be used as dead time compensation for the PWM output waveform in complementary PWM operation when MTU6 and MTU7 are used (Figure 20.106).
Page 528 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (1) Example of Dead Time Compensation Setting Procedure Figure 20.107 shows an example of dead time compensation setting procedure by using three counters in MTU5. Tdead Upper arm signal (Positive-phase output) Lower arm signal (Negative-phase output) Inverter output detection signal Dead time delay signal Tdelay...
Page 529: Tcntu, Tcntv, And Tcntw Capture At Crest And/Or Trough In Complementary Pwm Mode
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.13 TCNTU, TCNTV, and TCNTW Capture at Crest and/or Trough in Complementary PWM Mode The MTU5 external pulse width measurement function can be used to transfer the value in TCNTU, TCNTV, and TCNTW to TGRU, TGRV, and TGRW at the crest, or trough, or crest and trough.
Page 530: A/D Conversion Start Request Frame Synchronization Signal
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.3.15 A/D Conversion Start Request Frame Synchronization Signal This function can be used to monitor the generation timing of the A/D conversion start request signal using an external pin. When the A/D conversion request signal to be monitored is selected by the TADSTRGRn register (n = 0, 1), a pulse signal is output from the ADSMn pin that is at the high level when the A/D conversion start request signal is generated, and at the low level in the timer cycle used to generate the A/D conversion start request signal.
Page 531: Interrupt Sources
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.4 Interrupt Sources 20.4.1 Interrupt Sources and Priorities There are three kinds of interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own enable/disable bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
Page 532 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.79 MTU Interrupt Sources Channel Name Interrupt Source DTC Activation Priority MTU0 TGIA0 MTU0.TGRA input capture/compare match Possible High TGIB0 MTU0.TGRB input capture/compare match Possible TGIC0 MTU0.TGRC input capture/compare match Possible TGID0 MTU0.TGRD input capture/compare match Possible...
Page 533: Dtc Activation
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (1) Input Capture/Compare Match Interrupt If the TIER.TGIE bit is set to 1 when a TGR input capture/compare match occurs on a channel, an interrupt is requested. The MTU has 35 input capture/compare match interrupts (six for MTU0 and MTU9, four each for MTU3, MTU4, MTU6, and MTU7, two each for MTU1 and MTU2, and three for MTU5).
Page 534: A/D Converter Activation
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.4.3 A/D Converter Activation The A/D converter can be activated by one of the following three methods in the MTU. Table 20.80 shows the relationship between interrupt sources and A/D converter start request signals. (1) A/D Converter Activation by TGRA Input Capture/Compare Match or at MTU4.TCNT (MTU7.TCNT) Trough in Complementary PWM Mode The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel.
Page 535 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Table 20.80 Interrupt Sources and A/D Converter Start Request Signals Target Registers Interrupt Source A/D Converter Start Request Signal MTU0.TGRA and MTU0.TCNT Input capture/compare match TRGA0N MTU9.TGRA and MTU9.TCNT TRGA9N MTU9.TGRA and MTU9.TCNT, TRG9AEN MTU9.TGRE and MTU9.TCNT* MTU0.TGRA and MTU0.TCNT,...
Page 536: Operation Timing
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.5 Operation Timing 20.5.1 Input/Output Timing (1) TCNT Count Timing Figure 20.111 and Figure 20.112 show the TCNT count timing in internal clock operation, Figure 20.113 shows the TCNT count timing in external clock operation (normal mode), and Figure 20.114 shows the TCNT count timing in external clock operation (phase counting mode).
Page 537 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the value set in TIOR is output from MTIOCnm pin (n = 0 to 4, 6, 7, 9;...
Page 538 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (3) Input Capture Signal Timing Figure 20.117 shows the input capture signal timing. PCLKA Input capture input Input capture signal N + 1 N + 2 TCNT N + 2 Figure 20.117 Input Capture Input Signal Timing R01UH0576EJ0100 Rev.1.00 Page 538 of 1230...
Page 539 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (4) Timing for Counter Clearing by Compare Match/Input Capture FFigure 20.118 and Figure 20.119 show the timing when counter clearing on compare match is specified, and Figure 20.120 shows the timing when counter clearing on input capture is specified. PCLKA Compare match signal...
Page 540 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (5) Buffer Operation Timing Figure 20.121 to Figure 20.123 show the timing in buffer operation. PCLKA TCNT n + 1 Compare match signal TGRA, TGRB TGRC, TGRD Figure 20.121 Buffer Operation Timing (Compare Match) PCLKA Input capture signal...
Page 541 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (6) Buffer Transfer Timing (Complementary PWM Mode) Figure 20.124 to Figure 20.126 show the buffer transfer timing in complementary PWM mode. PCLKA TCNTS 0000h MTU4.TGRD write signal Temporary register transfer signal Buffer register Temporary register Figure 20.124 Transfer Timing from Buffer Register to Temporary Register (TCNTSA Stopped)
Page 542: Interrupt Signal Timing
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.5.2 Interrupt Signal Timing (1) TGI Interrupt Timing by Compare Match Figure 20.127 and Figure 20.128 show the TGI interrupt request signal timing when a compare match occurs. PCLKA TCNT input clock TCNT N + 1 Compare...
Page 543 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (2) TGI Interrupt Timing by Input Capture Figure 20.129 and Figure 20.130 show the TGI interrupt request signal timing when an input capture occurs. PCLKA Input capture signal TCNT Interrupt signal Figure 20.129 TGI Interrupt Timing (Input Capture) (MTU0 to MTU4, MTU6, MTU7, and MTU9) PCLKA Input capture...
Page 544 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (3) TCIV and TCIU Interrupt Timing Figure 20.131 shows the TCIV interrupt request signal timing when an overflow is generated. Figure 20.132 shows the TCIU interrupt request signal timing when an underflow is generated. PCLKA TCNT input clock...
Page 545: Usage Notes
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6 Usage Notes 20.6.1 Module Stop Function Setting MTU operation can be disabled or enabled using the module stop control register. MTU operation is stopped with the initial setting. Register access is enabled by releasing the module clock stop state. For details, refer to section 11, Low Power Consumption.
Page 546: Contention Between Tcnt Write And Clear Operations
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the TCNT write cycle, TCNT clearing takes precedence and TCNT write operation is not performed. Figure 20.134 shows the timing in this case. Written by CPU PCLKA Counter...
Page 547: Contention Between Tgr Write Operation And Compare Match
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.6 Contention between TGR Write Operation and Compare Match If a compare match occurs in a TGR write cycle, TGR write operation is executed and the compare match signal is also generated. Figure 20.136 shows the timing in this case.
Page 548: Contention Between Buffer Register Write And Tcnt Clear Operations
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.8 Contention between Buffer Register Write and TCNT Clear Operations When the buffer transfer timing is set at the TCNT clear timing by the timer buffer transfer mode register (TBTM), if TCNT clearing occurs in the TGR write cycle, the data before write operation is transferred to TGR by the buffer operation.
Page 549: Contention Between Tgr Write Operation And Input Capture
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.10 Contention between TGR Write Operation and Input Capture If an input capture signal is generated in the TGR write cycle, the input capture operation takes precedence and the TGR write operation is not performed in MTU0 to MTU4, MTU6, MTU7, and MTU9. In MTU5, the TGR write operation is performed and the input capture signal is generated.
Page 550: Contention Between Buffer Register Write Operation And Input Capture
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.11 Contention between Buffer Register Write Operation and Input Capture If an input capture signal is generated in the buffer register write cycle, the buffer operation takes precedence and the buffer register write operation is not performed. Figure 20.142 shows the timing in this case.
Page 551: Contention Between Mtu2.Tcnt Write Operation And Overflow/Underflow In Cascaded Operation
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.12 Contention between MTU2.TCNT Write Operation and Overflow/Underflow in Cascaded Operation With timer counters MTU1.TCNT and MTU2.TCNT in a cascade, when a contention occurs between MTU1.TCNT counting (an MTU2.TCNT overflow/underflow) and the MTU2.TCNT write cycle, the MTU2.TCNT write operation is performed and the MTU1.TCNT count signal is disabled.
Page 552: Counter Value When Count Operation Is Stopped In Complementary Pwm Mode
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.13 Counter Value When Count Operation is Stopped in Complementary PWM Mode When counting operation in MTU3.TCNT and MTU4.TCNT (MTU6.TCNT and MTU7.TCNT) is stopped in complementary PWM mode, the MTU3.TCNT (MTU6.TCNT) value is set to the timer dead time register (TDDRA (TDDRB)) value and MTU4.TCNT (MTU7.TCNT) is set to 0000h.
Page 553: Buffer Operation And Compare Match In Reset-Synchronized Pwm Mode
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.15 Buffer Operation and Compare Match in Reset-Synchronized PWM Mode When setting buffer operation in reset-synchronized PWM mode, set the BFA and BFB bits in MTU4.TMDR1 (MTU7.TMDR1) to 0. The MTIOC4C (MTIOC7C) pin cannot output waveforms if the BFA bit in MTU4.TMDR1 (MTU7.TMDR1) is set to 1.
Page 554: Overflow In Reset-Synchronized Pwm Mode
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.16 Overflow in Reset-Synchronized PWM Mode After reset-synchronized PWM mode is selected, MTU3.TCNT and MTU4.TCNT (MTU6.TCNT and MTU7.TCNT) start counting when the CST3 (CST6) bit of TSTRA (TSTRB) is set to 1. In this state, the MTU4.TCNT (MTU7.TCNT) count clock source and count edge are determined by the MTU3.TCR (MTU6.TCR) setting.
Page 555: Contention Between Overflow/Underflow And Counter Clearing
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.17 Contention between Overflow/Underflow and Counter Clearing If an overflow/underflow and counter clearing occur simultaneously, a TCIVn interrupt (n = 0 to 4, 6, 7, 9) nor a TCIUn interrupt (n = 1, 2) is not generated and TCNT clearing takes precedence. Figure 20.147 shows the operation timing when a TGR compare match is specified as the clearing source and TGR is set to FFFFh.
Page 556: Note On Transition From Normal Mode Or Pwm Mode 1 To Reset-Synchronized Pwm Mode
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.19 Note on Transition from Normal Mode or PWM Mode 1 to Reset-Synchronized PWM Mode When making a transition from normal mode or PWM mode 1 to reset-synchronized PWM mode in MTU3 and MTU4 (or MTU6 and MTU7), if the counter is stopped while the output pins (MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B, MTIOC4D, MTIOC6B, MTIOC6D, MTIOC7A, MTIOC7C, MTIOC7B, and MTIOC7D) are held at a high level and then operation is started after a transition to reset-synchronized PWM mode, the initial pin output will not be...
Page 557: Interrupt Skipping Function 2
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.22 Interrupt Skipping Function 2 When interrupt skipping function 2 is in use and the difference between the values in MTU4.TADCORA and MTU4.TADCORB is small, correct counting of the number skipped may not be possible, in which case requests for A/D conversion will not be generated with the expected timing.
Page 558: Notes To Prevent Malfunctions In Synchronous Clearing For Complementary Pwm Mode
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.25 Notes to Prevent Malfunctions in Synchronous Clearing for Complementary PWM Mode If control of the output waveform is enabled (TWCRA.WRE bit = 1 or TWCRB.WRE bit = 1) at the time of synchronous counter clearing in complementary PWM mode, satisfaction of either condition 1 or 2 below has the following effects.
Page 559 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Synchronous clearing MTU3.TGRA MTU3. TCNT Tb interval Tb interval MTU4. TCNT TDDR Positive phase output Negative phase output Although there is no period for output of the active level over this Dead time is interval, synchronous clearing leads to output of the active level .
Page 560: Continuous Output Of Interrupt Signal In Response To A Compare Match
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.6.26 Continuous Output of Interrupt Signal in Response to a Compare Match When the TGR register is set to 0000h, the PCLKA/1 clock is set as the count clock, and compare match is set as the trigger for clearing of the count clock, the value of the TCNT counter remains 0000h, and the interrupt signal will be output continuously (i.e.
Page 561 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Write 0 to MTU4.TADCOBRA MTU4.TCNT MTU4.TADCORA MTU4.TADCOBRA A/D converter start request (TRG4AN) Complementary PWM mode An A/D converter start request is not issued during up-counting UT4AE = 0 immediately after buffer transfer (trough). DT4AE = 1 BF[1:0] = 10b (transfer at trough) UT4AE, DT4AE, BF[1:0]: Bits in TADCR...
Page 562: Mtu Output Pin Initialization
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.7 MTU Output Pin Initialization 20.7.1 Operating Modes The MTU has the following six operating modes. Waveforms can be output in any of these modes.  Normal mode (MTU0 to MTU4, MTU6, MTU7, and MTU9) ...
Page 563: Overview Of Initialization Procedures And Mode Transitions In Case Of Error During Operation
RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) 20.7.3 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation  When making a transition to a mode (Normal, PWM1, PWM2, or PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of TIOR setting.
Page 564 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) Pin initialization procedures are described below for the numbered combinations in Table 20.81. The active level is assumed to be low. (1) Operation When Error Occurs in Normal Mode and Operation is Restarted in Normal Mode Figure 20.154 shows a case in which an error occurs in normal mode and operation is restarted in normal mode after re- setting.
Page 565 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (2) Operation When Error Occurs in Normal Mode and Operation is Restarted in PWM Mode 1 Figure 20.155 shows a case in which an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting.
Page 566 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (4) Operation When Error Occurs in Normal Mode and Operation is Restarted in Phase Counting Mode Figure 20.157 shows a case in which an error occurs in normal mode and operation is restarted in phase counting mode after re-setting.
Page 567 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (5) Operation When Error Occurs in Normal Mode and Operation is Restarted in Complementary PWM Mode Figure 20.158 shows a case in which an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
Page 568 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (6) Operation When Error Occurs in Normal Mode and Operation is Restarted in Reset- Synchronized PWM Mode Figure 20.159 shows a case in which an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 569 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (7) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Normal Mode Figure 20.160 shows a case in which an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
Page 570 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (8) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in PWM mode 1 Figure 20.161 shows a case in which an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
Page 571 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (10) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Phase Counting Mode Figure 20.163 shows a case in which an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting.
Page 572 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (11) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Complementary PWM Mode Figure 20.164 shows a case in which an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
Page 573 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (12) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Reset- Synchronized PWM Mode Figure 20.165 shows a case in which an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 574 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (13) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in Normal Mode Figure 20.166 shows a case in which an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
Page 575 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (14) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in PWM Mode 1 Figure 20.167 shows a case in which an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
Page 576 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (15) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in PWM Mode 2 Figure 20.168 shows a case in which an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting.
Page 577 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (17) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in Normal Mode Figure 20.170 shows a case in which an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
Page 578 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (18) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 1 Figure 20.171 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
Page 579 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (19) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 2 Figure 20.172 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
Page 580 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (21) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Normal Mode Figure 20.174 shows a case in which an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
Page 581 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (22) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in PWM Mode 1 Figure 20.175 shows a case in which an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 582 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (23) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Complementary PWM Mode Figure 20.176 shows a case in which an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time of stopping the counter).
Page 583 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (24) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Complementary PWM Mode with New Settings Figure 20.177 shows a case in which an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (operation is restarted using new cycle and duty ratio settings).
Page 584 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (25) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Reset-Synchronized PWM Mode Figure 20.178 shows a case in which an error occurs in complementary PWM mode and operation is restarted in reset- synchronized PWM mode after re-setting.
Page 585 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (26) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Normal Mode Figure 20.179 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in normal mode after re-setting.
Page 586 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (27) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in PWM Mode 1 Figure 20.180 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 587 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (28) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Complementary PWM Mode Figure 20.181 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in complementary PWM mode after re-setting.
Page 588 RX24T Group 20. Multi-Function Timer Pulse Unit (MTU3d) (29) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Reset-Synchronized PWM Mode Figure 20.182 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 589: Port Output Enable 3 (Poe3B)
RX24T Group 21. Port Output Enable 3 (POE3b) Port Output Enable 3 (POE3b) The port output enable 3 (POE3b) register can be used to place output pins for the MTU in the high-impedance state under various conditions. In this section, “PCLK” is used to refer to PCLKB. 21.1 Overview Table 21.1 lists the specifications of the POE, and Figure 21.1 shows a block diagram of the POE.
Page 590 RX24T Group 21. Port Output Enable 3 (POE3b) POECR1 to POECR8 MTIOC3B Output-level Input signals for use in MTIOC3D comparison circuit control of complementary MTIOC4A Output-level PWM output from the MTU MTIOC4C comparison circuit pins (MTU3 and MTU4) MTIOC4B Output-level comparison circuit MTIOC4D High-impedance request signal or...
Page 591 RX24T Group 21. Port Output Enable 3 (POE3b) Table 21.2 shows I/O pins to be used by the POE. Table 21.2 POE I/O Pins Pin Name Description POE0# Input Request signal to place the MTU3 and MTU4 pins for MTU complementary PWM output in high- impedance state, and in accordance with register settings, is also capable of placing the MTU0, MTU6, MTU7, and MTU9 pins in the high-impedance state.
Page 592: Register Descriptions
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2 Register Descriptions The POE registers are initialized by a reset. 21.2.1 Input Level Control/Status Register 1 (ICSR1) Address(es): 0008 C4C0h — — — POE0F — — — PIE1 — — — —...
Page 593: Input Level Control/Status Register 2 (Icsr2)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.2 Input Level Control/Status Register 2 (ICSR2) Address(es): 0008 C4C4h — — — POE4F — — — PIE2 — — — — — — POE4M[1:0] Value after reset: Symbol Bit Name Description b1, b0 POE4M[1:0] POE4 Mode Select...
Page 594: Input Level Control/Status Register 3 (Icsr3)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.3 Input Level Control/Status Register 3 (ICSR3) Address(es): 0008 C4C8h — — — POE8F — — POE8E PIE3 — — — — — — POE8M[1:0] Value after reset: Symbol Bit Name Description b1, b0 POE8M[1:0] POE8 Mode Select...
Page 595: Input Level Control/Status Register 4 (Icsr4)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.4 Input Level Control/Status Register 4 (ICSR4) Address(es): 0008 C4D6h POE10 POE10 — — — — — PIE4 — — — — — — POE10M[1:0] Value after reset: Symbol Bit Name Description b1, b0 POE10M[1:0] POE10 Mode Select...
Page 596: Input Level Control/Status Register 5 (Icsr5)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.5 Input Level Control/Status Register 5 (ICSR5) Address(es): 0008 C4D8h POE11 POE11 — — — — — PIE5 — — — — — — POE11M[1:0] Value after reset: Symbol Bit Name Description b1, b0 POE11M[1:0] POE11 Mode Select...
Page 597: Input Level Control/Status Register 6 (Icsr6)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.6 Input Level Control/Status Register 6 (ICSR6) Address(es): 0008 C4DCh OSTST OSTST — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b8 to b0 —...
Page 598: Input Level Control/Status Register 7 (Icsr7)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.7 Input Level Control/Status Register 7 (ICSR7) Address(es): 0008 C4E0h POE12 POE12 — — — — — PIE7 — — — — — — POE12M[1:0] Value after reset: Symbol Bit Name Description b1, b0 POE12M[1:0] POE12 Mode Select...
Page 599: Output Level Control/Status Register 1 (Ocsr1)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.8 Output Level Control/Status Register 1 (OCSR1) Address(es): 0008 C4C2h OSF1 — — — — — OCE1 OIE1 — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 600: Output Level Control/Status Register 2 (Ocsr2)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.9 Output Level Control/Status Register 2 (OCSR2) Address(es): 0008 C4C6h OSF2 — — — — — OCE2 OIE2 — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 601: Active Level Setting Register 1 (Alr1)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.10 Active Level Setting Register 1 (ALR1) Address(es): 0008 C4DAh OLSG2 OLSG2 OLSG1 OLSG1 OLSG0 OLSG0 — — — — — — — — OLSEN — Value after reset: Symbol Bit Name Description OLSG0A MTIOC3B Active Level Setting...
Page 602 RX24T Group 21. Port Output Enable 3 (POE3b) OLSG2B Bit (MTIOC4D Active Level Setting) This bit sets the active level of the MTIOC4D output. Specifically, setting the OLSG2B bit to 0 sets the low level and to 1 sets the high level as the active level for detection of short circuits. OLSEN Bit (Active Level Setting Enable) This bit enables or disables of the active-level settings in the OLSGnm bits (n = 0 to 2;...
Page 603: Active Level Setting Register 2 (Alr2)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.11 Active Level Setting Register 2 (ALR2) Address(es): 0008 C4DEh OLSG6 OLSG6 OLSG5 OLSG5 OLSG4 OLSG4 — — — — — — — — OLSEN — Value after reset: Symbol Bit Name Description OLSG4A MTIOC6B Active Level Setting...
Page 604 RX24T Group 21. Port Output Enable 3 (POE3b) OLSG6B Bit (MTIOC7D Active Level Setting) This bit sets the active level of the MTIOC7D output. Specifically, setting the OLSG6B bit to 0 sets the low level and to 1 sets the high level as the active level for detection of short circuits. OLSEN Bit (Active Level Setting Enable) This bit enables or disables the active-level settings in the OLSGnm bits (n = 4 to 6;...
Page 605: Software Port Output Enable Register (Spoer)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.12 Software Port Output Enable Register (SPOER) Address(es): 0008 C4CAh MTUC MTUC MTUC MTUC — — — — H0HIZ H67HIZ H34HIZ H9HIZ Value after reset: Symbol Bit Name Description MTUCH34HIZ MTU3 and MTU4 Output High- 0: Does not place the pins in high-impedance state.
Page 606 RX24T Group 21. Port Output Enable 3 (POE3b) MTUCH9HIZ Bit (MTU9 Output High-Impedance Enable) This bit specifies whether to place the MTU9 pins in high-impedance state. [Setting condition]  By writing 1 to MTUCH9HIZ [Clearing conditions]  Reset  By writing 0 to MTUCH9HIZ after reading MTUCH9HIZ = 1 R01UH0576EJ0100 Rev.1.00 Page 606 of 1230 Nov 30, 2015...
Page 607: Port Output Enable Control Register 1 (Poecr1)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.13 Port Output Enable Control Register 1 (POECR1) Address(es): 0008 C4CBh MTU0B MTU0A MTU0D MTU0C MTU0B MTU0A — — Value after reset: Symbol Bit Name Description MTU0AZE MTIOC0A PB3 Pin High-Impedance 0: Does not place the pin in high-impedance state. R/W* Enable 1: Places the pin in high-impedance state.
Page 608: Port Output Enable Control Register 2 (Poecr2)
RX24T Group 21. Port Output Enable 3 (POE3b) MTU0A1ZE Bit (MTIOC0A P31 Pin High-Impedance Enable) This bit specifies whether to place the MTIOC0A output of P31 in high-impedance state when any of the ICSR3.POE8F flag, SPOER.MTUCH0HIZ bit, and ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally specified in POECR5, the ICSRn.POEmF flag (n = 1, 2, 4, 5, 7;...
Page 609 RX24T Group 21. Port Output Enable 3 (POE3b) the OCSR2.OSF2 flag, ICSR2.POE4F flag, SPOER.MTUCH67HIZ bit, ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally specified in the POECR4 register, the ICSRn.POEmF flag (n = 1, 3 to 5, 7; m = 0, 8, 10, 11, 12), or POECMPFR.CnFLAG (n = 0 to 3) flag is set to 1.
Page 610: Port Output Enable Control Register 4 (Poecr4)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.15 Port Output Enable Control Register 4 (POECR4) Address(es): 0008 C4D0h IC5ADD IC4ADD IC3ADD IC1ADD CMADD IC5ADD IC4ADD IC3ADD IC2ADD CMADD IC6ADD IC6ADD — — — — MT67ZE MT67ZE MT67ZE MT67ZE MT67ZE MT67ZE MT34ZE MT34ZE...
Page 611 RX24T Group 21. Port Output Enable 3 (POE3b) CMADDMT34ZE Bit (MTU3 and MTU4 High-Impedance CFLAG Add) Adds the POECMPFR.CnFLAG flag (n = 0 to 3) to the high-impedance control conditions for the MTU3 and MTU4 pins (MTIOC3B/MTIOC3D/MTIOC4A/MTIOC4C/MTIOC4B/MTIOC4D). However, when this flag is placed in the high-impedance, the OEIn interrupt (n = 1 to 5) will not occur. IC2ADDMT34ZE Bit (MTU3 and MTU4 High-Impedance POE4F Add) Adds the ICSR2.POE4F flag to the high-impedance control conditions for the MTU3 and MTU4 pins (MTIOC3B/ MTIOC3D/MTIOC4A/MTIOC4C/MTIOC4B/MTIOC4D).
Page 612 RX24T Group 21. Port Output Enable 3 (POE3b) MTIOC6D/MTIOC7A/MTIOC7C/MTIOC7B/MTIOC7D). R01UH0576EJ0100 Rev.1.00 Page 612 of 1230 Nov 30, 2015...
Page 613: Port Output Enable Control Register 5 (Poecr5)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.16 Port Output Enable Control Register 5 (POECR5) Address(es): 0008 C4D2h IC4ADD IC6ADD IC5ADD IC2ADD IC1ADD CMADD — — — — — — — — — — MT0ZE MT0ZE MT0ZE MT0ZE MT0ZE MT0ZE Value after reset: Symbol...
Page 614 RX24T Group 21. Port Output Enable 3 (POE3b) IC5ADDMT0ZE Bit (MTU0 High-Impedance POE11F Add) Adds the ICSR5.POE11F flag to the high-impedance control conditions for the MTU0 pin (MTIOC0A, MTIOC0B, MTIOC0C, MTIOC0D). IC6ADDMT0ZE Bit (MTU0 High-Impedance POE12F Add) Adds the ICSR7.POE12F flag to the high-impedance control conditions for the MTU0 pin (MTIOC0A, MTIOC0B, MTIOC0C, MTIOC0D).
Page 615: Port Output Enable Control Register 7 (Poecr7)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.17 Port Output Enable Control Register 7 (POECR7) Address(es): 0008 C4E2h MTU9D MTU9C MTU9B MTU9A MTU9D MTU9C MTU9B MTU9A — — — — — — — — Value after reset: Symbol Bit Name Description MTU9AZE MTIOC9A PD7 Pin High-Impedance...
Page 616 RX24T Group 21. Port Output Enable 3 (POE3b) the ICSR7.POE12F flag, SPOER.MTUCH9HIZ bit, and ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally specified in POECR8, the ICSRn.POEmF flag (n = 1 to 5; m = 0, 4, 8, 10, 11), or POECMPFR.CnFLAG (n = 0 to 3) flag, is set to 1.
Page 617: Port Output Enable Control Register 8 (Poecr8)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.18 Port Output Enable Control Register 8 (POECR8) Address(es): 0008 C4E4h IC5ADD IC4ADD IC3ADD IC2ADD IC1ADD CMADD — — — — — — — — — — MT9ZE MT9ZE MT9ZE MT9ZE MT9ZE MT9ZE Value after reset: Symbol...
Page 618 RX24T Group 21. Port Output Enable 3 (POE3b) IC4ADDMT9ZE Bit (MTU9 High-Impedance POE10F Add) Adds the ICSR4.POE10F flag to the high-impedance control conditions for the MTU9 pin (MTIOC9A, MTIOC9B, MTIOC9C, MTIOC9D). IC5ADDMT9ZE Bit (MTU9 High-Impedance POE11F Add) Adds the ICSR5.POE11F flag to the high-impedance control conditions for the MTU9 pin (MTIOC9A, MTIOC9B, MTIOC9C, MTIOC9D).
Page 619: Port Output Enable Comparator Detection Flag Register (Poecmpfr)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.19 Port Output Enable Comparator Detection Flag Register (POECMPFR) Address(es): 0008 C4E6h C3FLA C2FLA C1FLA C0FLA — — — — — — — — — — — — Value after reset: Symbol Bit Name Description C0FLAG...
Page 620: Port Output Enable Comparator Request Select Register (Poecmpsel)
RX24T Group 21. Port Output Enable 3 (POE3b) 21.2.20 Port Output Enable Comparator Request Select Register (POECMPSEL) Address(es): 0008 C4E8h POERE POERE POERE POERE — — — — — — — — — — — — Value after reset: Symbol Bit Name Description POEREQ0...
Page 621: Operation
RX24T Group 21. Port Output Enable 3 (POE3b) 21.3 Operation The following shows the target pins and conditions for high-impedance control. (1) MTU3 pins (MTIOC3B, MTIOC3D) When one of the following conditions is satisfied while the POECR2.MTU3BDZE bit is 1, the pins become high- impedance.
Page 622 RX24T Group 21. Port Output Enable 3 (POE3b) When the ICSR7.POE12F flag becomes 1 while the POECR4.IC6ADDMT34ZE bit and the ICSR7.POE12E bit are  Comparator detection When the POECMPFR.C0FLAG flag becomes 1 while the POECR4.CMADDMT34ZE bit and the POECMPSEL.POEREQ0 bit are 1. When the POECMPFR.C1FLAG flag becomes 1 while the POECR4.CMADDMT34ZE bit and the POECMPSEL.POEREQ1 bit are 1.
Page 623 RX24T Group 21. Port Output Enable 3 (POE3b)  Operation for detection of the POE4# input level When the ICSR2.POE4F flag becomes 1.  Operation for comparison of the output levels on the MTIOC6B and MTIOC6D pins When the OCSR2.OCF2 flag becomes 1 while the OCSR2.OCE2 bit is 1. ...
Page 624 RX24T Group 21. Port Output Enable 3 (POE3b) When the POECMPFR.C1FLAG flag becomes 1 while the POECR4.CMADDMT67ZE bit and the POECMPSEL.POEREQ1 bit are 1. When the POECMPFR.C2FLAG flag becomes 1 while the POECR4.CMADDMT67ZE bit and the POECMPSEL.POEREQ2 bit are 1. When the POECMPFR.C3FLAG flag becomes 1 while the POECR4.CMADDMT67ZE bit and the POECMPSEL.POEREQ3 bit are 1.
Page 625 RX24T Group 21. Port Output Enable 3 (POE3b) When the ICSR2.POE4F flag becomes 1 while the POECR5.IC1ADDMT0ZE bit is 1. When the ICSR4.POE10F flag becomes 1 while the POECR5.IC4ADDMT0ZE bit and the ICSR4.POE10E bit are When the ICSR5.POE11F flag becomes 1 while the POECR5.IC5ADDMT0ZE bit and the ICSR5.POE11E bit are When the ICSR7.POE12F flag becomes 1 while the POECR5.IC6ADDMT0ZE bit and the ICSR7.POE12E bit are ...
Page 626 RX24T Group 21. Port Output Enable 3 (POE3b) impedance.  Operation for detection of the POE8# input level When the ICSR3.POE8F flag becomes 1 while the ICSR3.POE8E bit is 1.  SPOER setting When the SPOER.MTUCH0HIZ bit is set to 1. ...
Page 627 RX24T Group 21. Port Output Enable 3 (POE3b) POECMPSEL.POEREQ2 bit are 1. When the POECMPFR.C3FLAG flag becomes 1 while the POECR5.CMADDMT0ZE bit and the POECMPSEL.POEREQ3 bit are 1.  Detection of oscillation stop When the ICSR6.OSTSTF flag becomes 1 while the ICSR6.OSTSTE bit is 1. (11) MTU0 pin PB1 (MTIOC0C) When one of the following conditions is satisfied while the POECR1.MTU0CZE bit is 1, the pins become high- impedance.
Page 628 RX24T Group 21. Port Output Enable 3 (POE3b) When the ICSR7.POE12F flag becomes 1 while the POECR5.IC6ADDMT0ZE bit and the ICSR7.POE12E bit are  Comparator detection When the POECMPFR.C0FLAG flag becomes 1 while the POECR5.CMADDMT0ZE bit and the POECMPSEL.POEREQ0 bit are 1. When the POECMPFR.C1FLAG flag becomes 1 while the POECR5.CMADDMT0ZE bit and the POECMPSEL.POEREQ1 bit are 1.
Page 629 RX24T Group 21. Port Output Enable 3 (POE3b)  Conditions added by POECR8 When the ICSR1.POE0F flag becomes 1 while the POECR8.IC1ADDMT9ZE bit is 1. When the ICSR2.POE4F flag becomes 1 while the POECR8.IC2ADDMT9ZE bit is 1. When the ICSR3.POE8F flag becomes 1 while the POECR8.IC3ADDMT9ZE bit and the ICSR3.POE8E bit are 1. When the ICSR4.POE10F flag becomes 1 while the POECR8.IC4ADDMT9ZE bit and the ICSR4.POE10E bit are When the ICSR5.POE11F flag becomes 1 while the POECR8.IC5ADDMT9ZE bit and the ICSR5.POE11E bit are ...
Page 630 RX24T Group 21. Port Output Enable 3 (POE3b) impedance state.  Operation for detection of the POE12# input level When the ICSR7.POE12F flag becomes 1 while the ICSR7.POE12E bit is 1.  SPOER setting When the SPOER.MTUCH9HIZ bit is set to 1. ...
Page 631 RX24T Group 21. Port Output Enable 3 (POE3b) POECMPSEL.POEREQ3 bit are 1.  Detection of oscillation stop When the ICSR6.OSTSTF flag becomes 1 while the ICSR6.OSTSTE bit is 1. (18) MTU9 pin P20 (MTIOC9C) When one of the following conditions is satisfied while the POECR7.MTU9C1ZE bit is 1, the pins are placed in high- impedance state.
Page 632 RX24T Group 21. Port Output Enable 3 (POE3b) When the ICSR6.OSTSTF flag becomes 1 while the ICSR6.OSTSTE bit is 1. (20) MTU9 pin P02 (MTIOC9D) When one of the following conditions is satisfied while the POECR7.MTU9D1ZE bit is 1, the pins are placed in high- impedance state.
Page 633 RX24T Group 21. Port Output Enable 3 (POE3b) OCSR1.OSF1 OCSR1.OCE1 ICSR1 POE0# POE0F POECR2 POECR4.IC2ADDMT34ZE MTU3BDZE Hi-Z request signal for MTIOC3B/MTIOC3D pin POECR4.IC3ADDMT34ZE MTU4ACZE Hi-Z request signal for POECR4.IC4ADDMT34ZE MTIOC4A/MTIOC4C pin POECR4.IC5ADDMT34ZE MTU4BDZE Hi-Z request signal for POECR4.IC6ADDMT34ZE MTIOC4B/MTIOC4D pin POECR4.CMADDMT34ZE SPOER.MTUCH34HIZ OCSR2.OSF2...
Page 634: Input-Level Detection Operation
RX24T Group 21. Port Output Enable 3 (POE3b) 21.3.1 Input-Level Detection Operation If the input conditions set by ICSR1 to ICSR5 and ICSR7 occur on the POE0#, POE4#, POE8#, POE10#, POE11#, and POE12# pins, the MTU3 and MTU4 or MTU6 and MTU7 pins for the MTU complementary PWM output, MTU0 pins, and MTU9 pins are placed in high-impedance state.
Page 635: Output-Level Compare Operation
RX24T Group 21. Port Output Enable 3 (POE3b) (2) Low-Level Detection Figure 21.4 shows the low-level detection operation. When 16 continuous low levels are sampled with the sampling clock selected by the ICSR1 to ICSR5 and ICSR7 registers, the low level is recognized and the MTU complementary PWM output pins, MTU0 pins, and MTU9 pins are placed in high-impedance state.
Page 636: High-Impedance Control Using Registers
RX24T Group 21. Port Output Enable 3 (POE3b) 21.3.3 High-Impedance Control Using Registers The high-impedance state of the MTU pins (MTU0, MTU3, MTU4, MTU6, MTU7, and MTU9) can be directly controlled by using the SPOER register. For instance, setting the SPOER.MTUCH34HIZ bit to 1 places the MTU3 and MTU4 pins specified by the POECR2 register in the high-impedance state.
Page 637 RX24T Group 21. Port Output Enable 3 (POE3b) However, note that just writing 0 to a flag is ignored (the flag is not set to 0); the flags can be cleared by writing 0 to it only after setting the inactive level to be output from the pin. The inactive level is output by setting the MTU, ALR1, and ALR2 registers.
Page 638: Poe Setting Procedure
RX24T Group 21. Port Output Enable 3 (POE3b) 21.4 POE Setting Procedure Figure 21.6 shows the procedure for setting the POE. It illustrates an example of high-impedance control in response to comparison of the output levels on the MTU3 pins (MTIOC3B/MTIOC3D). In the figure, P71 is used as the MTIOC3B pin and P74 is used as the MTIOC3D pin.
Page 639: Usage Notes
RX24T Group 21. Port Output Enable 3 (POE3b) 21.6 Usage Notes 21.6.1 Transition to Low Power Consumption Mode When the POE is used, do not make a transition to software standby mode. In this mode, the POE stops and thus the high-impedance state of pins cannot be controlled.
Page 640: Bit Timer (Tmr)
RX24T Group 22. 8-Bit Timer (TMR) 8-Bit Timer (TMR) This MCU has four units (unit 0, unit 1, unit 2, unit 3) of an on-chip 8-bit timer (TMR) module that comprise two 8-bit counter channels, totaling eight channels. The 8-bit timer module can be used to count external events and also be used as a multi-function timer in a variety of applications, such as generation of counter reset signal, interrupt requests, and pulse output with a desired duty cycle using a compare-match signal with two registers.
Page 641 RX24T Group 22. 8-Bit Timer (TMR) Table 22.2 TMR Functions (1/2) Item Unit 0 Unit 1 Counter mode 8 Bits 16 Bits 8 Bits 16 Bits Channel TMR0 TMR1 TMR0 + TMR1 TMR2 TMR3 TMR2 + TMR3 Count clock PCLK/1 PCLK/1 PCLK/1 PCLK/1...
Page 642 RX24T Group 22. 8-Bit Timer (TMR) Table 22.3 TMR Functions (2/2) Item Unit 2 Unit 3 Counter mode 8 Bits 16 Bits 8 Bits 16 Bits Channel TMR4 TMR5 TMR4 + TMR5 TMR6 TMR7 TMR6 + TMR7 Count clock PCLK/1 PCLK/1 PCLK/1 PCLK/1...
Page 643 RX24T Group 22. 8-Bit Timer (TMR) Internal clock PCLK PCLK/2 PCLK/8 PCLK/32 PCLK/64 PCLK/1024 PCLK/8192 Count clock 1 Count clock 0 TMCI0 Clock select TMCI1 TCORA TCORA Compare match A1 Compare match A0 Comparator A0 Comparator A1 To SCI Overflow 1 Overflow 0 TMO0 TCNT...
Page 644 RX24T Group 22. 8-Bit Timer (TMR) Internal clock PCLK PCLK/2 PCLK/8 PCLK/32 PCLK/64 PCLK/1024 PCLK/8192 Count clock 3 Count clock 2 TMCI2 Clock select TMCI3 TCORA TCORA Compare match A3 Comparator A2 Comparator A3 Compare match A2 To SCI Overflow 3 TCNT TCNT TMO2...
Page 645 RX24T Group 22. 8-Bit Timer (TMR) Internal clock PCLK PCLK/2 PCLK/8 PCLK/32 PCLK/64 PCLK/1024 PCLK/8192 Count clock 5 Count clock 4 TMCI4 Clock select TMCI5 TCORA TCORA Compare match A5 Compare match A4 Comparator A4 Comparator A5 Overflow 5 Overflow 4 TMO4 TCNT TCNT...
Page 646 RX24T Group 22. 8-Bit Timer (TMR) Internal clock PCLK PCLK/2 PCLK/8 PCLK/32 PCLK/64 PCLK/1024 PCLK/8192 Count clock 7 Count clock 6 TMCI6 Clock select TMCI7 TCORA TCORA Compare match A7 Comparator A6 Comparator A7 Compare match A6 Overflow 7 TCNT TCNT TMO6 Overflow 6...
Page 647 RX24T Group 22. 8-Bit Timer (TMR) Table 22.4 lists the I/O pins of the TMR. Table 22.4 Pin Configuration of TMR Unit Channel Pin Name Description TMR0 TMO0 Output Outputs compare match TMCI0 Input Inputs external count clock TMRI0 Input Inputs external counter reset TMR1 TMO1...
Page 648: Register Descriptions
RX24T Group 22. 8-Bit Timer (TMR) 22.2 Register Descriptions Table 22.5 Register Allocation for 16-Bit Access Address Upper 8 Bits Lower 8 Bits 0008 8208h TMR0.TCNT TMR1.TCNT 0008 8204h TMR0.TCORA TMR1.TCORA 0008 8206h TMR0.TCORB TMR1.TCORB 0008 820Ah TMR0.TCCR TMR1.TCCR 0008 8218h TMR2.TCNT TMR3.TCNT 0008 8214h...
Page 649: Time Constant Register A (Tcora)
RX24T Group 22. 8-Bit Timer (TMR) 22.2.2 Time Constant Register A (TCORA) Address(es): TMR0.TCORA 0008 8204h, TMR1.TCORA 0008 8205h, TMR2.TCORA 0008 8214h, TMR3.TCORA 0008 8215h, TMR4.TCORA 0008 8224h, TMR5.TCORA 0008 8225h, TMR6.TCORA 0008 8234h, TMR7.TCORA 0008 8235h TMR0.TCORA(TMR2.TCORA, TMR1.TCORA(TMR3.TCORA, TMR4.TCORA, TMR6.TCORA) TMR5.TCORA, TMR7.TCORA) Value after reset: TCORA is an 8-bit readable/writable register.
Page 650: Timer Control Register (Tcr)
RX24T Group 22. 8-Bit Timer (TMR) 22.2.4 Timer Control Register (TCR) Address(es): TMR0.TCR 0008 8200h, TMR1.TCR 0008 8201h, TMR2.TCR 0008 8210h, TMR3.TCR 0008 8211h, TMR4.TCR 0008 8220h, TMR5.TCR 0008 8221h, TMR6.TCR 0008 8230h, TMR7.TCR 0008 8231h CMIEB CMIEA OVIE CCLR[1:0] —...
Page 651: Timer Counter Control Register (Tccr)
RX24T Group 22. 8-Bit Timer (TMR) 22.2.5 Timer Counter Control Register (TCCR) Address(es): TMR0.TCCR 0008 820Ah, TMR1.TCCR 0008 820Bh, TMR2.TCCR 0008 821Ah, TMR3.TCCR 0008 821Bh, TMR4.TCCR 0008 822Ah, TMR5.TCCR 0008 822Bh, TMR6.TCCR 0008 823Ah, TMR7.TCCR 0008 823Bh TMRIS — — CSS[1:0] CKS[2:0] Value after reset:...
Page 652 RX24T Group 22. 8-Bit Timer (TMR) Table 22.6 Clock Input to TCNT and Count Condition TCCR Register CSS[1:0] CKS[2:0] Channel Description TMR0 — Clock input prohibited (TMR2, TMR4, Uses external count clock. Counts at rising edge* TMR6) Uses external count clock. Counts at falling edge* Uses external count clock.
Page 653: Timer Control/Status Register (Tcsr)
RX24T Group 22. 8-Bit Timer (TMR) 22.2.6 Timer Control/Status Register (TCSR)  TMR0.TCSR, TMR2.TCSR, TMR4.TCSR, TMR6.TCSR Address(es): TMR0.TCSR 0008 8202h, TMR2.TCSR 0008 8212h, TMR4.TCSR 0008 8222h, TMR6.TCSR 0008 8232h — — — ADTE OSB[1:0] OSA[1:0] Value after reset: x: Undefined Symbol Bit Name Description...
Page 654 RX24T Group 22. 8-Bit Timer (TMR)  TMR1.TCSR, TMR3.TCSR, TMR5.TCSR, TMR7.TCSR Address(es): TMR1.TCSR 0008 8203h, TMR3.TCSR 0008 8213h, TMR5.TCSR 0008 8223h, TMR7.TCSR 0008 8233h — — — — OSB[1:0] OSA[1:0] Value after reset: x: Undefined Symbol Bit Name Description b1, b0 OSA[1:0] Output Select A* b1 b0...
Page 655: Operation
RX24T Group 22. 8-Bit Timer (TMR) 22.3 Operation 22.3.1 Pulse Output Figure 22.5 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. 1. Set the TCR.CCLR[1:0] bits to 01b (cleared by compare match A) so that TCNT is cleared at a compare match of TCORA.
Page 656: External Counter Reset Input
RX24T Group 22. 8-Bit Timer (TMR) 22.3.2 External Counter Reset Input Figure 22.6 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time from a TMRIn input. 1. Set the TCR.CCLR[1:0] bits to 11b (cleared by external counter reset signal) and set the TMRIS bit in TCCR to 1 (cleared when the external counter reset signal is high) so that TCNT is cleared at the high level input of the TMRIn signal.
Page 657: Operation Timing
RX24T Group 22. 8-Bit Timer (TMR) 22.4 Operation Timing 22.4.1 TCNT Count Timing Figure 22.7 shows the count timing of TCNT for internal clock. Figure 22.8 shows the count timing of TCNT for external clock. Note that the external clock pulse width must be at least 1.5 PCLK cycles for increment at a single edge, and at least 2.5 PCLK cycles for increment at both edges.
Page 658: Timing Of Interrupt Signal Output On A Compare Match
RX24T Group 22. 8-Bit Timer (TMR) 22.4.2 Timing of Interrupt Signal Output on a Compare Match A compare match refers to a match between the value of the TCORA or TCORB register and the TCNT, and a compare match interrupt signal is output at this time if the interrupt request is enabled. The compare match is generated in the last cycle in which the values match (at the time at which the value counted by TCNT to produce the match is updated).
Page 659: Timing Of Counter Clear By Compare Match
RX24T Group 22. 8-Bit Timer (TMR) 22.4.4 Timing of Counter Clear by Compare Match TCNT is cleared when compare match A or B occurs, depending on the settings of the TCR.CCLR[1:0] bits. Figure 22.11 shows the timing of this operation. PCLK Compare match signal TCNT...
Page 660: Timing Of Interrupt Signal Output On An Overflow
RX24T Group 22. 8-Bit Timer (TMR) 22.4.6 Timing of Interrupt Signal Output on an Overflow When TCNT overflows (changes from FFh to 00h), an overflow interrupt signal is output if this interrupt request is enabled. Figure 22.14 shows the timing of output of the interrupt signal. For the corresponding interrupt vector number, see section 14, Interrupt Controller (ICUb) and Table 22.7.
Page 661: Operation With Cascaded Connection
RX24T Group 22. 8-Bit Timer (TMR) 22.5 Operation with Cascaded Connection If the CSS[1:0] bits in either TMR0.TCCR or TMR1.TCCR are set to 11b, the TMR of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of TMR0 could be counted by TMR1 (compare match count mode).
Page 662: Interrupt Sources
RX24T Group 22. 8-Bit Timer (TMR) 22.6 Interrupt Sources 22.6.1 Interrupt Sources and DTC Activation There are three interrupt sources for TMRn: CMIAn, CMIBn, and OVIn. Their interrupt sources and priorities are listed in Table 22.7. It is also possible to activate the DTC by means of CMIAn and CMIBn interrupts. Table 22.7 TMR Interrupt Sources Name...
Page 663: Startup Of The A/D Converter
RX24T Group 22. 8-Bit Timer (TMR) 22.6.2 Startup of the A/D Converter The compare match A of TMR0, TMR2, TMR4, and TMR6 allows the A/D converter* to be started. An A/D conversion start request is issued to the A/D converter in response to a generation of compare match A when the TMRn.TCSR.ADTE bit is 1 (i.e., when an A/D conversion request in response to compare match A is enabled).
Page 664: Usage Notes
RX24T Group 22. 8-Bit Timer (TMR) 22.7 Usage Notes 22.7.1 Module Stop State Setting Operation of the TMR can be disabled or enabled by using the module stop control registers. The initial setting is for halting of TMR operation. Register access becomes possible after release from the module stop state. For details, see section 11, Low Power Consumption.
Page 665: Conflict Between Tcnt Write And Increment
RX24T Group 22. 8-Bit Timer (TMR) 22.7.4 Conflict between TCNT Write and Increment Even if a counting-up signal is generated concurrently with CPU write to TCNT, the counting-up is not performed and the write takes priority as shown in Figure 22.16. TCNT write by CPU PCLK TCNT count clock...
Page 666: Conflict Between Compare Matches A And B
RX24T Group 22. 8-Bit Timer (TMR) 22.7.6 Conflict between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output methods high for compare match A and compare match B, as listed in Table 22.9. Table 22.9 Timer Output Priorities Output Setting...
Page 667 RX24T Group 22. 8-Bit Timer (TMR) Table 22.10 Switching of Internal Clocks and TCNT Operation (2/2) Timing to Change the TCCR.CKS[2:0] Bits TCNT Counter Operation Switching from low to high* Clock before switching Clock after switching TCNT count clock TCNT TCCR.CKS[2:0] bits changed Switching from high to low* Clock before...
Page 668: Clock Source Setting With Cascaded Connection
RX24T Group 22. 8-Bit Timer (TMR) 22.7.8 Clock Source Setting with Cascaded Connection If 16-bit counter mode and compare match count mode are specified at the same time, count clocks for TMR0.TCNT and TMR1.TCNT (TMR2.TCNT and TMR3.TCNT, TMR4.TCNT and TMR5.TCNT, TMR6.TCNT and TMR7.TCNT) are not generated, and the counter stops.
Page 669: Compare Match Timer (Cmt)
RX24T Group 23. Compare Match Timer (CMT) Compare Match Timer (CMT) This MCU has two on-chip compare match timer (CMT) units (unit 0 and unit 1), each consisting of a two-channel 16-bit timer (i.e., a total of four channels). The CMT has a 16-bit counter, and can generate interrupts at set intervals. In this section, “PCLK”...
Page 670: Register Descriptions
RX24T Group 23. Compare Match Timer (CMT) 23.2 Register Descriptions 23.2.1 Compare Match Timer Start Register 0 (CMSTR0) Address(es): 0008 8000h — — — — — — — — — — — — — — STR1 STR0 Value after reset: Symbol Bit Name Description...
Page 671: Compare Match Timer Control Register (Cmcr)
RX24T Group 23. Compare Match Timer (CMT) 23.2.3 Compare Match Timer Control Register (CMCR) Address(es): CMT0.CMCR 0008 8002h, CMT1.CMCR 0008 8008h, CMT2.CMCR 0008 8012h, CMT3.CMCR 0008 8018h — — — — — — — — — CMIE — — — —...
Page 672: Compare Match Counter (Cmcnt)
RX24T Group 23. Compare Match Timer (CMT) 23.2.4 Compare Match Counter (CMCNT) Address(es): CMT0.CMCNT 0008 8004h, CMT1.CMCNT 0008 800Ah, CMT2.CMCNT 0008 8014h, CMT3.CMCNT 0008 801Ah Value after reset: The CMCNT counter is a readable/writable up-counter. When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTRm.STRn (m = 0, 1; n = 0 to 3) bit is set to 1, the CMCNT counter starts counting up using the selected clock.
Page 673: Operation
RX24T Group 23. Compare Match Timer (CMT) 23.3 Operation 23.3.1 Periodic Count Operation When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTRm.STRn (m = 0, 1; n = 0 to 3) bit is set to 1, the CMCNT counter starts counting up using the selected clock. When the value in the counter and the value in the register match, a compare match interrupt (CMIn) (n = 0 to 3) is generated.
Page 674: Interrupts
RX24T Group 23. Compare Match Timer (CMT) 23.4 Interrupts 23.4.1 Interrupt Sources The CMT has channels and each of them to which a different vector address is allocated has a compare match interrupt (CMIn) (n = 0 to 3). When a compare match interrupt occurs, the corresponding interrupt request is output. When the interrupt request is used to generate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings.
Page 675: Usage Notes
RX24T Group 23. Compare Match Timer (CMT) 23.5 Usage Notes 23.5.1 Setting the Module Stop Function The CMT can be enabled or disabled using the module stop control register. After a reset, the CMT is in the module stop state. The registers can be accessed by releasing the module stop state. For details, refer to section 11, Low Power Consumption.
Page 676: Independent Watchdog Timer (Iwdta)
RX24T Group 24. Independent Watchdog Timer (IWDTa) Independent Watchdog Timer (IWDTa) In this section, “PCLK” is used to refer to PCLKB. 24.1 Overview The independent watchdog timer (IWDT) can be used to detect programs being out of control. The user can detect when a program runs out of control if an underflow occurs, by creating a program that refreshes the IWDT counter before it underflows.
Page 677 RX24T Group 24. Independent Watchdog Timer (IWDTa) To use the IWDT, the IWDT-dedicated clock (IWDTCLK) should be supplied so that the IWDT operates even if the peripheral module clock (PCLK) stops. The bus interface and registers operate with PCLK, and the 14-bit counter and control circuits operate with IWDTCLK.
Page 678: Register Descriptions
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.2 Register Descriptions 24.2.1 IWDT Refresh Register (IWDTRR) Address(es): IWDT.IWDTRR 0008 8030h Value after reset: Description b7 to b0 The counter is refreshed by writing 00h and then writing FFh to this register. The IWDTRR register refreshes the counter of the IWDT.
Page 679: Iwdt Control Register (Iwdtcr)
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.2.2 IWDT Control Register (IWDTCR) Address(es): IWDT.IWDTCR 0008 8032h — — RPSS[1:0] — — RPES[1:0] CKS[3:0] — — TOPS[1:0] Value after reset: Symbol Bit Name Description b1, b0 TOPS[1:0] Timeout Period Select b1 b0 0 0: 128 cycles (007Fh) 0 1: 512 cycles (01FFh) 1 0: 1024 cycles (03FFh)
Page 680 RX24T Group 24. Independent Watchdog Timer (IWDTa) TOPS[1:0] Bits (Timeout Period Select) These bits select the timeout period (period until the counter underflows) from among 128, 512, 1024, or 2048 cycles, taking the divided clock specified by the CKS[3:0] bits as one cycle. After the counter is refreshed, the combination of the CKS[3:0] and TOPS[1:0] bits determines the time (number of IWDTCLK cycles) until the counter underflows.
Page 681 RX24T Group 24. Independent Watchdog Timer (IWDTa) RPES[1:0] Bits (Window End Position Select) These bits select 75%, 50%, 25% or 0% of the count period for the window end position of the counter. The window end position should be a value smaller than the window start position (window start position > window end position). If the window end position is greater than the window start position, only the window start position setting is enabled.
Page 682: Iwdt Status Register (Iwdtsr)
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.2.3 IWDT Status Register (IWDTSR) Address(es): IWDT.IWDTSR 0008 8034h REFEF UNDFF CNTVAL[13:0] Value after reset: Symbol Bit Name Description b13 to b0 CNTVAL[13:0] Counter Value Value counted by the counter UNDFF Underflow Flag 0: No underflow occurred R/(W) 1: Underflow occurred...
Page 683: Iwdt Reset Control Register (Iwdtrcr)
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.2.4 IWDT Reset Control Register (IWDTRCR) Address(es): IWDT.IWDTRCR 0008 8036h RSTIR — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 0. Writing to these bits has no effect. RSTIRQS Reset Interrupt Request Select 0: Non-maskable interrupt request output is enabled.
Page 684: Iwdt Count Stop Control Register (Iwdtcstpr)
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.2.5 IWDT Count Stop Control Register (IWDTCSTPR) Address(es): IWDT.IWDTSCTPR 0008 8038h SLCST — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 0. Writing to these bits has no effect. SLCSTP Sleep Mode Count Stop Control 0: Count stop is disabled.
Page 685: Operation
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.3 Operation 24.3.1 Count Operation in Each Start Mode Select the IWDT start mode by setting the IWDT start mode select bit (OFS0.IWDTSTRT) in option function select register 0. When the OFS0.IWDTSTRT bit is 1 (register start mode), the IWDT control register (IWDTCR), IWDT reset control register (IWDTRCR), and IWDT count stop control register (IWDTCSTPR) are enabled, and counting is started by refreshing (writing) the IWDT refresh register (IWDTRR).
Page 686 RX24T Group 24. Independent Watchdog Timer (IWDTa) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin IWDT Control register (IWDTCR) (1) Initial value Writing to the Writing to the Writing to the (2) Set value register is invalid.
Page 687: Auto-Start Mode
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.3.1.2 Auto-Start Mode When the IWDT start mode select bit (OFS0.IWDTSTRT) in option function select register 0 is 0, auto-start mode is selected, and the IWDT control register (IWDTCR), IWDT reset control register (IWDTRCR), and IWDT count stop control register (IWDTCSTPR) are disabled.
Page 688 RX24T Group 24. Independent Watchdog Timer (IWDTa) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin Refresh the counter Active: High Counting starts Counting starts Counting starts Counting starts Underflow Refresh error Refresh error Status flag Refresh error flag cleared Active: High...
Page 689: Control Over Writing To The Iwdtcr, Iwdtrcr, And Iwdtcstpr Registers
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.3.2 Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers Writing to the IWDT control register (IWDTCR), IWDT reset control register (IWDTRCR), or IWDT count stop control register (IWDTCSTPR) is only possible once between the release from the reset state and the first refresh operation. After a refresh operation (counting starts) or the IWDTCR, IWDTRCR, or IWDTCSTPR register is written to, the protection signal in the IWDT becomes 1 to protect registers IWDTCR, IWDTRCR, and IWDTCSTPR against subsequent attempts at writing.
Page 690: Refresh Operation
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.3.3 Refresh Operation The counter is refreshed and starts operation (counting is started by refreshing) by writing the values 00h and then FFh to the IWDT refresh register (IWDTRR). If a value other than FFh is written after 00h, the counter is not refreshed. After such invalid writing, correct refreshing is performed by again writing 00h and then FFh to the IWDT refresh register (IWDTRR).
Page 691 RX24T Group 24. Independent Watchdog Timer (IWDTa) Figure 24.6 shows the IWDT refresh-operation waveforms when PCLK > IWDTCLK and clock divide ratio = IWDTCLK. Peripheral module clock (PCLK) IWDT-dedicated clock (IWDTCLK) Data written to IWDTRR register IWDTRR register write Valid signal (internal signal) IWDTRR register Invalid...
Page 692: Status Flags
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.3.4 Status Flags The refresh error (IWDTSR.REFEF) and underflow (IWDTSR.UNDFF) flags retain the source of the reset signal output from the IWDT or the source of the interrupt request from the IWDT. Thus, after release from the reset state or interrupt request generation, read the IWDTSR.REFEF and IWDTSR.UNDFF flags to check for the reset or interrupt source.
Page 693: Reading The Counter Value
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.3.7 Reading the Counter Value As the counter in IWDT-dedicated clock (IWDTCLK), the counter value cannot be read directly. The IWDT synchronizes the counter value with the peripheral module clock (PCLK) and stores it in the counter value bits (IWDTSR.CNTVAL[13:0]) of the IWDT status register.
Page 694: Correspondence Between Option Function Select Register 0 (Ofs0) And Iwdt Registers
RX24T Group 24. Independent Watchdog Timer (IWDTa) 24.3.8 Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers Table 24.5 lists the correspondence between option function select register 0 (OFS0) used in auto-start mode and the registers used in register start mode. Do not change the OFS0 register setting during IWDT operation.
Page 695: Serial Communications Interface (Scig)
RX24T Group 25. Serial Communications Interface (SCIg) Serial Communications Interface (SCIg) This MCU has three independent serial communications interface (SCI) channels. The SCI consists of the SCIg module (SCI1, SCI5, and SCI6). The SCIg module (SCI1, SCI5, and SCI6) can handle both asynchronous and clock synchronous serial communications. Asynchronous serial data communications can be carried out with standard asynchronous communications chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communications Interface Adapter (ACIA).
Page 696 RX24T Group 25. Serial Communications Interface (SCIg) Table 25.1 SCIg Specifications (2/2) Item Description Smart card interface Error processing An error signal can be automatically transmitted when detecting a parity error during mode reception Data can be automatically retransmitted when receiving an error signal during transmission Data type Both direct convention and inverse convention are supported.
Page 697 RX24T Group 25. Serial Communications Interface (SCIg) Module data bus SCMR RDRH TDRH RDR (RDRL) TDR (TDRL) MDDR PCLK RXDn/ SEMR Baud rate SSCLn/ PCLK/4 generator SNFR SMISOn PCLK/16 SIMR1 TXDn/ PCLK/64 SIMR2 SSDAn/ SIMR3 SMOSIn SISR RTSn#/ CTSn#/ SPMR SSn# Parity addition Transmission...
Page 698 RX24T Group 25. Serial Communications Interface (SCIg) Module data bus RDRH TDRH SCMR MDDR RDR (RDRL) TDR (TDRL) PCLK SEMR RXDn/ Baud rate SSCLn/ PCLK/4 SNFR generator SMISOn SIMR1 PCLK/16 TXDn/ SIMR2 PCLK/64 SSDAn/ SIMR3 SMOSIn SISR RTSn#/ SPMR CTSn#/ SSn# Transmission TMO0, 2...
Page 699 RX24T Group 25. Serial Communications Interface (SCIg) Table 25.3 to Table 25.5 list the pin configuration of the SCIs for the individual modes. Table 25.3 SCI Pin Configuration in Asynchronous Mode and Clock Synchronous Mode Channel Pin Name Function SCI1 SCK1 SCI1 clock input/output RXD1...
Page 700: Register Descriptions
RX24T Group 25. Serial Communications Interface (SCIg) 25.2 Register Descriptions 25.2.1 Receive Shift Register (RSR) RSR is a shift register which is used to receive serial data input from the RXDn pin and converts it into parallel data. When one frame of data has been received, it is automatically transferred to the RDR register. The RSR register cannot be directly accessed by the CPU.
Page 701: Receive Data Register H, L, Hl (Rdrh, Rdrl, Rdrhl)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.3 Receive Data Register H, L, HL (RDRH, RDRL, RDRHL)  Receive Data Register H (RDRH) Address(es): SCI1.RDRH 0008 A030h, SCI5.RDRH 0008 A0B0h, SCI6.RDRH 0008 A0D0h  Receive Data Register L (RDRL) Address(es): SCI1.RDRL 0008 A031h, SCI5.RDRL 0008 A0B1h, SCI6.RDRL 0008 A0D1h ...
Page 702: Transmit Data Register H, L, Hl (Tdrh, Tdrl, Tdrhl)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.5 Transmit Data Register H, L, HL (TDRH, TDRL, TDRHL)  Transmit Data Register H (TDRH) Address(es): SCI1.TDRH 0008 A02Eh, SCI5.TDRH 0008 A0AEh, SCI6.TDRH 0008 A0CEh  Transmit Data Register L (TDRL) Address(es): SCI1.TDRL 0008 A02Fh, SCI5.TDRL 0008 A0AFh, SCI6.TDRL 0008 A0CFh ...
Page 703: Serial Mode Register (Smr)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.7 Serial Mode Register (SMR) Note: Some bits in SMR have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SMR 0008 A020h, SCI5.SMR 0008 A0A0h, SCI6.SMR 0008 A0C0h STOP CKS[1:0] Value after reset:...
Page 704 RX24T Group 25. Serial Communications Interface (SCIg) STOP Bit (Stop Bit Length) Selects the stop bit length in transmission. In reception, only the first stop bit is checked regardless of this bit setting. If the second stop bit is 0, it is treated as the start bit of the next transmit frame.
Page 705 RX24T Group 25. Serial Communications Interface (SCIg) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SMR 0008 A020h, SMCI5.SMR 0008 A0A0h, SMCI6.SMR 0008 A0C0h BCP[1:0] CKS[1:0] Value after reset: Symbol Bit Name Description b1, b0 CKS[1:0] Clock Select b1 b0 R/W* 0 0: PCLK clock (n = 0)* 0 1: PCLK/4 clock (n = 1)*...
Page 706 RX24T Group 25. Serial Communications Interface (SCIg) PM Bit (Parity Mode) Selects the parity mode for transmission and reception (even or odd). For details on the usage of this bit in smart card interface mode, refer to section 25.6.2, Data Format (Except in Block Transfer Mode).
Page 707: Serial Control Register (Scr)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.8 Serial Control Register (SCR) Note: Some bits in the SCR register have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SCR 0008 A022h, SCI5.SCR 0008 A0A2h, SCI6.SCR 0008 A0C2h MPIE TEIE...
Page 708 RX24T Group 25. Serial Communications Interface (SCIg) Symbol Bit Name Description Receive Enable 0: Serial reception is disabled R/W* 1: Serial reception is enabled Transmit Enable 0: Serial transmission is disabled R/W* 1: Serial transmission is enabled Receive Interrupt Enable 0: RXI and ERI interrupt requests are disabled 1: RXI and ERI interrupt requests are enabled Transmit Interrupt Enable...
Page 709 RX24T Group 25. Serial Communications Interface (SCIg) RIE Bit (Receive Interrupt Enable) Enables or disables RXI and ERI interrupt requests. An RXI interrupt request is disabled by setting the RIE bit to 0. An ERI interrupt request can be canceled by reading 1 from the ORER, FER, or PER flag in the SSR register and then setting the flag to 0, or setting the RIE bit to 0.
Page 710 RX24T Group 25. Serial Communications Interface (SCIg) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SCR 0008 A022h, SMCI5.SCR 0008 A0A2h, SMCI6.SCR 0008 A0C2h MPIE TEIE CKE[1:0] Value after reset: Symbol Bit Name Description  When SMR.GM = 0 b1, b0 CKE[1:0] Clock Enable...
Page 711 RX24T Group 25. Serial Communications Interface (SCIg) RE Bit (Receive Enable) Enables or disables serial reception. When this bit is set to 1, serial reception is started by detecting the start bit. Note that the SMR register should be set prior to setting the RE bit to 1 in order to designate the reception format.
Page 712: Serial Status Register (Ssr)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.9 Serial Status Register (SSR) Some bits in the SSR register have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SSR 0008 A024h, SCI5.SSR 0008 A0A4h, SCI6.SSR 0008 A0C4h TDRE RDRF ORER TEND...
Page 713 RX24T Group 25. Serial Communications Interface (SCIg) PER Flag (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]  When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 714 RX24T Group 25. Serial Communications Interface (SCIg) TDRE Flag (Transmit Data Empty Flag) Indicates whether the TDR register has data to be transmitted. [Setting condition]  When data is transferred from TDR to TSR [Clearing condition]  When data is written to TDR R01UH0576EJ0100 Rev.1.00 Page 714 of 1230 Nov 30, 2015...
Page 715 RX24T Group 25. Serial Communications Interface (SCIg) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SSR 0008 A024h, SMCI5.SSR 0008 A0A4h, SMCI6.SSR 0008 A0C4h TDRE RDRF ORER TEND MPBT Value after reset: Symbol Bit Name Description MPBT Multi-Processor Bit Transfer This bit should be set to 0 in smart card interface mode.
Page 716 RX24T Group 25. Serial Communications Interface (SCIg) PER Flag (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]  When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 717: Smart Card Mode Register (Scmr)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.10 Smart Card Mode Register (SCMR) Address(es): SMCI1.SCMR 0008 A026h, SMCI5.SCMR 0008 A0A6h, SMCI6.SCMR 0008 A0C6h BCP2 — — CHR1 SDIR SINV — SMIF Value after reset: Symbol Bit Name Description SMIF Smart Card Interface Mode 0: Non-smart card interface mode R/W* Select...
Page 718 RX24T Group 25. Serial Communications Interface (SCIg) BCP2 Bit (Base Clock Pulse 2) Selects the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set this bit in combination with the SMR.BCP[1:0] bits. Table 25.7 Combinations of the SCMR.BCP2 Bit and SMR.BCP[1:0] Bits SCMR.BCP2 Bit...
Page 719: Bit Rate Register (Brr)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.11 Bit Rate Register (BRR) Address(es): SCI1.BRR 0008 A021h, SCI5.BRR 0008 A0A1h, SCI6.BRR 0008 A0C1h Value after reset: BRR is an 8-bit register that adjusts the bit rate. As each SCI channel has independent baud rate generator control, different bit rates can be set for each. Table 25.8 shows the relationship between the setting (N) in the BRR and the bit rate (B) for normal asynchronous mode, multi- processor transfer, clock synchronous mode, smart card interface mode, simple SPI mode, and simple I C mode.
Page 720 RX24T Group 25. Serial Communications Interface (SCIg) Table 25.10 Clock Source Settings SMR.CKS[1:0] Bit Setting Clock Source PCLK clock PCLK/4 clock PCLK/16 clock PCLK/64 clock Table 25.11 Base Clock Settings in Smart Card Interface Mode SCMR.BCP2 Bit Setting SMR.BCP[1:0] Bit Setting Base Clock Cycles for 1-bit Period 93 clock cycles 128 clock cycles...
Page 721 RX24T Group 25. Serial Communications Interface (SCIg) Table 25.12 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency PCLK (MHz) 9.8304 12.288 Bit Rate (bps) Error (%) n Error (%) Error (%) n Error (%) n Error (%) 0.03 –0.26 –0.25...
Page 722 RX24T Group 25. Serial Communications Interface (SCIg) Table 25.13 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) SEMR Settings SEMR Settings PCLK BGDM ABCS Maximum Bit Rate PCLK BGDM ABCS Maximum Bit Rate (MHz) (bps) (MHz) (bps) 250000 562500 500000 1125000 1000000...
Page 723 RX24T Group 25. Serial Communications Interface (SCIg) Table 25.14 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Maximum Bit Rate (bps) PCLK (MHz) External Input Clock (MHz) SEMR.ABCS Bit = 0 SEMR.ABCS Bit = 1 2.0000 125000 250000 9.8304 2.4576 153600 307200...
Page 724 RX24T Group 25. Serial Communications Interface (SCIg) Table 25.16 BRR Settings for Various Bit Rates (Clock Synchronous Mode, Simple SPI Mode) Operating Frequency PCLK (MHz) Bit Rate (bps) — — — — — — — — — — 2.5 k 10 k 25 k 50 k...
Page 725 RX24T Group 25. Serial Communications Interface (SCIg) Table 25.18 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Bit Rate (bps) PCLK (MHz) Error (%) 9600 7.1424 0.00 10.00 10.7136 13.00 8.99 14.2848 0.00 16.00 12.01...
Page 726 RX24T Group 25. Serial Communications Interface (SCIg) Table 25.20 BRR Settings for Various Bit Rates (Simple I C Mode) Operating Frequency PCLK (MHz) Bit Rate (bps) Error (%) n Error (%) Error (%) n Error (%) n Error (%) 10 k –2.3 –3.8 –2.3...
Page 727: Modulation Duty Register (Mddr)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.12 Modulation Duty Register (MDDR) Address(es): SCI1.MDDR 0008 A032h, SCI5.MDDR 0008 A0B2h, SCI6.MDDR 0008 A0D2h Value after reset: MDDR corrects the bit rate adjusted by the BRR register. When the BRME bit in SEMR is set to 1, the bit rate generated by the on-chip baud rate generator is evenly corrected according to the settings of MDDR (M/256).
Page 728: Serial Extended Mode Register (Semr)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.13 Serial Extended Mode Register (SEMR) Address(es): SCI1.SEMR 0008 A027h, SCI5.SEMR 0008 A0A7h, SCI6.SEMR 0008 A0C7h RXDES BGDM NFEN ABCS — BRME — ACS0 Value after reset: Symbol Bit Name Description ACS0 Asynchronous Mode (Valid only in asynchronous mode) R/W* Clock Source Select...
Page 729 RX24T Group 25. Serial Communications Interface (SCIg) ACS0 Bit (Asynchronous Mode Clock Source Select) Selects the clock source in the asynchronous mode. The ACS0 bit is valid in asynchronous mode (SMR.CM bit = 0) and when an external clock input is selected (SCR.CKE[1:0] bits = 10b or 11b).
Page 730 RX24T Group 25. Serial Communications Interface (SCIg) cancellation is applied to the SSDAn and SSCLn input signals in simple I C mode. In any mode other than above, set the NFEN bit to 0 to disable the digital noise filter function. When the function is disabled, input signals are transferred as is, as internal signals.
Page 731: Noise Filter Setting Register (Snfr)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.14 Noise Filter Setting Register (SNFR) Address(es): SCI1.SNFR 0008 A028h, SCI5.SNFR 0008 A0A8h, SCI6.SNFR 0008 A0C8h — — — — — NFCS[2:0] Value after reset: Symbol Bit Name Description b2 to b0 NFCS[2:0] Noise Filter Clock Select In asynchronous mode, the standard setting for the base clock is as R/W*...
Page 732: I C Mode Register 1 (Simr1)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.15 C Mode Register 1 (SIMR1) Address(es): SCI1.SIMR1 0008 A029h, SCI5.SIMR1 0008 A0A9h, SCI6.SIMR1 0008 A0C9h IICDL[4:0] — — IICM Value after reset: Symbol Bit Name Description IICM Simple I C Mode Select SMIF IICM R/W* 0: Asynchronous mode, Multi-processor mode,...
Page 733: I 2 C Mode Register 2 (Simr2)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.16 C Mode Register 2 (SIMR2) Address(es): SCI1.SIMR2 0008 A02Ah, SCI5.SIMR2 0008 A0AAh, SCI6.SIMR2 0008 A0CAh IICACK IICCSC IICINT — — — — — Value after reset: Symbol Bit Name Description IICINTM C Interrupt Mode Select 0: Use ACK/NACK interrupts.
Page 734: I 2 C Mode Register 3 (Simr3)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.17 C Mode Register 3 (SIMR3) Address(es): SCI1.SIMR3 0008 A02Bh, SCI5.SIMR3 0008 A0ABh, SCI6.SIMR3 0008 A0CBh IICSTIF IICSTP IICRST IICSTA IICSCLS[1:0] IICSDAS[1:0] AREQ Value after reset: Symbol Bit Name Description IICSTAREQ Start Condition Generation 0: A start condition is not generated.
Page 735 RX24T Group 25. Serial Communications Interface (SCIg) IICSTPREQ Bit (Stop Condition Generation) When a stop condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b as well as setting the IICSTPREQ bit to 1. [Setting condition] ...
Page 736: I C Status Register (Sisr)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.18 C Status Register (SISR) Address(es): SCI1.SISR 0008 A02Ch, SCI5.SISR 0008 A0ACh, SCI6.SISR 0008 A0CCh IICACK — — — — — — — Value after reset: x: Undefined Symbol Bit Name Description IICACKR ACK Reception Data Flag 0: ACK received R/W*...
Page 737: Spi Mode Register (Spmr)
RX24T Group 25. Serial Communications Interface (SCIg) 25.2.19 SPI Mode Register (SPMR) Address(es): SCI1.SPMR 0008 A02Dh, SCI5.SPMR 0008 A0ADh, SCI6.SPMR 0008 A0CDh CKPH CKPOL — — CTSE Value after reset: Symbol Bit Name Description SSn# Pin Function Enable 0: SSn# pin function is disabled. R/W* 1: SSn# pin function is enabled.
Page 738 RX24T Group 25. Serial Communications Interface (SCIg) MFF Flag (Mode Fault Flag) This bit indicates mode fault errors. In a multi-master configuration, determine the mode fault error occurrence by reading the MFF flag. [Setting condition]  Input on the SSn# pin being at the low level during master operation in simple SPI mode (SSE bit = 1 and MSS bit = 0) [Clearing condition] ...
Page 739: Operation In Asynchronous Mode
RX24T Group 25. Serial Communications Interface (SCIg) 25.3 Operation in Asynchronous Mode Figure 25.4 shows the general format for asynchronous serial communications. One frame consists of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). In asynchronous serial communications, the communications line is usually held in the mark state (high level).
Page 740 RX24T Group 25. Serial Communications Interface (SCIg) Table 25.24 Serial Transfer Formats (Asynchronous Mode) SCMR Setting SMR Setting Serial Transfer Format and Frame Length CHR1 STOP 9-bit data STOP 9-bit data STOP STOP 9-bit data STOP 9-bit data STOP STOP 8-bit data STOP 8-bit data...
Page 741: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
RX24T Group 25. Serial Communications Interface (SCIg) 25.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times* the bit rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse* of the base clock, data is latched at the middle of each bit, as shown in Figure 25.5.
Page 742: Clock
RX24T Group 25. Serial Communications Interface (SCIg) 25.3.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be selected as the SCI’s transfer clock, according to the setting of the CM bit in the SMR register and the CKE[1:0] bits in the SCR register.
Page 743: Cts And Rts Functions
RX24T Group 25. Serial Communications Interface (SCIg) 25.3.5 CTS and RTS Functions The CTS function is the use of input on the CTSn# pin in transmission control. Setting the SPMR.CTSE bit to 1 enables the CTS function. When the CTS function is enabled, placing the low level on the CTSn# pin causes transmission to start.
Page 744: Sci Initialization (Asynchronous Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.3.6 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, start by writing the initial value 00h to the SCR register and then continue through the procedure for SCI given in Figure 25.7. Whenever the operating mode or transfer format is changed, the SCR register must be initialized before the change is made.
Page 745: Serial Data Transmission (Asynchronous Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.3.7 Serial Data Transmission (Asynchronous Mode) Figure 25.8 to Figure 25.10 show an example of the operation for serial transmission in asynchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI transfers data from the TDR register* to the TSR register when data is written to the TDR register* in the TXI interrupt handling routine.
Page 746 RX24T Group 25. Serial Communications Interface (SCIg) Data Start bit Parity bit Stop bit D7 0/1 1 D7 0/1 D0 D1 SCR.TE bit 1 frame TXI interrupt flag (IRn in ICU SSR.TEND flag TXI interrupt request Data written to TDR in TXI interrupt Data written to TDR in Data written to TDR in...
Page 747 RX24T Group 25. Serial Communications Interface (SCIg) Data Start bit Parity bit Stop bit Idle state 0 D0 D7 0/1 1 D7 0/1 D7 0/1 1 0 D0 D1 0 D0 (mark state) SCR.TE bit (TIE = 1) TXI interrupt flag (IRn in ICU (TIE = 0) SSR.TEND flag...
Page 748 RX24T Group 25. Serial Communications Interface (SCIg) [ 1 ] SCI initialization: [ 1 ] Initialization Set data transmission. After the TE bit in SCR is set to 1, 1 is output for a frame, and transmission is enabled. Start data transmission [ 2 ] Transmit data write to TDR by a TXI interrupt request: When transmit data is transferred from TDR to TSR, a transmit...
Page 749: Serial Data Reception (Asynchronous Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.3.8 Serial Data Reception (Asynchronous Mode) Figure 25.12 and Figure 25.13 show an example of the operation for serial data reception in asynchronous mode. In serial data reception, the SCI operates as described below. 1.
Page 750 RX24T Group 25. Serial Communications Interface (SCIg) Data Data Data Parity Stop Parity Stop Start bit Start bit Start bit Idle state (mark state) RXI interrupt flag (IRn in ICU* SSR.FER flag RDR data read in RXI interrupt RXI interrupt handling routine request generated...
Page 751 RX24T Group 25. Serial Communications Interface (SCIg) [ 1 ] Initialization [ 1 ] SCI initialization: Set data reception. Start data reception [ 2 ] [ 3 ] Receive error processing and break detection: If a receive error occurs, an ERI interrupt is [ 2 ] generated.
Page 752 RX24T Group 25. Serial Communications Interface (SCIg) [ 3 ] Error processing SSR.ORER flag = 1 Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR. In combination with step [ 7 ], this will make correct reception of the next frame possible.
Page 753: Multi-Processor Communications Function
RX24T Group 25. Serial Communications Interface (SCIg) 25.4 Multi-Processor Communications Function Using the multi-processor communication functions enables to transmit and receive data by sharing a communication line between multiple processors by using asynchronous serial communication in which the multi-processor bit is added. In multi-processor communication, a unique ID code is allocated to each receiving station.
Page 754: Multi-Processor Serial Data Transmission
RX24T Group 25. Serial Communications Interface (SCIg) 25.4.1 Multi-Processor Serial Data Transmission Figure 25.17 is a sample flowchart of multi-processor data transmission. In the ID transmission cycle, the ID should be transmitted with the SSR.MPBT bit set to 1. In the data transmission cycle, the data should be transmitted with the MPBT bit set to 0.
Page 755: Multi-Processor Serial Data Reception
RX24T Group 25. Serial Communications Interface (SCIg) 25.4.2 Multi-Processor Serial Data Reception Figure 25.19 and Figure 25.20 are sample flowcharts of multi-processor data reception. When the SCR.MPIE bit is set to 1, reading the communication data is skipped until reception of the communication data in which the multi-processor bit is set to 1.
Page 756 RX24T Group 25. Serial Communications Interface (SCIg) Initialization [ 1 ] [ 1 ] SCI initialization: Set data reception. Start data reception [ 2 ] ID reception cycle: Set the MPIE bit in SCR to 1 and wait for ID reception.
Page 757 RX24T Group 25. Serial Communications Interface (SCIg) [ 5 ] Error processing SSR.ORER flag = 1 Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR. In combination with step [ 7 ], this will make correct reception of the next frame possible.
Page 758: Operation In Clock Synchronous Mode
RX24T Group 25. Serial Communications Interface (SCIg) 25.5 Operation in Clock Synchronous Mode Figure 25.21 shows the data format for clock synchronous serial data communications. In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data.
Page 759: Cts And Rts Functions
RX24T Group 25. Serial Communications Interface (SCIg) 25.5.2 CTS and RTS Functions In the CTS function, CTSn# pin input is used to control reception/transmission start when the clock source is the internal clock. Setting the SPMR.CTSE bit to 1 enables the CTS function. When the CTS function is enabled, placing the low level on the CTSn# pin causes reception/transmission to start.
Page 760: Sci Initialization (Clock Synchronous Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.5.3 SCI Initialization (Clock Synchronous Mode) Before transmitting and receiving data, start by writing the initial value 00h to the SCR register and then continue through the procedure for SCI given in Figure 25.22. Whenever the operating mode or transfer format is changed, the SCR register must be initialized before the change is made.
Page 761: Serial Data Transmission (Clock Synchronous Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.5.4 Serial Data Transmission (Clock Synchronous Mode) Figure 25.22, Figure 25.23, and Figure 25.24 show an example of the operation for serial transmission in clock synchronous mode. In serial data transmission, the SCI operates as described below. 1.
Page 762 RX24T Group 25. Serial Communications Interface (SCIg) Synchronization clock Serial data Bit 0 Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 SCR.TE bit TXI interrupt flag (IRn in ICU SSR.TEND flag TXI interrupt request TXI interrupt TXI interrupt TXI interrupt generated...
Page 763 RX24T Group 25. Serial Communications Interface (SCIg) Synchronization clock Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Serial data (TIE = 1) TXI interrupt flag (IRn in ICU* (TIE = 0) SSR.TEND flag TEI interrupt Data written to TDR in...
Page 764 RX24T Group 25. Serial Communications Interface (SCIg) [ 1 ] SCI initialization: [ 1 ] Initialization Set data transmission. [ 2 ] Writing transmit data write to TDR by a TXI interrupt Start transmission request: When transmit data is transferred from TDR to TSR, a transmit data empty interrupt (TXI) request is [ 2 ] generated.
Page 765: Serial Data Reception (Clock Synchronous Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.5.5 Serial Data Reception (Clock Synchronous Mode) Figure 25.27 and Figure 25.28 show an example of SCI operation for serial reception in clock synchronous mode. In serial data reception, the SCI operates as described below. 1.
Page 766 RX24T Group 25. Serial Communications Interface (SCIg) Synchronization clock Serial data Bit 6 Bit 7 Bit 0 Bit 7 Bit 0 RXI interrupt flag (IRn in ICU* SSR.ORER flag RXI interrupt RXI interrupt ERI interrupt request RDR data read in RXI request request generated by overrun error...
Page 767 RX24T Group 25. Serial Communications Interface (SCIg) Figure 25.29 shows a sample flowchart for serial data reception. [ 1 ] SCI initialization: Initialization Make input port-pin settings for pins to be used [ 1 ] as RXDn pins. Start data reception [ 2 ] [ 3 ] Receive error processing: If a receive error occurs, read the ORER flag in...
Page 768: Simultaneous Serial Data Transmission And Reception (Clock Synchronous Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.5.6 Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode) Figure 25.30 shows a sample flowchart for simultaneous serial transmit and receive operations in clock synchronous mode. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Page 769: Operation In Smart Card Interface Mode
RX24T Group 25. Serial Communications Interface (SCIg) 25.6 Operation in Smart Card Interface Mode The SCI supports smart card (IC card) interfaces conforming to ISO/IEC 7816-3 (standard for Identification Cards), as an extended function of the SCI. Smart card interface mode can be selected using the appropriate register. 25.6.1 Sample Connection Figure 25.31 shows a sample connection between a smart card (IC card) and this MCU.
Page 770: Data Format (Except In Block Transfer Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.6.2 Data Format (Except in Block Transfer Mode) Figure 25.32 shows the data transfer formats in smart card interface mode.  One frame consists of 8-bit data and a parity bit in asynchronous mode. ...
Page 771: Block Transfer Mode
RX24T Group 25. Serial Communications Interface (SCIg) For communications with IC cards of the direct convention type and inverse convention type, follow the procedure below. (1) Direct Convention Type For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB first as the start character, as shown in Figure 25.33.
Page 772: Receive Data Sampling Timing And Reception Margin
RX24T Group 25. Serial Communications Interface (SCIg) 25.6.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate according to the settings of the BCP2 bit in the SCMR register and the BCP[1:0] bits in the SMR register (the frequency is always 16 times the bit rate in normal asynchronous mode).
Page 773: Sci Initialization (Smart Card Interface Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.6.5 SCI Initialization (Smart Card Interface Mode) Initialize the SCI following the example of flowchart shown in Figure 25.36. Be sure to initialize the SCI before switching from transmission mode to reception mode and vice versa. Even if the RE bit is set to 0, the RDR register is not initialized.
Page 774: Serial Data Transmission (Except In Block Transfer Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.6.6 Serial Data Transmission (Except in Block Transfer Mode) Serial data transmission in smart card interface mode (except in block transfer mode), in that an error signal is sampled and data can be retransmitted, is different from that in non-smart card interface mode. Figure 25.37 shows the data retransfer operation during transmission.
Page 775 RX24T Group 25. Serial Communications Interface (SCIg) Note that the SSR.TEND flag is set in different timings depending on the GM bit setting in the SMR register. Figure 25.38 shows the TEND flag generation timing. I/O data SSR.TEND flag Guard (TXI interrupt) time 12.5 etu (11.5 etu in block transfer mode)
Page 776 RX24T Group 25. Serial Communications Interface (SCIg) Start Initialization Start data transmission SSR.ERS flag = 0? Error processing TXI interrupt Write transmit data to TDR Write all transmit data SSR.ERS flag = 0? Error processing TXI interrupt Set bits TIE, RIE, and TE in SCR to 0 Figure 25.39 Sample Smart Card Interface Transmission Flowchart...
Page 777: Serial Data Reception (Except In Block Transfer Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.6.7 Serial Data Reception (Except in Block Transfer Mode) Serial data reception in smart card interface mode is similar to that in non-smart card interface mode. Figure 25.40 shows the data retransfer operation in reception mode. 1.
Page 778 RX24T Group 25. Serial Communications Interface (SCIg) Start Initialization Start data reception SSR.ORER = 0 and SSR.PER = 0? Error processing RXI interrupt Read data from RDR All data received? Set bits RIE and RE in SCR to 0 Figure 25.41 Sample Smart Card Interface Reception Flowchart R01UH0576EJ0100 Rev.1.00 Page 778 of 1230...
Page 779: Clock Output Control
RX24T Group 25. Serial Communications Interface (SCIg) 25.6.8 Clock Output Control Clock output can be fixed using the CKE[1:0] bits in the SCR register when the GM bit in the SMR register is 1. Specifically, the minimum width of a clock pulse can be specified. Figure 25.42 shows an example of clock output fixing timing when the CKE[0] bit is controlled with GM = 1 and CKE[1] = 0.
Page 780: Operation In Simple I C Mode
RX24T Group 25. Serial Communications Interface (SCIg) 25.7 Operation in Simple I C Mode Simple I C-bus format is composed of 8 data bits and an acknowledge bit. By continuing into a slave-address frame after a start condition or restart condition, a master device is able to specify a slave device as the partner for communications. The currently specified slave device remains valid until a new slave device is specified or a stop condition is satisfied.
Page 781: Generation Of Start, Restart, And Stop Conditions
RX24T Group 25. Serial Communications Interface (SCIg) 25.7.1 Generation of Start, Restart, and Stop Conditions Writing 1 to the IICSTAREQ bit in the SIMR3 register causes the generation of a start condition. The generation of a start condition proceeds through the following operations. ...
Page 782 RX24T Group 25. Serial Communications Interface (SCIg) Figure 25.45 shows the timing of operations in the generation of start, restart, and stop conditions. SSCLn SSDAn SIMR3.IICSTAREQ SIMR3.IICRSTAREQ SIMR3.IICSTPREQ SIMR3.IICSDAS[1:0] 11b 01b SIMR3.IICSCLS[1:0] Restart-condition generated Stop-condition generated Start-condition generated interrupt request interrupt request interrupt request Figure 25.45...
Page 783: Clock Synchronization
RX24T Group 25. Serial Communications Interface (SCIg) 25.7.2 Clock Synchronization The SSCLn line may be placed at the low level in the case of a wait inserted by a slave device as the other side of transfer. Setting the IICCSC bit in the SIMR2 register to 1 applies control to obtain synchronization when the levels of the internal SSCLn clock signal and the level being input on the SSCLn pin differ.
Page 784: Ssda Output Delay
RX24T Group 25. Serial Communications Interface (SCIg) 25.7.3 SSDA Output Delay The IICDL[4:0] bits in the SIMR1 register can be used to set a delay for output on the SSDAn pin relative to falling edges of output on the SSCLn pin. Delay-time settings from 0 to 31 are selectable, representing periods of the corresponding numbers of cycles of the clock signal from the on-chip baud rate generator (derived by frequency-dividing the base clock, PCLK, by the divisor selected by the CKS[1:0] bits in the SMR register).
Page 785: Sci Initialization (Simple I 2 C Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.7.4 SCI Initialization (Simple I C Mode) Before transferring data, write the initial value (00h) to SCR and initialize the interface following the example shown in Figure 25.48. When changing the operating mode, transfer format, and so on, be sure to set SCR to its initial value before proceeding with the changes.
Page 786: Operation In Master Transmission (Simple I 2 C Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.7.5 Operation in Master Transmission (Simple I C Mode) Figure 25.49 and Figure 25.50 show examples of operations in master transmission and Figure 25.51 is a flowchart showing the procedure for data transmission. The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts) and the value of the SCR.RIE bit is assumed to be 0 (RXI and ERI interrupt requests are disabled).
Page 787 RX24T Group 25. Serial Communications Interface (SCIg) [ 1 ] Initialization for simple I C mode Initialization [ 1 ] For transmission, set the SCR.RIE bit to 0 (RXI and ERI interrupts requests are disabled) Start of transmission [ 2 ] Generate a start condition.
Page 788: Master Reception (Simple I 2 C Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.7.6 Master Reception (Simple I C Mode) Figure 25.52 shows an example of operations in simple I C mode master reception and Figure 25.53 is a flowchart showing the procedure for master reception. The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts).
Page 789 RX24T Group 25. Serial Communications Interface (SCIg) Initialization [ 1 ] [ 1 ] Initialization for simple I C mode: Set the RIE bit in SCR to 0. Start of reception [ 2 ] Generate a start condition. [ 3 ] Writing to TDR: Simultaneously set the SIMR3.IICSTAREQ bit Writing the slave address and value for the R/W bit to...
Page 790: Operation In Simple Spi Mode
RX24T Group 25. Serial Communications Interface (SCIg) 25.8 Operation in Simple SPI Mode As an extended function, the SCI supports a simple SPI mode that handles transfer among one or multiple master devices and multiple slave devices. Making the settings for clock synchronous mode (SCMR.SMIF = 0, SIMR1.IICM = 0, SMR.CM = 1) plus setting the SSE bit in the SPMR to 1 places the SCI in simple SPI mode.
Page 791: States Of Pins In Master And Slave Modes
RX24T Group 25. Serial Communications Interface (SCIg) 25.8.1 States of Pins in Master and Slave Modes The direction (input or output) of pins for the simple SPI mode interface differs according to whether the device is a master (SCR.CKE[1:0] = 00b or 01b and SPMR.MSS = 0) or slave (SCR.CKE[1:0] = 10b or 11b and SPMR.MSS = 1). Table 25.26 lists the states of pins according to the mode and the level on the SSn# pin.
Page 792: Relationship Between Clock And Transmit/Receive Data
RX24T Group 25. Serial Communications Interface (SCIg) 25.8.4 Relationship between Clock and Transmit/Receive Data The CKPOL and CKPH bits in the SPMR can be used to set up the clock for use in transmission and reception in four different ways. The relation between the clock signal and the transmission and reception of data is shown in Figure 25.55.
Page 793: Sci Initialization (Simple Spi Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.8.5 SCI Initialization (Simple SPI Mode) The procedure is the same as for initialization in clock synchronous mode Figure 25.22, Sample SCI Initialization Flowchart. The CKPOL and CKPH bits in the SPMR must be set to ensure that the kind of clock signal they select is suitable for both master and slave devices.
Page 794: 25.10 Noise Cancellation Function
RX24T Group 25. Serial Communications Interface (SCIg) 25.10 Noise Cancellation Function Figure 25.57 shows the configuration of the noise filter used for noise cancellation. The noise filter consists of two stages of flip-flop circuits and a match-detection circuit. When the level on the pin matches in three consecutive samples taken at the set sampling interval, the matching level continues to be conveyed internally until the level on the pin again matches in three consecutive samples.
Page 795: 25.11 Interrupt Sources
RX24T Group 25. Serial Communications Interface (SCIg) 25.11 Interrupt Sources 25.11.1 Buffer Operations for TXI and RXI Interrupts If the conditions for a TXI and RXI interrupt are satisfied while the interrupt status flag in the interrupt controller is 1, the SCI does not output the interrupt request but retains it internally (with a capacity for retention of one request per source).
Page 796: Interrupts In Smart Card Interface Mode
RX24T Group 25. Serial Communications Interface (SCIg) 25.11.3 Interrupts in Smart Card Interface Mode Table 25.28 lists interrupt sources in smart card interface mode. A transmit end interrupt (TEI) request cannot be used in this mode. Table 25.28 SCI Interrupt Sources Name Interrupt Source Interrupt Flag...
Page 797: Interrupts In Simple I C Mode
RX24T Group 25. Serial Communications Interface (SCIg) 25.11.4 Interrupts in Simple I C Mode C mode are listed in Table 25.29. The STI interrupt is allocated to the transmit end The interrupt sources in simple I interrupt (TEI) request. The receive error interrupt (ERI) request cannot be used. The DTC can also be used to handle transfer in simple I C mode.
Page 798: 25.12 Usage Notes
RX24T Group 25. Serial Communications Interface (SCIg) 25.12 Usage Notes 25.12.1 Setting the Module Stop Function Module stop control register B (MSTPCRB) is used to stop and start SCI operations. With the value after a reset, SCI operations are stopped. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption.
Page 799: Restrictions On Clock Synchronous Transmission (Clock Synchronous Mode And Simple Spi Mode)
RX24T Group 25. Serial Communications Interface (SCIg) 25.12.6 Restrictions on Clock Synchronous Transmission (Clock Synchronous Mode and Simple SPI Mode) When the external clock source is used as a synchronization clock, the following restrictions apply. (1) Start of transmission Update TDR by the CPU or DTC and wait for at least five PCLK cycles before allowing the transmit clock to be input (see Figure 25.58).
Page 800: Restrictions On Using Dtc
RX24T Group 25. Serial Communications Interface (SCIg) 25.12.7 Restrictions on Using DTC When using the DTC to read RDR, RDRH, and RDRL, be sure to set the receive data full interrupt (RXI) as the activation source of the relevant SCI. 25.12.8 Notes on Starting Transfer At the point where transfer starts when the interrupt status flag (IRn.IR bit) in the interrupt controller is 1, follow the...
Page 801 RX24T Group 25. Serial Communications Interface (SCIg) Data transmission [ 1 ] Data being transmitted is lost halfway. Data can be [ 1 ] All data transmitted? normally transmitted from the CPU by setting the TE bit in SCR to 1, reading SSR, and writing data to TDR after canceling software standby mode.
Page 802 RX24T Group 25. Serial Communications Interface (SCIg) Transition to software standby Software standby mode mode canceled Port mode register (PMR) setting SCR.TE The level at transition to software standby mode is retained SCKn output pin TXDn output pin The level before transition to Port input/output High output Stop...
Page 803: External Clock Input In Clock Synchronous Mode And Simple Spi Mode
RX24T Group 25. Serial Communications Interface (SCIg) Data reception [ 1 ] Data being received is invalid. [ 1 ] RXI interrupt Read receive data in RDR SCR.RE = 0 Make transition to software standby mode [ 2 ] Setting for the module stop state is included. [ 2 ] Cancel software standby mode Change operating mode?
Page 804: Limitations On Simple Spi Mode
RX24T Group 25. Serial Communications Interface (SCIg) 25.12.11 Limitations on Simple SPI Mode (1) Master Mode  Use a resistor to pull up or pull down the clock line matching the initial settings for the transfer clock set by the SPMR.CKPH and CKPOL bits when the SPMR.SSE bit is 1.
Page 805: Note On Transmit Enable Bit (Te Bit)
RX24T Group 25. Serial Communications Interface (SCIg) 25.12.12 Note on Transmit Enable Bit (TE Bit) When setting the SCR.TE bit to 0 (serial transmission is disabled) while the pin function is “TXDn”, output of the pin becomes high impedance. Prevent the TXDn line from becoming high impedance by any of the following ways: (1) Connect a pull-up resistor to the TXDn line.
Page 806: I C-Bus Interface (Riica)
RX24T Group 26. I C-bus Interface (RIICa) C-bus Interface (RIICa) This MCU has a single-channel I C-bus interface (RIIC). The RIIC module conforms with the NXP I C-bus (Inter-IC bus) interface and provides a subset of its functions. In this section, “PCLK” is used to refer to PCLKB. 26.1 Overview Table 26.1 lists the specifications of the RIIC, Figure 26.1 shows a block diagram of the RIIC, and Figure 26.2 shows...
Page 807 RX24T Group 26. I C-bus Interface (RIICa) Table 26.1 RIIC Specifications (2/2) Item Description Low power consumption Module stop state can be set. function  Four RIIC operating modes Master transmit mode, master receive mode, slave transmit mode, and slave receive mode PCLK CKS[2:0] ICMR1...
Page 808 RX24T Group 26. I C-bus Interface (RIICa) Power supply for pull-up (VCC to 5 V) SCLin SCLout# SDAin SDAout# (Master) SCLin SCLin SCLout# SCLout# SDAin SDAin SDAout# SDAout# (Slave 1) (Slave 2) Figure 26.2 I/O Pin Connection to the External Circuit (I C-bus Configuration Example) The input level of the signals for RIIC is CMOS when I C-bus is selected (ICMR3.SMBS bit is 0), or TTL when SMBus...
Page 809: Register Descriptions
RX24T Group 26. I C-bus Interface (RIICa) 26.2 Register Descriptions 26.2.1 C-bus Control Register 1 (ICCR1) Address(es): RIIC0.ICCR1 0008 8300h IICRST SOWP SCLO SDAO SCLI SDAI Value after reset: Symbol Bit Name Description SDAI SDA Line Monitor 0: SDA0 line is low. 1: SDA0 line is high.
Page 810 RX24T Group 26. I C-bus Interface (RIICa) CLO Bit (Extra SCL Clock Cycle Output) This bit is used to output an extra SCL clock cycle for debugging or error processing. Normally, set the bit to 0. Setting the bit to 1 in a normal communication state causes a communication error. For details on this function, refer to section 26.11.2, Extra SCL Clock Cycle Output Function.
Page 811: I 2 C-Bus Control Register 2 (Iccr2)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.2 C-bus Control Register 2 (ICCR2) Address(es): RIIC0.ICCR2 0008 8301h BBSY — — Value after reset: Symbol Bit Name Description — Reserved This bit is read as 0. The write value should be 0. Start Condition Issuance 0: Does not request to issue a start condition.
Page 812 RX24T Group 26. I C-bus Interface (RIICa) RS Bit (Restart Condition Issuance Request) This bit is used to request that a restart condition be issued in master mode. When this bit is set to 1 to request to issue a restart condition, a restart condition is issued when the BBSY flag is set to 1 (bus busy state) and the MST bit is set to 1 (master mode).
Page 813 RX24T Group 26. I C-bus Interface (RIICa) TRS Bit (Transmit/Receive Mode) This bit indicates transmit or receive mode. The RIIC is in receive mode when the TRS bit is set to 0 and is in transmit mode when the bit is set to 1. Combination of this bit and the MST bit indicates the operating mode of the RIIC.
Page 814 RX24T Group 26. I C-bus Interface (RIICa) BBSY Flag (Bus Busy Detection Flag) The BBSY flag indicates whether the I C-bus is occupied (bus busy state) or released (bus free state). This bit is set to 1 when the SDA0 line changes from high to low under the condition of SCL0 line = high, assuming that a start condition has been issued.
Page 815: I 2 C-Bus Mode Register 1 (Icmr1)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.3 C-bus Mode Register 1 (ICMR1) Address(es): RIIC0.ICMR1 0008 8302h MTWP CKS[2:0] BCWP BC[2:0] Value after reset: Symbol Bit Name Description b2 to b0 BC[2:0] Bit Counter R/W* 0 0 0: 9 bits 0 0 1: 2 bits 0 1 0: 3 bits 0 1 1: 4 bits...
Page 816: I 2 C-Bus Mode Register 2 (Icmr2)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.4 C-bus Mode Register 2 (ICMR2) Address(es): RIIC0.ICMR2 0008 8303h DLCS SDDL[2:0] — TMOH TMOL TMOS Value after reset: Symbol Bit Name Description TMOS Timeout Detection Time Select 0: Long mode is selected. 1: Short mode is selected.
Page 817 RX24T Group 26. I C-bus Interface (RIICa) TMOH Bit (Timeout H Count Control) This bit is used to enable or disable the internal counter of the timeout function to count up while the SCL0 line is held high when the timeout function is enabled (ICFER.TMOE bit is 1). SDDL[2:0] Bits (SDA Output Delay Counter) The SDA output can be delayed by the SDDL[2:0] setting.
Page 818: I 2 C-Bus Mode Register 3 (Icmr3)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.5 C-bus Mode Register 3 (ICMR3) Address(es): RIIC0.ICMR3 0008 8304h WAIT RDRFS ACKW SMBS ACKBT ACKBR NF[1:0] Value after reset: Symbol Bit Name Description b1, b0 NF[1:0] Noise Filter Stage Select b1 b0 0 0: Noise of up to one IIC ...
Page 819 RX24T Group 26. I C-bus Interface (RIICa) ACKBR Bit (Receive Acknowledge) This bit is used to store the acknowledge bit information received from the receive device in transmit mode. [Setting condition]  When 1 is received as the acknowledge bit with the ICCR2.TRS bit set to 1 [Clearing conditions] ...
Page 820: I 2 C-Bus Function Enable Register (Icfer)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.6 C-bus Function Enable Register (ICFER) Address(es): RIIC0.ICFER 0008 8305h — SCLE NACKE SALE NALE MALE TMOE Value after reset: Symbol Bit Name Description TMOE Timeout Function Enable 0: The timeout function is disabled. 1: The timeout function is enabled.
Page 821 RX24T Group 26. I C-bus Interface (RIICa) NACKE Bit (NACK Reception Transfer Suspension Enable) This bit is used to specify whether to continue or discontinue the transfer operation when NACK is received from the slave device in transmit mode. Normally, set this bit to 1. When NACK is received with the NACKE bit set to 1, the next transfer operation is suspended.
Page 822: I 2 C-Bus Status Enable Register (Icser)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.7 C-bus Status Enable Register (ICSER) Address(es): RIIC0.ICSER 0008 8306h HOAE — DIDE — GCAE SAR2E SAR1E SAR0E Value after reset: Symbol Bit Name Description SAR0E Slave Address Register 0 Enable 0: Slave address in registers SARL0 and SARU0 is disabled. 1: Slave address in registers SARL0 and SARU0 is enabled.
Page 823 RX24T Group 26. I C-bus Interface (RIICa) HOAE Bit (Host Address Enable) This bit is used to specify whether to ignore received host address (0001 000b) when the ICMR3.SMBS bit is 1. When this bit is set to 1 while the ICMR3.SMBS bit is 1, if the received slave address matches the host address, the RIIC recognizes the received slave address as the host address independently of the slave addresses set in registers SARLy and SARUy (y = 0 to 2) and performs the receive operation.
Page 824: I 2 C-Bus Interrupt Enable Register (Icier)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.8 C-bus Interrupt Enable Register (ICIER) Address(es): RIIC0.ICIER 0008 8307h TEIE NAKIE SPIE STIE ALIE TMOIE Value after reset: Symbol Bit Name Description TMOIE Timeout Interrupt Request Enable 0: Timeout interrupt (TMOI) request is disabled. 1: Timeout interrupt (TMOI) request is enabled.
Page 825 RX24T Group 26. I C-bus Interface (RIICa) TEIE Bit (Transmit End Interrupt Request Enable) This bit is used to enable or disable transmit end interrupt (TEI) requests when the ICSR2.TEND flag is set to 1. An TEI interrupt request is canceled by setting the TEND flag or the TEIE bit to 0. TIE Bit (Transmit Data Empty Interrupt Request Enable) This bit is used to enable or disable transmit data empty interrupt (TXI) requests when the ICSR2.TDRE flag is set to 1.
Page 826: I 2 C-Bus Status Register 1 (Icsr1)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.9 C-bus Status Register 1 (ICSR1) Address(es): RIIC0.ICSR1 0008 8308h — — AAS2 AAS1 AAS0 Value after reset: Symbol Bit Name Description AAS0 Slave Address 0 Detection Flag 0: Slave address 0 is not detected. R/(W) 1: Slave address 0 is detected.
Page 827 RX24T Group 26. I C-bus Interface (RIICa) For 10-bit address format: SARUy.FS bit = 1  When the received slave address does not match a value of (11110b + SARUy.SVA[1:0] bits) with the ICSER.SARyE bit set to 1 (slave address y detection enabled) This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the first byte.
Page 828 RX24T Group 26. I C-bus Interface (RIICa) (host address detection is enabled) This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the first byte.  When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset R01UH0576EJ0100 Rev.1.00 Page 828 of 1230 Nov 30, 2015...
Page 829: I 2 C-Bus Status Register 2 (Icsr2)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.10 C-bus Status Register 2 (ICSR2) Address(es): RIIC0.ICSR2 0008 8309h TDRE TEND RDRF NACKF STOP START TMOF Value after reset: Symbol Bit Name Description TMOF Timeout Detection Flag 0: Timeout is not detected. R/(W) 1: Timeout is detected.
Page 830 RX24T Group 26. I C-bus Interface (RIICa) [Setting conditions] When master arbitration-lost detection is enabled: ICFER.MALE = 1  When the internal SDA output state does not match the SDA0 line level at the rising edge of SCL clock except for the ACK period during data (including slave address) transmission in master transmit mode (when the SDA0 line is driven low while the internal SDA output is at a high level (the SDA0 pin is in the high-impedance state)) ...
Page 831 RX24T Group 26. I C-bus Interface (RIICa) NACKF Flag (NACK Detection Flag) [Setting condition]  When acknowledge is not received (NACK is received) from the receive device in transmit mode with the ICFER.NACKE bit set to 1 (transfer suspension enabled) [Clearing conditions] ...
Page 832: Slave Address Register Ly (Sarly) (Y = 0 To 2)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2) Address(es): RIIC0.SARL0 0008 830Ah, RIIC0.SARL1 0008 830Ch, RIIC0.SARL2 0008 830Eh SVA[6:0] SVA0 Value after reset: Symbol Bit Name Description SVA0 10-Bit Address LSB A slave address is set.
Page 833: Slave Address Register Uy (Saruy) (Y = 0 To 2)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2) Address(es): RIIC0.SARU0 0008 830Bh, RIIC0.SARU1 0008 830Dh, RIIC0.SARU2 0008 830Fh — — — — — SVA[1:0] Value after reset: Symbol Bit Name Description 7-Bit/10-Bit Address Format Select 0: The 7-bit address format is selected.
Page 834: I 2 C-Bus Bit Rate Low-Level Register (Icbrl)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.13 C-bus Bit Rate Low-Level Register (ICBRL) Address(es): RIIC0.ICBRL 0008 8310h — — — BRL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 BRL[4:0] Bit Rate Low-Level Period Low-level period of SCL clock b7 to b5 —...
Page 835: I 2 C-Bus Bit Rate High-Level Register (Icbrh)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.14 C-bus Bit Rate High-Level Register (ICBRH) Address(es): RIIC0.ICBRH 0008 8311h — — — BRH[4:0] Value after reset: Symbol Bit Name Description b4 to b0 BRH[4:0] Bit Rate High-Level Period High-level period of SCL clock b7 to b5 —...
Page 836 RX24T Group 26. I C-bus Interface (RIICa) Table 26.5 Examples of ICBRH/ICBRL Settings for Transfer Rate Operating Frequency PCLK (MHz) Transfer 12.5 Rate (kbps) CKS[2:0] ICBRH ICBRL CKS[2:0] ICBRH ICBRL CKS[2:0] ICBRH ICBRL 100b 22 (F6h) 25 (F9h) 101b 13 (EDh) 15 (EFh) 101b 16 (F0h)
Page 837: I 2 C-Bus Transmit Data Register (Icdrt)
RX24T Group 26. I C-bus Interface (RIICa) 26.2.15 C-bus Transmit Data Register (ICDRT) Address(es): RIIC0.ICDRT 0008 8312h Value after reset: When the ICDRT register detects a space in the I C-bus shift register (ICDRS), it transfers the transmit data that has been written to the ICDRT register to the ICDRS register and starts transmitting data in transmit mode.
Page 838: Operation
RX24T Group 26. I C-bus Interface (RIICa) 26.3 Operation 26.3.1 Communication Data Format The I C-bus format consists of 8-bit data and 1-bit acknowledge. The first byte following a start condition or restart condition is an address byte used to specify a slave device with which the master device communicates. The specified slave is valid until a new slave is specified or a stop condition is issued.
Page 839: Initial Settings
RX24T Group 26. I C-bus Interface (RIICa) 26.3.2 Initial Settings Before starting data transmission and reception, initialize the RIIC according to the procedure in Figure 26.5. Set the ICCR1.ICE bit to 1 (internal reset) after setting the ICCR1.IICRST bit to 1 (RIIC reset) with the ICCR1.ICE bit set to 0 (SCL0 and SDA0 pins in inactive state).
Page 840: Master Transmit Operation
RX24T Group 26. I C-bus Interface (RIICa) 26.3.3 Master Transmit Operation In master transmit operation, the RIIC outputs the SCL clock and transmitted data signals as the master device, and the slave device returns acknowledgments. Figure 26.6 shows an example of usage of master transmission and Figure 26.7 to Figure 26.9 show the timing of operations in master transmission.
Page 841 RX24T Group 26. I C-bus Interface (RIICa) Master transmission [1] Initial settings Initial settings ICCR2.BBSY = 0? [2] Check I C-bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.NACKF = 0? ICSR2.TDRE = 1? [3] Transmit slave address and W (first byte). [4] Check ACK and set transmit data.
Page 842 RX24T Group 26. I C-bus Interface (RIICa) Automatic low-hold (to prevent wrong transmission) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + W) Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF ICDRT 7-bit address + W DATA 1...
Page 843: Master Receive Operation
RX24T Group 26. I C-bus Interface (RIICa) SCL0 SDA0 A/NA DATA n-2 DATA n-1 DATA n BBSY Transmit data (DATA n) Transmit data (DATA n-1) TDRE TEND RDRF DATA n-1 ICDRT DATA n ICDRS DATA n-2 DATA n-1 DATA n XXXX (Initial value/final receive data) ICDRR 0 (ACK)
Page 844 RX24T Group 26. I C-bus Interface (RIICa) Since the ICSR2.NACKF flag being 1 at this time indicates that no slave device recognized the address or there was an error in communications, write 1 to the ICCR2.SP bit to issue a stop condition. For master reception from a device with a 10-bit address, start by using master transmission to issue the 10-bit address, and then issue a restart condition.
Page 845 RX24T Group 26. I C-bus Interface (RIICa) Master reception starts Initial settings (1) Initial settings ICCR2.BBSY = 0? (2) Check I C-bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.TDRE = 1? Write the ICDRT register (3) Transmit the slave address followed by R and check ACK.
Page 846 RX24T Group 26. I C-bus Interface (RIICa) Master reception Initial settings [1] Initial settings ICCR2.BBSY = 0? [2] Check I C-bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.TDRE = 1? Write data to ICDRT register [3] Transmit the slave address followed by R and check ACK.
Page 847 RX24T Group 26. I C-bus Interface (RIICa) Automatic low hold Master transmit mode Master receive mode (to prevent wrong transmission) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + R) TDRE Receive data (7-bit address + R) Receive data (DATA 1) TEND RDRF...
Page 848 RX24T Group 26. I C-bus Interface (RIICa) Automatic low hold (WAIT) Automatic low hold (WAIT) SCL0 NACK SDA0 DATA n-2 DATA n-1 DATA n BBSY TDRE Receive data (DATA n-2) Receive data (DATA n-1) Receive data (DATA n) TEND RDRF XXXX (last data for transmission ICDRT [7-bit addresses + R/Upper 10 bits + R])
Page 849: Slave Transmit Operation
RX24T Group 26. I C-bus Interface (RIICa) 26.3.5 Slave Transmit Operation In slave transmit operation, the master device outputs the SCL clock, the RIIC transmits data as a slave device, and the master device returns acknowledgments. Figure 26.15 shows an example of usage of slave transmission and Figure 26.16 and Figure 26.17 show the timing of operations in slave transmission.
Page 850 RX24T Group 26. I C-bus Interface (RIICa) Slave transmission [1] Initial settings Initial settings ICSR2.NACKF = 0? ICSR2.TDRE = 1? Write data to ICDRT register [2], [3] Check ACK bit and set transmit data (Checking of ACK not necessary immediately after address is received) All data transmitted? ICSR2.TEND = 1?
Page 851 RX24T Group 26. I C-bus Interface (RIICa) Slave receive mode Slave transmit mode Automatic low hold (to prevent wrong transmission) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF AASy XXXX (Initial value/last data for transmission)
Page 852: Slave Receive Operation
RX24T Group 26. I C-bus Interface (RIICa) 26.3.6 Slave Receive Operation In slave receive operation, the master device outputs the SCL clock and transmit data, and the RIIC returns acknowledgments as a slave device. Figure 26.18 shows an example of usage of slave reception and Figure 26.19 and Figure 26.20 show the timing of operations in slave reception.
Page 853 RX24T Group 26. I C-bus Interface (RIICa) Automatic low hold (to prevent failure to receive data) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY TDRE Receive data (7-bit address + W) Receive data (DATA 1) TEND RDRF AASy ICDRT XXXX (Initial value/last data for transmission) 7-bit address + W...
Page 854: Scl Synchronization Circuit
RX24T Group 26. I C-bus Interface (RIICa) 26.4 SCL Synchronization Circuit In generation of the SCL clock, the RIIC starts counting out the value for width at high level specified in the ICBRH register when it detects a rising edge on the SCL0 line and drives the SCL0 line low once counting of the width at high level is complete.
Page 855: Sda Output Delay Function
RX24T Group 26. I C-bus Interface (RIICa) 26.5 SDA Output Delay Function The RIIC module incorporates a function for delaying output on the SDA line. The delay can be applied to all output (issuing of the start, restart, and stop conditions, data, and the ACK and NACK signals) on the SDA line. With the SDA output delay function, SDA output is delayed from detection of a falling edge of the SCL signal to ensure that the SDA signal is output within the interval over which the SCL clock is at the low level.
Page 856: Digital Noise Filter Circuits
RX24T Group 26. I C-bus Interface (RIICa) 26.6 Digital Noise Filter Circuits The states of the SCL0 and SDA0 pins are conveyed to the internal circuitry through analog noise-filter and digital noise- filter circuits. Figure 26.23 is a block diagram of the digital noise-filter circuit. The on-chip digital noise-filter circuit of the RIIC consists of four flip-flop circuit stages connected in series and a match- detection circuit.
Page 857: Address Match Detection
RX24T Group 26. I C-bus Interface (RIICa) 26.7 Address Match Detection The RIIC can set three unique slave addresses in addition to the general call address and host address, and also can set 7- bit or 10-bit slave addresses. 26.7.1 Slave-Address Match Detection The RIIC can set three unique slave addresses, and has a slave address detection function for each unique slave address.
Page 858 RX24T Group 26. I C-bus Interface (RIICa) [10-bit address format: Slave reception] SCL0 Upper 2 bits 10-bit slave address (lower 8 bits) Data SDA0 BBSY Address match AASy Receive data (lower addresses) TDRE RDRF Read ICDRR register (Dummy read [lower addresses]) [10-bit address format: Slave transmission] 1 to 8 SCL0...
Page 859: Detection Of The General Call Address
RX24T Group 26. I C-bus Interface (RIICa) 26.7.2 Detection of the General Call Address The RIIC has a facility for detecting the general call address (0000 000b + 0 (write)). This is enabled by setting the ICSER.GCAE bit to 1. If the address received after a start or restart condition is issued is 0000 000b + 1 (read) (start byte), the RIIC recognizes this as the address of a slave device with an “all-zero”...
Page 860: Device-Id Address Detection
RX24T Group 26. I C-bus Interface (RIICa) 26.7.3 Device-ID Address Detection The RIIC module has a facility for detecting device-ID addresses conformant with the I C-bus specification (Rev. 03). When the RIIC receives 1111 100b as the first byte after a start condition or restart condition was issued with the ICSER.DIDE bit set to 1, the RIIC recognizes the address as a device ID, sets the ICSR1.DID flag to 1 on the rising edge of the eighth SCL clock cycle when the following R/W# bit is 0, and then compares the second and subsequent bytes with its own slave address.
Page 861 RX24T Group 26. I C-bus Interface (RIICa) [Device-ID reception] SCL0 SDA0 Address BBSY Slave address match AASy Device-ID match (1111 100b + R) Device-ID match (1111 100b + W) Receive data (7-bit address/lower 10 bits) TDRE RDRF Read ICDRR register (Dummy read [7-bit address/lower 10 bits]) [When address received after a restart condition is detected does not match the device-ID ] SCL0...
Page 862: Host Address Detection
RX24T Group 26. I C-bus Interface (RIICa) 26.7.4 Host Address Detection The RIIC has a function to detect the host address while the SMBus is operating. When the ICSER.HOAE bit is set to 1 while the ICMR3.SMBS bit is 1, the RIIC can detect the host address (0001 000b) in slave receive mode (bits MST and TRS in the ICCR2 register are 00b).
Page 863: Automatic Low-Hold Function For Scl
RX24T Group 26. I C-bus Interface (RIICa) 26.8 Automatic Low-Hold Function for SCL 26.8.1 Function to Prevent Wrong Transmission of Transmit Data If the shift register (ICDRS) is empty when data have not been written to the I C-bus transmit data register (ICDRT) with the RIIC in transmission mode (ICCR2.TRS bit is 1), the SCL0 line is automatically held at the low level over the intervals shown below.
Page 864: Nack Reception Transfer Suspension Function
RX24T Group 26. I C-bus Interface (RIICa) 26.8.2 NACK Reception Transfer Suspension Function The RIIC has a function to suspend transfer operation when NACK is received in transmit mode (ICCR2.TRS bit is 1). This function is enabled when the ICFER.NACKE bit is set to 1 (transfer suspension enabled). If the next transmit data has already been written (ICSR2.TDRE flag is 0) when NACK is received, next data transmission at the falling edge of the ninth SCL clock cycle is automatically suspended.
Page 865 RX24T Group 26. I C-bus Interface (RIICa) (1) 1-Byte Receive Operation and Automatic Low-Hold Function Using the WAIT Bit When the ICMR3.WAIT bit is set to 1, the RIIC performs 1-byte receive operation using the WAIT bit function. Furthermore, when the ICMR3.RDRFS bit is 0, the RIIC automatically sends the ICMR3.ACKBT bit value for the acknowledge bit in the period from the falling edge of the eighth SCL clock cycle to the falling edge of the ninth SCL clock cycle, and automatically holds the SCL0 line low at the falling edge of the ninth SCL clock cycle using the WAIT bit function.
Page 866: Arbitration-Lost Detection Functions
RX24T Group 26. I C-bus Interface (RIICa) 26.9 Arbitration-Lost Detection Functions In addition to the normal arbitration-lost detection function defined by the I C-bus specification, the RIIC has functions to prevent double-issue of a start condition, to detect arbitration-lost during transmission of NACK, and to detect arbitration-lost in slave transmit mode.
Page 867 RX24T Group 26. I C-bus Interface (RIICa) [When slave addresses conflict] Transmit data mismatch Release SCL/SDA (Arbitration lost) SCL0 SDA0 SCL0 SDA0 Data Data BBSY Address match Address mismatch AASy TDRE Clear AL flag to 0 [When data transmission conflicts after general call address is sent] Transmit data mismatch Release SCL/SDA (Arbitration lost)
Page 868: Function To Detect Loss Of Arbitration During Nack Transmission (Nale Bit)
RX24T Group 26. I C-bus Interface (RIICa) 26.9.2 Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) The RIIC has a function to cause arbitration to be lost if the internal SDA output level does not match the level on the SDA0 line (the high output as the internal SDA output;...
Page 869: Slave Arbitration-Lost Detection (Sale Bit)
RX24T Group 26. I C-bus Interface (RIICa) [Condition for arbitration-lost during NACK transmission]  When the internal SDA output level does not match the SDA0 line (ACK is received) during transmission of NACK (ICMR3.ACKBT bit = 1) 26.9.3 Slave Arbitration-Lost Detection (SALE Bit) The RIIC has a function to cause arbitration to be lost if the data for transmission (i.e.
Page 870: 26.10 Start Condition/Restart Condition/Stop Condition Issuing Function
RX24T Group 26. I C-bus Interface (RIICa) 26.10 Start Condition/Restart Condition/Stop Condition Issuing Function 26.10.1 Issuing a Start Condition The RIIC issues a start condition when the ICCR2.ST bit is set to 1. When the ST bit is set to 1, a start condition issuance request is made and the RIIC issues a start condition when the ICCR2.BBSY flag is 0 (bus free state).
Page 871: Issuing A Stop Condition
RX24T Group 26. I C-bus Interface (RIICa) 26.10.3 Issuing a Stop Condition The RIIC issues a stop condition when the ICCR2.SP bit is set to 1. When the SP bit is set to 1, a stop condition issuance request is made and the RIIC issues a stop condition when the ICCR2.BBSY flag is 1 (bus busy state) and the ICCR2.MST bit is 1 (master mode).
Page 872: 26.11 Bus Hanging
RX24T Group 26. I C-bus Interface (RIICa) 26.11 Bus Hanging If the clock signals from the master and slave devices go out of synchronization due to noise or other factors, the I C-bus might hang with a fixed level on the SCL0 line and/or SDA0 line. As measures against the bus hanging, the RIIC has a timeout function to detect hanging by monitoring the SCL0 line, a function for the output of an extra SCL clock cycle to release the bus from a hung state due to clock signals being out of synchronization, the RIIC reset function, and internal reset function.
Page 873 RX24T Group 26. I C-bus Interface (RIICa) [Timeout function] Start internal Start internal Start internal Start internal Start internal Start internal counter counter counter counter counter counter Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal counter counter counter...
Page 874: Extra Scl Clock Cycle Output Function
RX24T Group 26. I C-bus Interface (RIICa) 26.11.2 Extra SCL Clock Cycle Output Function In master mode, the RIIC module has a facility for the output of extra SCL clock cycles to release the SDA0 line of the slave device from being held at the low level due to the master being out of synchronization with the slave device. This function is mainly used in master mode to release the SDA0 line of the slave device from the state of being fixed to the low level by including extra cycles of SCL output from the RIIC with single cycles of the SCL clock as the unit if the RIIC cannot issue a stop condition because the slave device is holding the SDA0 line at the low level.
Page 875: Riic Reset And Internal Reset
RX24T Group 26. I C-bus Interface (RIICa) 26.11.3 RIIC Reset and Internal Reset The RIIC module incorporates a function for resetting itself. There are two types of reset. One is referred to as an RIIC reset; this initializes all registers including the ICCR2.BBSY flag. The other is referred to as an internal reset; this releases the RIIC from the slave-address matched state and initializes the internal counter while retaining other settings.
Page 876: 26.12 Smbus Operation
RX24T Group 26. I C-bus Interface (RIICa) 26.12 SMBus Operation The RIIC is available for data communication conforming to the SMBus (Version 2.0). To perform SMBus communication, set the ICMR3.SMBS bit to 1. To use the transfer rate within a range of 10 kbps to 100 kbps of the SMBus specification, set the ICMR1.CKS[2:0] bits, the ICBRH register, and the ICBRL register.
Page 877: Packet Error Code (Pec)
RX24T Group 26. I C-bus Interface (RIICa) SMBus specification : Total clock low-level extended period (slave device) LOW:SEXT : Total clock low-level extended period (master device) LOW:MEXT Start Stop LOW:SEXT LOW:MEXT LOW:MEXT LOW:MEXT LOW:MEXT SCL0 Data A/NA 7-bit slave address Data SDA0 BBSY...
Page 878: 26.13 Interrupt Sources
RX24T Group 26. I C-bus Interface (RIICa) 26.13 Interrupt Sources The RIIC issues four types of interrupt request: transfer error or event generation (arbitration-lost, NACK detection, timeout detection, start condition detection, and stop condition detection), receive data full, transmit data empty, and transmit end.
Page 879: 26.14 Resets And Register And Function States When Issuing Each Condition
RX24T Group 26. I C-bus Interface (RIICa) 26.14 Resets and Register and Function States When Issuing Each Condition The RIIC can be reset by MCU reset, RIIC reset, and internal reset functions. Table 26.7 lists the register and function states when issuing each reset or condition. Table 26.7 Register and Function States When Issuing Each Reset or Condition Start Condition/...
Page 880: 26.15 Usage Notes
RX24T Group 26. I C-bus Interface (RIICa) 26.15 Usage Notes 26.15.1 Setting Module Stop Function Module stop state can be entered or released using module stop control register B (MSTPCRB). The initial setting is for operation of the RIIC to be stopped. RIIC register access is enabled by releasing the module stop state. For details on module stop control register B, refer to section 11, Low Power Consumption.
Page 881: Serial Peripheral Interface (Rspib)
RX24T Group 27. Serial Peripheral Interface (RSPIb) Serial Peripheral Interface (RSPIb) In this section, “PCLK” is used to refer to PCLKB. 27.1 Overview This MCU includes one channel of Serial Peripheral Interface (RSPI). The RSPI channels are capable of high-speed, full-duplex synchronous serial communications with multiple processors and peripheral devices.
Page 882 RX24T Group 27. Serial Peripheral Interface (RSPIb) Table 27.1 RSPI Specifications (2/2) Item Description  Interrupt sources Interrupt sources Receive buffer full interrupt Transmit buffer empty interrupt RSPI error interrupt (mode fault, overrun, underrun, or parity error) RSPI idle interrupt (RSPI idle) ...
Page 883 RX24T Group 27. Serial Peripheral Interface (RSPIb) Internal Module data bus peripheral bus SPBR SPRX SPTX SPCR SSLP SPPCR Baud rate PCLK generator SPSR SPDR SPSCR Parity circuit SPSSR SPDCR SPCKD SSLND Shift register SPND SPCR2 SPCMD Selector Transmission/ reception controller Normal Clock Loopback...
Page 884 RX24T Group 27. Serial Peripheral Interface (RSPIb) Table 27.2 lists the I/O pins used in the RSPI. The RSPI automatically switches the I/O direction of the SSLA0 pin. SSLA0 is set as an output when the RSPI is a single master and as an input when the RSPI is a multi-master or a slave.
Page 885: Register Descriptions
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2 Register Descriptions 27.2.1 RSPI Control Register (SPCR) Address(es): RSPI0.SPCR 0008 8380h SPTIE SPEIE MSTR MODF SPRIE TXMD SPMS Value after reset: Symbol Bit Name Description SPMS RSPI Mode Select 0: SPI operation (4-wire method) 1: Clock synchronous operation (3-wire method) TXMD Communications Operating Mode...
Page 886 RX24T Group 27. Serial Peripheral Interface (RSPIb) MODFEN Bit (Mode Fault Error Detection Enable) The MODFEN bit enables or disables the detection of mode fault error (refer to section 27.3.8, Error Detection). In addition, the RSPI determines the I/O direction of the SSLA0 to SSLA3 pins based on combinations of the MODFEN and MSTR bits (refer to section 27.3.2, Controlling RSPI Pins).
Page 887: Rspi Slave Select Polarity Register (Sslp)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.2 RSPI Slave Select Polarity Register (SSLP) Address(es): RSPI0.SSLP 0008 8381h — — — — SSL3P SSL2P SSL1P SSL0P Value after reset: Symbol Bit Name Description SSL0P SSL0 Signal Polarity Setting 0: SSL0 signal is active low 1: SSL0 signal is active high SSL1P SSL1 Signal Polarity Setting...
Page 888: Rspi Pin Control Register (Sppcr)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.3 RSPI Pin Control Register (SPPCR) Address(es): RSPI0.SPPCR 0008 8382h — — MOIFE MOIFV — — SPLP2 SPLP Value after reset: Symbol Bit Name Description SPLP RSPI Loopback 0: Normal mode 1: Loopback mode (data is inverted for transmission) SPLP2 RSPI Loopback 2 0: Normal mode...
Page 889: Rspi Status Register (Spsr)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.4 RSPI Status Register (SPSR) Address(es): RSPI0.SPSR 0008 8383h SPRF — SPTEF UDRF PERF MODF IDLNF OVRF Value after reset: Symbol Bit Name Description OVRF Overrun Error Flag 0: No overrun error occurs R/(W) 1: An overrun error occurs IDLNF...
Page 890 RX24T Group 27. Serial Peripheral Interface (RSPIb)  The following 1 is satisfied (condition 1) or all of the following 2 to 4 are satisfied (condition 2). 1. The SPCR.SPE bit is 0 (disables the RSPI function) 2. The transmit buffer (SPTX) is empty (data for the next transfer is not set) 3.
Page 891 RX24T Group 27. Serial Peripheral Interface (RSPIb) [Setting condition]  When the SPCR.SPE bit is 0 (disables the RSPI function)  When data is transferred from the transmit buffer to the shift register [Clearing condition]  When the number of frames of transmit data specified by the SPDCR.SPFC[1:0] bits is written to the SPDR register The SPDR register can be set only when the SPTEF flag is 1.
Page 892: Rspi Data Register (Spdr)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.5 RSPI Data Register (SPDR) Address(es): RSPI0.SPDR 0008 8384h Value after reset: Value after reset: Address(es): RSPI0.SPDR.H 0008 8384h Value after reset: SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI. When accessing in longwords (the SPLW bit is 1), access SPDR.
Page 893: Bus Interface
RX24T Group 27. Serial Peripheral Interface (RSPIb) Furthermore, if the data length is other than 32 bits, bits not referred to in SPTXn (n = 0 to 3) are stored in the corresponding bits in SPRXn. For example, if the data length is 9 bits, received data are stored in the SPRXn[8:0] bits and the SPTXn[31:9] bits are stored in the SPRXn[31:9] bits.
Page 894 RX24T Group 27. Serial Peripheral Interface (RSPIb) (b) Reading SPDR can be read to read the value of a receive buffer (SPRXn) or a transmit buffer (SPTXn). The setting of the RSPI receive/transmit data select bit in the RSPI data control register (SPDCR.SPRDTD) selects whether reading is of the receive or transmit buffer.
Page 895: Rspi Sequence Control Register (Spscr)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.6 RSPI Sequence Control Register (SPSCR) Address(es): RSPI0.SPSCR 0008 8388h — — — — — SPSLN[2:0] Value after reset: Symbol Bit Name Description b2 to b0 SPSLN[2:0] RSPI Sequence Length b0 Sequence Length Referenced SPCMD0 to SPCMD7 (No.) 0 0 0: 1 0→0→…...
Page 896: Rspi Sequence Status Register (Spssr)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.7 RSPI Sequence Status Register (SPSSR) Address(es): RSPI0.SPSSR 0008 8389h — SPECM[2:0] — SPCP[2:0] Value after reset: Symbol Bit Name Description b2 to b0 SPCP[2:0] RSPI Command Pointer 0 0 0: SPCMD0 0 0 1: SPCMD1 0 1 0: SPCMD2 0 1 1: SPCMD3 1 0 0: SPCMD4...
Page 897: Rspi Bit Rate Register (Spbr)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.8 RSPI Bit Rate Register (SPBR) Address(es): RSPI0.SPBR 0008 838Ah Value after reset: SPBR sets the bit rate in master mode. If the contents of SPBR are changed while both the SPCR.MSTR and SPCR.SPE bits are 1, subsequent operations should not be performed.
Page 898: Rspi Data Control Register (Spdcr)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.9 RSPI Data Control Register (SPDCR) Address(es): RSPI0.SPDCR 0008 838Bh SPLW SPRDT — — — — SPFC[1:0] Value after reset: Symbol Bit Name Description b1, b0 SPFC[1:0] Number of Frames b1 b0 0 0: 1 frame Specification 0 1: 2 frames 1 0: 3 frames...
Page 899 RX24T Group 27. Serial Peripheral Interface (RSPIb) Table 27.4 Settable Combinations of SPSLN[2:0] Bits and SPFC[1:0] Bits Number of Frames in Number of Frames at which Transmit Buffer or Receive Setting SPSLN[2:0] SPFC[1:0] a Single Sequence Buffer Status Becomes “Has Valid Data” 000b 000b 000b...
Page 900: Rspi Clock Delay Register (Spckd)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.10 RSPI Clock Delay Register (SPCKD) Address(es): RSPI0.SPCKD 0008 838Ch — — — — — SCKDL[2:0] Value after reset: Symbol Bit Name Description b2 to b0 SCKDL[2:0] RSPCK Delay Setting 0 0 0: 1 RSPCK 0 0 1: 2 RSPCK 0 1 0: 3 RSPCK 0 1 1: 4 RSPCK...
Page 901: Rspi Slave Select Negation Delay Register (Sslnd)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.11 RSPI Slave Select Negation Delay Register (SSLND) Address(es): RSPI0.SSLND 0008 838Dh — — — — — SLNDL[2:0] Value after reset: Symbol Bit Name Description b2 to b0 SLNDL[2:0] SSL Negation Delay Setting 0 0 0: 1 RSPCK 0 0 1: 2 RSPCK 0 1 0: 3 RSPCK...
Page 902: Rspi Next-Access Delay Register (Spnd)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.12 RSPI Next-Access Delay Register (SPND) Address(es): RSPI0.SPND 0008 838Eh — — — — — SPNDL[2:0] Value after reset: Symbol Bit Name Description b2 to b0 SPNDL[2:0] RSPI Next-Access Delay Setting 0 0 0: 1 RSPCK + 2 PCLK 0 0 1: 2 RSPCK + 2 PCLK 0 1 0: 3 RSPCK + 2 PCLK 0 1 1: 4 RSPCK + 2 PCLK...
Page 903: Rspi Control Register 2 (Spcr2)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.13 RSPI Control Register 2 (SPCR2) Address(es): RSPI0.SPCR2 0008 838Fh SCKAS — — — SPIIE SPOE SPPE Value after reset: Symbol Bit Name Description SPPE Parity Enable 0: Does not add the parity bit to transmit data and does not check the parity bit of receive data 1: Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0)
Page 904 RX24T Group 27. Serial Peripheral Interface (RSPIb) SCKASE Bit (RSPCK Auto-Stop Function Enable) The SCKASE bit enables or disables the RSPCK auto-stop function. When this function is enabled, the RSPCK clock is stopped before an overrun error occurs when data is received in master mode. For details, refer to section 27.3.8.1, Overrun Error .
Page 905: Rspi Command Registers 0 To 7 (Spcmd0 To Spcmd7)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.2.14 RSPI Command Registers 0 to 7 (SPCMD0 to SPCMD7) Address(es): RSPI0.SPCMD0 0008 8390h, RSPI0.SPCMD1 0008 8392h, RSPI0.SPCMD2 0008 8394h, RSPI0.SPCMD3 0008 8396h, RSPI0.SPCMD4 0008 8398h, RSPI0.SPCMD5 0008 839Ah, RSPI0.SPCMD6 0008 839Ch, RSPI0.SPCMD7 0008 839Eh SCKDE SLNDE SPNDE...
Page 906 RX24T Group 27. Serial Peripheral Interface (RSPIb) SPCMDm register is used to set a transfer format for the RSPI in master mode. Each channel has eight RSPI command registers (SPCMD0 to SPCMD7). Some of the bits in SPCMD0 register is used to set a transfer mode for the RSPI in slave mode.
Page 907 RX24T Group 27. Serial Peripheral Interface (RSPIb) SPNDEN Bit (RSPI Next-Access Delay Enable) The SPNDEN bit sets the period from the time the RSPI in master mode terminates a serial transfer and sets the SSLAi signal inactive until the RSPI enables the SSLAi signal assertion for the next access (next-access delay). If the SPNDEN bit is 0, the RSPI sets the next-access delay to 1 RSPCK + 2 PCLK.
Page 908: Operation
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3 Operation In this section, the serial transfer period means a period from the beginning of driving valid data to the fetching of the final valid data. 27.3.1 Overview of RSPI Operations The RSPI is capable of synchronous serial transfers in slave mode (SPI operation), single-master mode (SPI operation), multi-master mode (SPI operation), slave mode (clock synchronous operation), and master mode (clock synchronous operation).
Page 909: Controlling Rspi Pins
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.2 Controlling RSPI Pins According to the MSTR, MODFEN, and SPMS bits in SPCR and the ODRn.Bi bit for I/O ports, the RSPI can switch pin states. Table 27.6 lists the relationship between pin states and bit settings. Setting the ODRn.Bi bit for an I/O port to 0 selects CMOS output;...
Page 910: Rspi System Configuration Examples
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.3 RSPI System Configuration Examples 27.3.3.1 Single Master/Single Slave (with This MCU Acting as Master) Figure 27.5 shows a single-master/single-slave RSPI system configuration example when this MCU is used as a master. In the single-master/single-slave configuration, the SSLA0 to SSLA3 output of this MCU (master) are not used. The SSL input of the SPI slave is fixed to the low level, and the SPI slave is maintained in a select state.
Page 911: Single Master/Single Slave (With This Mcu Acting As Slave)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.3.2 Single Master/Single Slave (with This MCU Acting as Slave) Figure 27.6 shows a single-master/single-slave RSPI system configuration example when this MCU is used as a slave. When this MCU is to operate as a slave, the SSLA0 pin is used as SSL input. The SPI master drives the RSPCK and MOSI.
Page 912: Single Master/Multi-Slave (With This Mcu Acting As Master)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.3.3 Single Master/Multi-Slave (with This MCU Acting as Master) Figure 27.8 shows a single-master/multi-slave RSPI system configuration example when this MCU is used as a master. In the example of Figure 27.8 , the RSPI system is comprised of this MCU (master) and four slaves (SPI slave 0 to SPI slave 3).
Page 913: Single Master/Multi-Slave (With This Mcu Acting As Slave)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.3.4 Single Master/Multi-Slave (with This MCU Acting as Slave) Figure 27.9 shows a single-master/multi-slave RSPI system configuration example when this MCU is used as a slave. In the example of Figure 27.9 , the RSPI system is comprised of an SPI master and two MCUs (slave X and slave Y). The SPCK and MOSI outputs of the SPI master are connected to the RSPCKA and MOSIA inputs of the MCUs (slave X and slave Y).
Page 914: Multi-Master/Multi-Slave (With This Mcu Acting As Master)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.3.5 Multi-Master/Multi-Slave (with This MCU Acting as Master) Figure 27.10 shows a multi-master/multi-slave RSPI system configuration example when this MCU is used as a master. In the example of Figure 27.10 , the RSPI system is comprised of two MCUs (master X and master Y) and two SPI slaves (SPI slave 1 and SPI slave 2).
Page 915: Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) (With This Mcu Acting As Master)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.3.6 Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) (with This MCU Acting as Master) Figure 27.11 shows a master (clock synchronous operation)/slave (clock synchronous operation) RSPI system configuration example when this MCU is used as a master. In the master (clock synchronous operation)/slave (clock synchronous operation) configuration, SSLA0 to SSLA3 of this MCU (master) are not used.
Page 916: Data Format
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.4 Data Format The RSPI’s data format depends on the settings in RSPI command register m (SPCMDm) (m = 0 to 7) and the parity enable bit in RSPI control register 2 (SPCR2.SPPE). Regardless of whether the MSB or LSB is first, the RSPI treats the range from the LSB bit in the RSPI data register (SPDR) to the selected data length as transfer data.
Page 917: When Parity Is Disabled (Spcr2.Sppe = 0)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.4.1 When Parity is Disabled (SPCR2.SPPE = 0) When parity is disabled, data for transmission are copied to the shift register with no prior processing. A description of the connection between the RSPI data register (SPDR) and the shift register in terms of the combination of MSB or LSB first and data length is given below.
Page 918 RX24T Group 27. Serial Peripheral Interface (RSPIb) (2) MSB First Transfer (24-Bit Data) Figure 27.15 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity disabled, 24 bits as the RSPI data length for an example that is not 32 bits, and MSB first selected. In transmission, the lower-order 24 bits (T23 to T00) from the current stage of the transmit buffer are copied to the shift register.
Page 919 RX24T Group 27. Serial Peripheral Interface (RSPIb) (3) LSB First Transfer (32-Bit Data) Figure 27.16 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity disabled, an RSPI data length of 32 bits, and LSB first selected. In transmission, bits T31 to T00 from the current stage of the transmit buffer are reordered bit by bit to obtain the order T00 to T31 for copying to the shift register.
Page 920 RX24T Group 27. Serial Peripheral Interface (RSPIb) (4) LSB First Transfer (24-Bit Data) Figure 27.17 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity disabled, 24 bits as the RSPI data length for an example that is not 32 bits, and LSB first selected. In transmission, the lower-order 24 bits (T23 to T00) from the current stage of the transmit buffer are reordered bit by bit to obtain the order T00 to T23 for copying to the shift register.
Page 921: When Parity Is Enabled (Spcr2.Sppe = 1)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.4.2 When Parity is Enabled (SPCR2.SPPE = 1) When parity is enabled, the lowest-order bit of the data for transmission becomes a parity bit. Hardware calculates the value of the parity bit. (1) MSB First Transfer (32-Bit Data) Figure 27.18 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, an RSPI data length of 32 bits, and MSB first selected.
Page 922 RX24T Group 27. Serial Peripheral Interface (RSPIb) (2) MSB First Transfer (24-Bit Data) Figure 27.19 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, 24 bits as the RSPI data length for an example that is not 32 bits, and MSB first selected. In transmission, the value of the parity bit (P) is calculated from bits T23 to T01.
Page 923 RX24T Group 27. Serial Peripheral Interface (RSPIb) (3) LSB First Transfer (32-Bit Data) Figure 27.20 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, an RSPI data length of 32 bits, and LSB first selected. In transmission, the value of the parity bit (P) is calculated from bits T30 to T00.
Page 924 RX24T Group 27. Serial Peripheral Interface (RSPIb) (4) LSB First Transfer (24-Bit Data) Figure 27.21 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, 24 bits as the RSPI data length for an example that is not 32 bits, and LSB first selected. In transmission, the value of the parity bit (P) is calculated from bits T22 to T00.
Page 925: Transfer Format
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.5 Transfer Format 27.3.5.1 CPHA = 0 Figure 27.22 shows a sample transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 0. Note that clock synchronous operation (the SPCR.SPMS bit is 1) should not performed when the RSPI operates in slave mode (SPCR.MSTR = 0) and the CPHA bit is 0.
Page 926: Cpha = 1
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.5.2 CPHA = 1 Figure 27.23 shows a sample transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 1. However, when the SPCR.SPMS bit is 1, the SSLAi signals are not used, and only the three signals RSPCKA, MOSIA, and MISOA handle communications.
Page 927: Communications Operating Mode
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.6 Communications Operating Mode Full-duplex synchronous serial communications or transmit operations only can be selected by the communications operating mode select bit (SPCR.TXMD). The SPDR access shown in Figure 27.24 and Figure 27.25 indicate the condition of access to the SPDR register, where W denotes a write cycle.
Page 928: Transmit Operations Only (Spcr.txmd = 1)
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.6.2 Transmit Operations Only (SPCR.TXMD = 1) Figure 27.25 shows an example of operation when the communications operating mode select bit (SPCR.TXMD) is set to 1. In the example in Figure 27.25 , the RSPI performs an 8-bit serial transfer in which the SPDCR.SPFC[1:0] bits are 00b, the SPCMDm.CPHA bit is 1, and the SPCMDm.CPOL bit is 0.
Page 929: Transmit Buffer Empty/Receive Buffer Full Interrupts
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.7 Transmit Buffer Empty/Receive Buffer Full Interrupts Figure 27.26 shows an example of operation of the transmit buffer empty interrupt (SPTI) and the receive buffer full interrupt (SPRI). The SPDR register access shown in Figure 27.26 indicates the condition of access to the SPDR register, where W denotes a write cycle, and R a read cycle.
Page 930 RX24T Group 27. Serial Peripheral Interface (RSPIb) (5) When SPDR is read in the receive buffer full interrupt routine or in the receive buffer full detecting process by polling the SPRF flag, the receive data can be read. When the receive data is read, the SPRF flag becomes 0. If transmit data is written to SPDR while the transmit buffer holds data that has not yet been transmitted (the SPTEF flag is 0), the RSPI does not update the data in the transmit buffer.
Page 931: Error Detection
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.8 Error Detection In the normal RSPI serial transfer, the data written to the transmit buffer of SPDR is transmitted, and the received data can be read from the receive buffer of SPDR. If access is made to SPDR, depending on the status of the transmit/receive buffer or the status of the RSPI at the beginning or end of serial transfer, in some cases non-normal transfers can be executed.
Page 932: Overrun Error
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.8.1 Overrun Error If a serial transfer ends when the receive buffer of SPDR is full, the RSPI detects an overrun error, and sets the SPSR.OVRF flag to 1. When the OVRF flag is 1, the RSPI does not copy data from the shift register to the receive buffer so that the data prior to the occurrence of the error is retained in the receive buffer.
Page 933 RX24T Group 27. Serial Peripheral Interface (RSPIb) When the RSPCK auto-stop function is enabled in master mode, an overrun error does not occur. Figure 27.28 and Figure 27.29 show the clock stop waveform when a serial transfer continues while the receive buffer is full in master mode.
Page 934: Parity Error
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.8.2 Parity Error If full-duplex synchronous serial communications is performed with the SPCR.TXMD bit set to 0 and the SPCR2.SPPE bit set to 1, when serial transfer ends, the RSPI checks whether there are parity errors. Upon detecting a parity error in the received data, the RSPI sets the SPSR.PERF flag to 1.
Page 935: Mode Fault Error
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.8.3 Mode Fault Error The RSPI operates in multi-master mode when the SPCR.MSTR bit is 1, the SPCR.SPMS bit is 0, and the SPCR.MODFEN bit is 1. If the active level is input with respect to the SSLA0 input signal of the RSPI in multi-master mode, the RSPI detects a mode fault error irrespective of the status of the serial transfer, and sets the SPSR.MODF flag to 1.
Page 936: Initializing Rspi
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.9 Initializing RSPI If 0 is written to the SPCR.SPE bit or the RSPI sets the SPE bit to 0 because of the detection of a mode fault error or an underrun error, the RSPI disables the RSPI function, and initializes some of the module functions. When a system reset is generated, the RSPI initializes all of the module functions.
Page 937: Spi Operation
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.10 SPI Operation 27.3.10.1 Master Mode Operation The only difference between single-master mode operation and multi-master mode operation lies in mode fault error detection (refer to section 27.3.8, Error Detection ). When operating in single-master mode, the RSPI does not detect mode fault errors whereas the RSPI running in multi-master mode does detect mode fault errors.
Page 938: Sequence Control
RX24T Group 27. Serial Peripheral Interface (RSPIb) (3) Sequence Control The transfer format that is employed in master mode is determined by SPSCR, SPCMDm, SPBR, SPCKD, SSLND, and SPND registers. SPSCR is a register used to determine the sequence configuration for serial transfers that are executed by the RSPI in master mode.
Page 939 RX24T Group 27. Serial Peripheral Interface (RSPIb) Figure 27.33 shows the relationship between the command and the transmit and receive buffers in the sequence of operations specified by the settings in Table 27.4 . SPTX0/SPRX0 Setting 1-1 SPCMD0 Only 1 frame SPTX0/SPRX0 SPTX1/SPRX1 Setting 1-2...
Page 940: Burst Transfer
RX24T Group 27. Serial Peripheral Interface (RSPIb) (4) Burst Transfer If the SPCMDm.SSLKP bit that the RSPI references during the current serial transfer is 1, the RSPI keeps the SSLAi signal level during the serial transfer until the beginning of the SSLAi signal assertion for the next serial transfer. If the SSLAi signal level for the next serial transfer is the same as the SSLAi signal level for the current serial transfer, the RSPI can execute continuous serial transfers while keeping the SSLAi signal assertion status (burst transfer).
Page 941 RX24T Group 27. Serial Peripheral Interface (RSPIb) (5) RSPCK Delay (t1) The RSPCK delay value of the RSPI in master mode depends on the SPCMDm.SCKDEN bit setting and the SPCKD register setting. The RSPI determines the SPCMDm register to be referenced during serial transfer by pointer control, and determines an RSPCK delay value during serial transfer by using the SPCMDm.SCKDEN bit and SPCKD, as listed in Table 27.9 .
Page 942 RX24T Group 27. Serial Peripheral Interface (RSPIb) (7) Next-Access Delay (t3) The next-access delay value of the RSPI in master mode depends on the SPCMDm.SPNDEN bit setting and the SPND setting. The RSPI determines the SPCMDm register to be referenced during serial transfer by pointer control, and determines a next-access delay value during serial transfer by using the SPCMDm.SPNDEN bit and SPND, as listed in Table 27.11 .
Page 943 RX24T Group 27. Serial Peripheral Interface (RSPIb) (8) Initialization Flowchart Figure 27.35 is a flowchart illustrating an example of initialization in SPI operation when the RSPI is used in master mode. For a description of how to set up the interrupt controller and I/O ports, refer to the descriptions given in the individual blocks.
Page 944 RX24T Group 27. Serial Peripheral Interface (RSPIb) (9) Software Processing Flow Figure 27.36 to Figure 27.38 show examples of the flow of software processing. (a) Transmit Processing Flow When transmitting data, the CPU will be notified of the completion of data transmission after the last writing of data for transmission if the SPII interrupt is enabled.
Page 945 RX24T Group 27. Serial Peripheral Interface (RSPIb) (b) Receive Processing Flow The RSPI does not handle receive-only operation, so processing for transmission is required. Pre-transfer processing Processing for reception Start processing End of initial settings for reception SPRI interrupt generated Clear the SPSR.MODF, OVRF, [1] Clear error sources.
Page 946 RX24T Group 27. Serial Peripheral Interface (RSPIb) Flow of Error Processing The RSPI has three types of error. When a mode fault error is generated, the SPCR.SPE bit is automatically cleared, stopping operations for transmission and reception. For errors from other sources, however, the SPCR.SPE bit is not cleared and operations for transmission and reception continue;...
Page 947: Slave Mode Operation
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.10.2 Slave Mode Operation (1) Starting a Serial Transfer If the SPCMD0.CPHA bit is 0, when detecting an SSLA0 input signal assertion, the RSPI needs to start driving valid data to the MISOA output signal. For this reason, when the CPHA bit is 0, the assertion of the SSLA0 input signal triggers the start of a serial transfer.
Page 948 RX24T Group 27. Serial Peripheral Interface (RSPIb) (4) Burst Transfer If the SPCMD0.CPHA bit is 1, continuous serial transfer (burst transfer) can be executed while retaining the assertion state for the SSLA0 input signal. If the CPHA bit is 1, the period from the first RSPCKA edge to the sampling timing for the reception of the final bit in an SSLA0 signal active state corresponds to a serial transfer period.
Page 949 RX24T Group 27. Serial Peripheral Interface (RSPIb) (6) Software Processing Flow Figure 27.40 to Figure 27.42 show examples of the flow of software processing. (a) Transmit Processing Flow Pre-transfer processing Processing for transmission Start processing End of initial settings for transmission SPTI interrupt generated Clear the SPSR.MODF, UDRF, [1] Clear error sources.
Page 950 RX24T Group 27. Serial Peripheral Interface (RSPIb) Flow of Error Processing In slave operation, even when a mode fault error is generated, the SPSR.MODF flag can be cleared regardless of the status of the SSLA0 pin. When interrupts are used and an error occurs, if the ICU.IRn.IR flag for the SPTI or SPRI interrupt request is set to 1, clear the ICU.IRn.IR flag in the error processing routine.
Page 951: Clock Synchronous Operation
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.11 Clock Synchronous Operation Setting the SPCR.SPMS bit to 1 selects clock synchronous operation of the RSPI. In clock synchronous operation, the SSLAi pin is not used, and the three pins of RSPCKA, MOSIA, and MISOA handle communications. The SSLAi pin is available as I/O port pins.
Page 952 RX24T Group 27. Serial Peripheral Interface (RSPIb) Sequence length Determining Loading transfer format settings setting reference command SPSCR Command pointer control SPCMD0 SPCMD1 SPCMD2 SPCMD3 SPCMD4 CPHA SLNDEN SPNDEN SCKDEN CPOL SPCMD5 SSLND SPND SPCKD BRDV[1:0] SPCMD6 SSLA[2:0] SPCMD7 SSLKP SPB[3:0] LSBF Transfer format determiner...
Page 953 RX24T Group 27. Serial Peripheral Interface (RSPIb) Figure 27.45 shows the relationship between the command and the transmit and receive buffers in the sequence of operations specified by the settings in Table 27.4 . SPTX0/SPRX0 Setting 1-1 SPCMD0 Only 1 frame SPTX0/SPRX0 SPTX1/SPRX1 Setting 1-2...
Page 954 RX24T Group 27. Serial Peripheral Interface (RSPIb) (4) Initialization Flowchart Figure 27.46 is a flowchart illustrating an example of initialization in clock synchronous operation when the RSPI is used in master mode. For a description of how to set up the interrupt controller and I/O ports, refer to the descriptions given in the individual blocks.
Page 955: Slave Mode Operation
RX24T Group 27. Serial Peripheral Interface (RSPIb) (5) Flow of Software Processing Software processing during clock-synchronous master operation is the same as that for SPI master operation. For details, refer to section 27.3.10.1 , (9) Software Processing Flow . Note that mode fault errors will not occur. 27.3.11.2 Slave Mode Operation (1) Starting a Serial Transfer...
Page 956 RX24T Group 27. Serial Peripheral Interface (RSPIb) (3) Initialization Flowchart Figure 27.47 is a flowchart illustrating an example of initialization in clock synchronous operation when the RSPI is used in slave mode. For a description of how to set up the interrupt controller and I/O ports, refer to the descriptions given in the individual blocks.
Page 957: Loopback Mode
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.12 Loopback Mode When 1 is written to the SPPCR.SPLP2 bit or SPPCR.SPLP bit, the RSPI shuts off the path between the MISOA pin and the shift register if the SPCR.MSTR bit is 1, and between the MOSIA pin and the shift register if the SPCR.MSTR bit is 0, and connects the input path and output path of the shift register.
Page 958: Self-Diagnosis Of Parity Bit Function
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.13 Self-Diagnosis of Parity Bit Function The parity circuit consists of a parity bit adding unit used for transmit data and an error detecting unit used for received data. In order to detect defects in the parity bit adding unit and error detecting unit of the parity circuit, self-diagnosis is executed for the parity circuit following the flowchart shown in Figure 27.49 .
Page 959: Interrupt Sources
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.3.14 Interrupt Sources The RSPI has interrupt sources of receive buffer full, transmit buffer empty, mode fault, underrun, overrun, parity error, and RSPI idle. In addition, the DTC can be activated by the receive buffer full or transmit buffer empty interrupt to perform data transfer.
Page 960: Usage Notes
RX24T Group 27. Serial Peripheral Interface (RSPIb) 27.4 Usage Notes 27.4.1 Setting Module Stop Function Module stop control register B (MSTPCRB) can be used to enable or disable the RSPI. Immediately after a reset, operation of the RSPI is disabled. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 961: Crc Calculator (Crc)
RX24T Group 28. CRC Calculator (CRC) CRC Calculator (CRC) The CRC (Cyclic Redundancy Check) calculator generates CRC codes. 28.1 Overview Table 28.1 lists the specifications of the CRC calculator, and Figure 28.1 shows a block diagram of the CRC calculator. Table 28.1 CRC Specifications Item...
Page 962: Register Descriptions
RX24T Group 28. CRC Calculator (CRC) 28.2 Register Descriptions 28.2.1 CRC Control Register (CRCCR) Address(es): 0008 8280h DORCL — — — — GPS[1:0] Value after reset: Symbol Bit Name Description b1, b0 GPS[1:0] CRC Generating Polynomial b1 b0 0 0: No calculation is executed. Switching 0 1: 8-bit CRC (X + X + 1)
Page 963: Crc Data Output Register (Crcdor)
RX24T Group 28. CRC Calculator (CRC) 28.2.3 CRC Data Output Register (CRCDOR) Address(es): 0008 8282h Value after reset: CRCDOR is a readable and writable register. Since its initial value is 0000h, rewrite the CRCDOR register to perform calculation using a value other than the initial value.
Page 964: Operation
RX24T Group 28. CRC Calculator (CRC) 28.3 Operation The CRC calculator generates CRC codes for use in LSB first or MSB first transfer. The following shows examples of generating the CRC code for input data (F0h) using the 16-bit CRC generating polynomial (X + 1).
Page 965 RX24T Group 28. CRC Calculator (CRC) 1. 8-bit serial reception (LSB first) CRC code Data Input 2. Write 83h to the CRC control register (CRCCR) CRCCR CRCDOR Clear CRCDOR 3. Write F0h to the CRC data input register (CRCDIR) CRCDIR CRCDOR CRC code generation 4.
Page 966 RX24T Group 28. CRC Calculator (CRC) 1. 8-bit serial reception (MSB first) Data CRC code Input 2. Write 87h to the CRC control register (CRCCR) CRCCR CRCDOR Clear CRCDOR 3. Write F0h to the CRC data input register (CRCDIR) CRCDIR CRCDOR CRC code generation 4.
Page 967: Usage Notes
RX24T Group 28. CRC Calculator (CRC) 28.4 Usage Notes 28.4.1 Module Stop Function Setting Operation of the CRC calculator can be disabled or enabled using the module stop control register B (MSTPCRB). After a reset, the CRC is in the module stop state. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 968: Overview
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 12-Bit A/D Converter (S12ADF) In this section, “PCLK” is used to refer to PCLKB. 29.1 Overview This MCU incorporates three units of a 12-bit successive approximation A/D converter. There are two A/D converter units (units 0 and 1) that can use five channels, and one unit (unit 2) that can use 12 channels.
Page 969 RX24T Group 29. 12-Bit A/D Converter (S12ADF) Table 29.1 Specifications of 12-Bit A/D Converter (1/2) Item Description Number of units Three units (S12AD, S12AD1, and S12AD2) Input channels Five channels for S12AD, five channels for S12AD1, and 12 channels for S12AD2 Extended analog function Internal reference voltage (S12AD2 only) A/D conversion method...
Page 970 RX24T Group 29. 12-Bit A/D Converter (S12ADF) Table 29.1 Specifications of 12-Bit A/D Converter (2/2) Item Description  Channel-dedicated sample-and-hold function (three channels for S12AD1 only) Functions  Input signal amplification function of the programmable gain amplifier (1 channel for S12AD and 3 channels for S12AD1) ...
Page 971 RX24T Group 29. 12-Bit A/D Converter (S12ADF) Table 29.2 Functions of 12-Bit A/D Converter (1/2) Pin Name, Abbreviation Item Unit 0 (S12AD) Unit 1 (S12AD1) Unit 2 (S12AD2) Analog input channels AN000 to AN003, AN100 to AN103, AN200 to AN211, AN016 AN116 internal reference...
Page 972 RX24T Group 29. 12-Bit A/D Converter (S12ADF) Table 29.2 Functions of 12-Bit A/D Converter (2/2) Pin Name, Abbreviation Item Unit 0 (S12AD) Unit 1 (S12AD1) Unit 2 (S12AD2) Conditions for Synchronous Compare match/input capture from MTU9.TGRA, and TRG9AEN TRG9AEN TRG9AEN A/D conversion trigger compare match from MTU9.TGRE.
Page 973 RX24T Group 29. 12-Bit A/D Converter (S12ADF) S12AD Bus interface AVCC0 12-bit D/A A/D data register A/D control register AVSS0 Interrupt signal (S12ADI, GBADI) Comparator Control circuit Synchronous trigger (including decoder) (MTU, TMR) Sample and AN016 hold circuit Asynchronous trigger (ADTRG0#) AN003 AN002...
Page 974 RX24T Group 29. 12-Bit A/D Converter (S12ADF) S12AD1 Bus interface AVCC1 12-bit D/A A/D data register A/D control register AVSS1 Interrupt signal (S12ADI1, GBADI1) Comparator Control circuit Synchronous trigger (including decoder) (MTU, TMR) Sample and AN116 hold circuit Asynchronous trigger (ADTRG1#) AN103 Programmable...
Page 975 RX24T Group 29. 12-Bit A/D Converter (S12ADF) S12AD2 Bus interface AVCC2 12-bit D/A A/D data register A/D control register AVSS2 Interrupt signal (S12ADI2, GBADI2) Comparator Control circuit Synchronous trigger (including decoder) (MTU, TMR) Internal Sample and reference voltage hold circuit Asynchronous trigger AN211 (ADTRG2#)
Page 976 RX24T Group 29. 12-Bit A/D Converter (S12ADF) Table 29.3 Input/Output Pins of 12-Bit A/D Converter Internal Sample & Hold Circuit Unit Pin Name Function for the Pin Unit 0 (S12AD) AN000 Input Analog input pin Incorporated — AN001 Input Analog input pin —...
Page 977: Register Descriptions
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2 Register Descriptions 29.2.1 A/D Data Registers y (ADDRy) A/D Data Duplication Register (ADDBLDR) A/D Data Duplication Register A (ADDBLDRA) A/D Data Duplication Register B (ADDBLDRB) A/D Internal Reference Voltage Data Register (ADOCDR) Address(es): S12AD.ADDR0 0008 9020h, S12AD.ADDR1 0008 9022h, S12AD.ADDR2 0008 9024h, S12AD.ADDR3 0008 9026h, S12AD.ADDR16 0008 9040h, S12AD.ADDBLDR 0008 9018h, S12AD.ADDBLDRA 0008 9084h, S12AD.ADDBLDRB 0008 9086h, S12AD1.ADDR0 0008 9220h,...
Page 978 RX24T Group 29. 12-Bit A/D Converter (S12ADF) (3) When A/D-Converted Value Addition Mode is Selected  Flush-right format (A/D-converted value addition mode and 1-time to 4-time conversion selected) The value added by the A/D-converted value of the same channel is stored in bits 13 to 0. Bits 15 and 14 are read as 0.
Page 979: A/D Self-Diagnosis Data Register (Adrd)
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2.2 A/D Self-Diagnosis Data Register (ADRD) Address(es): S12AD.ADRD 0008 901Eh, S12AD1.ADRD 0008 921Eh, S12AD2.ADRD 0008 941Eh Value after reset: ADRD is a 16-bit read-only register that stores the A/D conversion results based on the 12-bit A/D converter’s self- diagnosis.
Page 980: A/D Control Register (Adcsr)
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2.3 A/D Control Register (ADCSR) Address(es): S12AD.ADCSR 0008 9000h, S12AD1. ADCSR 0008 9200h, S12AD2. ADCSR 0008 9400h TRGE EXTRG DBLE GBADI ADST ADCS[1:0] ADIE — — — DBLANS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 DBLANS[4:0]...
Page 981 RX24T Group 29. 12-Bit A/D Converter (S12ADF) When double trigger mode is selected in group scan mode, double trigger mode operation is performed for group A only and not performed for group B or C. Also, in double trigger mode, the analog inputs of multiple channels and internal reference voltage cannot be selected for group A, but can be selected for groups B and C.
Page 982 RX24T Group 29. 12-Bit A/D Converter (S12ADF) EXTRG Bit (Trigger Select) The EXTRG bit selects the synchronous trigger or the asynchronous trigger as the trigger for starting A/D conversion. In group scan mode, the setting of this bit is valid for the selected trigger of group A. For groups B and C, A/D conversion is started by the selected synchronous trigger regardless of this bit setting.
Page 983 RX24T Group 29. 12-Bit A/D Converter (S12ADF) internal reference voltage is completed, A/D conversion is stopped. The ADCS[1:0] bits should be set while the ADST bit is 0. They should not be set simultaneously when 1 is written to the ADST bit. ADST Bit (A/D Conversion Start) The ADST bit starts or stops A/D conversion process.
Page 984: A/D Channel Select Register A0 (Adansa0)
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2.4 A/D Channel Select Register A0 (ADANSA0) (1) S12AD.ADANSA0 Address(es): 0008 9004h ANSA0 ANSA0 ANSA0 ANSA0 — — — — — — — — — — — — Value after reset: Symbol Bit Name Description ANSA000 A/D Conversion Channel Select...
Page 985 RX24T Group 29. 12-Bit A/D Converter (S12ADF) ANSA0n Bit (n = 00 to 03) (A/D Conversion Channel Select) The ANSA0n bit select analog input channels for A/D conversion from among AN100 to AN103. The channels to be selected and the number of channels can be arbitrarily set. The ANSA000 bit corresponds to AN100 and the ANSA003 bit corresponds to AN103.
Page 986: A/D Channel Select Register A1 (Adansa1)
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2.5 A/D Channel Select Register A1 (ADANSA1) (1) S12AD.ADANSA1 Address(es): 0008 9006h ANSA1 — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description ANSA100 A/D Conversion Channel Select...
Page 987: A/D Channel Select Register B0 (Adansb0)
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2.6 A/D Channel Select Register B0 (ADANSB0) (1) S12AD.ADANSB0 Address(es): 0008 9014h ANSB0 ANSB0 ANSB0 ANSB0 — — — — — — — — — — — — Value after reset: Symbol Bit Name Description ANSB000 A/D Conversion Channel Select...
Page 988 RX24T Group 29. 12-Bit A/D Converter (S12ADF) ANSB0n Bit (n = 00 to 03) (A/D Conversion Channel Select) The ANSB0n bit select analog input channels for A/D conversion from among AN100 to AN103 in group B when group scan mode is selected. The S12AD1.ADANSB0 register is used for group scan mode only; not used for any other modes. The channels specified in group A (the channels corresponding to group A, selected with the S12AD1.ADANSA0 and S12AD1.ADANSA1 registers and the ADCSR.DBLANS[4:0] bits in double trigger mode) should be excluded as the channels to be selected and the number of channels to be set.
Page 989: A/D Channel Select Register B1 (Adansb1)
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2.7 A/D Channel Select Register B1 (ADANSB1) (1) S12AD.ADANSB1 Address(es): 0008 9016h ANSB1 — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description ANSB100 A/D Conversion Channel Select...
Page 990 RX24T Group 29. 12-Bit A/D Converter (S12ADF) (2) S12AD1.ADANSB1 Address(es): 0008 9216h ANSB1 — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description ANSB100 A/D Conversion Channel Select 0: AN116 is not subjected to conversion.
Page 991: A/D Channel Select Register C0 (Adansc0)
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2.8 A/D Channel Select Register C0 (ADANSC0) (1) S12AD.ADANSC0 Address(es): 0008 90D4h ANSC0 ANSC0 ANSC0 ANSC0 — — — — — — — — — — — — Value after reset: Symbol Bit Name Description ANSC000 A/D Conversion Channel Select...
Page 992 RX24T Group 29. 12-Bit A/D Converter (S12ADF) The ANSC000 bit corresponds to AN100 and the ANSC003 bit corresponds to AN103. The ANSC0n bit should be set while the S12AD1.ADCSR.ADST bit is 0. (3) S12AD2.ADANSC0 Address(es): 0008 94D4h ANSC0 ANSC0 ANSC0 ANSC0 ANSC0 ANSC0...
Page 993: A/D Channel Select Register C1 (Adansc1)
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2.9 A/D Channel Select Register C1 (ADANSC1) (1) S12AD.ADANSC1 Address(es): 0008 90D6h ANSC1 — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description ANSC100 A/D Conversion Channel Select...
Page 994: A/D-Converted Value Addition/Average Function Select Register 0 (Adads0)
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2.10 A/D-Converted Value Addition/Average Function Select Register 0 (ADADS0) (1) S12AD.ADADS0 Address(es): 0008 9008h ADS00 ADS00 ADS00 ADS00 — — — — — — — — — — — — Value after reset: Symbol Bit Name Description...
Page 995 RX24T Group 29. 12-Bit A/D Converter (S12ADF) (2) S12AD1.ADADS0 Address(es): 0008 9208h ADS00 ADS00 ADS00 ADS00 — — — — — — — — — — — — Value after reset: Symbol Bit Name Description ADS000 A/D-Converted Value Addition/ 0: A/D-converted value addition/average mode for AN100 Average Channel Select to AN103 is not selected.
Page 996 RX24T Group 29. 12-Bit A/D Converter (S12ADF) (3) S12AD2.ADADS0 Address(es): 0008 9408h ADS01 ADS01 ADS00 ADS00 ADS00 ADS00 ADS00 ADS00 ADS00 ADS00 ADS00 ADS00 — — — — Value after reset: Symbol Bit Name Description ADS000 A/D-Converted Value Addition/ 0: A/D-converted value addition/average mode for AN200 Average Channel Select to AN211 is not selected.
Page 997: A/D-Converted Value Addition/Average Function Select Register 1 (Adads1)
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2.11 A/D-Converted Value Addition/Average Function Select Register 1 (ADADS1) (1) S12AD.ADADS1 Address(es): 0008 900Ah ADS10 — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description...
Page 998 RX24T Group 29. 12-Bit A/D Converter (S12ADF) (2) S12AD1.ADADS1 Address(es): 0008 920Ah ADS10 — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description ADS100 A/D-Converted Value Addition/ 0: A/D-converted value addition/average mode for AN116 Average Channel Select is not selected.
Page 999 RX24T Group 29. 12-Bit A/D Converter (S12ADF) Sequence conversion count 4 times ADS002 ADS006 ADS002 3 times ADS002 ADS006 ADS002 2 times ADS002 ADS006 ADS002 1 time • • • ADS000 ADS001 ADS002 ADS003 ADS004 ADS005 ADS006 ADS007 ADS000 ADS001 ADS002 Conversion in progress Figure 29.4 Scan Conversion Sequence with S12AD2.ADADC.ADC[2:0] = 011b, S12AD2.ADADC.AVEE = 0,...
Page 1000: A/D-Converted Value Addition/Average Count Select Register (Adadc)
RX24T Group 29. 12-Bit A/D Converter (S12ADF) 29.2.12 A/D-Converted Value Addition/Average Count Select Register (ADADC) Address(es): S12AD.ADADC 0008 900Ch, S12AD1.ADADC 0008 920Ch, S12AD2.ADADC 0008 940Ch AVEE — — — — ADC[2:0] Value after reset: Symbol Bit Name Description b2 to b0 ADC[2:0] Addition Count Select 0 0 0: 1-time conversion (no addition;...

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