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Renesas R7F0C806 User Manual

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R7F0C806-809

Single-Chip Microcontrollers

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

The sales of these products are limited for China, Hong Kong, and India.

User's Manual: Hardware

Rev.1.40 Apr 2018

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Summary of Contents for Renesas R7F0C806

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
Page 4: How To Use This Manual
This manual is intended to give users an understanding of the functions described in the Organization below. Organization The R7F0C806-809 manual is separated into two parts: this manual and the software edition (common to the RL78 family). R7F0C806-809 RL78 Family User’s Manual...
Page 5 All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.
Page 6: Table Of Contents
1.1 Features ............................1 1.2 List of Part Numbers ........................3 1.3 Pin Configuration (Top View) ......................4 1.3.1 R7F0C806 and R7F0C807 products ....................4 1.3.2 R7F0C808 and R7F0C809 products ....................4 1.4 Pin Identification ..........................5 1.5 Block Diagram ..........................6 1.5.1 R7F0C806 and R7F0C807 products ....................
Page 7 CHAPTER 4 PORT FUNCTIONS ......................58 4.1 Port Functions ..........................58 4.2 Port Configuration ........................58 4.2.1 Port configuration of R7F0C806 and R7F0C807 products ............... 58 4.2.2 Port configuration of R7F0C808 and R7F0C809 products ............... 60 4.3 Registers Controlling Port Function ..................62 4.3.1 Port mode registers 0, 1, 4 (PM0, PM1, PM4) ..................
Page 8 4.6.5 Register settings ..........................85 4.7 Cautions When Using Port Function ..................86 4.7.1 Cautions on 1-bit manipulation instruction for port register n (Pn) ............ 86 4.7.2 Notes on specifying the pin settings ....................87 CHAPTER 5 CLOCK GENERATOR ...................... 88 5.1 Functions of Clock Generator .....................
Page 9 6.3.13 Input switch control register (ISC) ....................130 6.3.14 Timer I/O control register (TIOSC) ....................131 6.3.15 Registers controlling port functions of pins to be used for timer I/O ..........132 6.4 Basic Rules of Timer Array Unit ....................133 6.4.1 Basic rules of simultaneous channel operation function ..............
Page 10 7.3.3 Interval timer control register (ITMCH, ITMCL) ................224 7.4 12-bit Interval Timer Operation ....................225 7.4.1 12-bit interval timer operation timing ....................225 7.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from HALT/STOP mode .......................... 226 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ..........
Page 11 10.8 How to Read A/D Converter Characteristics Table ............... 254 10.8.1 Resolution ............................ 254 10.8.2 Overall error ..........................254 10.8.3 Quantization error ......................... 254 10.8.4 Zero-scale error ..........................255 10.8.5 Full-scale error ..........................255 10.8.6 Integral linearity error ........................255 10.8.7 Differential linearity error ......................
Page 12 11.6.3 Calculating baud rate ........................367 11.6.4 Procedure for processing errors that occurred during UART (UART0) communication ....371 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) ....372 12.1 Functions of Real-Time Output Controller................372 12.2 Configuration of Real-Time Output Controller ..............373 12.3 Registers Controlling Real-Time Output Controller .............
Page 13 12.6.1 Overview ............................385 12.6.2 Timing of controlling three-phase BLDC motors ................386 12.6.3 Flowchart of real-time output initialization..................387 12.6.4 Register setting example ......................388 12.7 Example of Controlling Stepper Motors ................. 389 12.7.1 Overview ............................389 12.7.2 Hardware connection example ..................... 389 12.7.3 Controlling the stepper motors .....................
Page 14 CHAPTER 15 STANDBY FUNCTION ....................418 15.1 Overview ............................ 418 15.2 Standby Function Operation ....................419 15.2.1 HALT mode ..........................419 15.2.2 STOP mode ..........................421 CHAPTER 16 RESET FUNCTION ......................424 16.1 Timing of Reset Operation ...................... 426 16.2 Operation States During Reset Periods ................. 428 16.3 Register for Confirming Reset Source ...................
Page 15 23.2 Oscillator Characteristics ......................480 23.2.1 On-chip oscillator characteristics ....................480 23.3 DC Characteristics ........................481 23.3.1 Pin characteristics of R7F0C806 and R7F0C807 ................. 481 23.3.2 Pin characteristics of R7F0C808 and R7F0C809 ................. 482 23.3.3 Common items ..........................484 23.3.4 Supply current characteristics ...................... 485 23.4 AC Characteristics ........................
Page 16 23.6.4 Data retention power supply voltage characteristics ..............493 23.7 Flash Memory Programming Characteristics ................ 494 23.8 Dedicated Flash Memory Programmer Communication (UART) ......... 494 23.9 Timing of Entry to Flash Memory Programming Modes ............495 CHAPTER 24 PACKAGE DRAWINGS ....................496 24.1 20-Pin Products ........................
Page 17: Chapter 1 Outline
1 channel ● Watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator) ● Real-time output function: 8 channels (R7F0C806 and R7F0C807 only) A/D converter ● 8/10-bit resolution A/D converter (V = 2.4 to 5.5 V) ● Analog input: 8 channels R01UH0481EJ0140 Rev.1.40...
Page 18 ● On-chip key interrupt function ● On-chip clock output/buzzer output controller Others ● On-chip BCD (binary-coded decimal) correction circuit <R> ROM, RAM capacities Flash ROM 20 Pins R7F0C806, R7F0C807 R7F0C808, R7F0C809 8 KB 1 KB R7F0C80762ESP-C R7F0C80962ESP-C R7F0C80762ESN-C R7F0C80962ESN-C 4 KB...
Page 19: List Of Part Numbers
(7.5 × 12.8 mm, 1.27 mm pitch) R7F0C80662ESN-C#HA0,R7F0C80862ESN-C#HA0 Caution The part number represents the number at the time of publication. Be sure to review the latest part number through the target product page in the Renesas Electronics Corp. website. R01UH0481EJ0140 Rev.1.40...
Page 20: Pin Configuration (Top View)
R7F0C806-809 CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 R7F0C806 and R7F0C807 products ● 20-pin plastic SSOP (4.4 × 6.5 mm, 0.65 mm pitch) ● 20-pin plastic SOP (7.5 × 12.8 mm, 1.27 mm pitch) <R> P125/KR1/RESET P40/KR0/TOOL0/(PCLBUZ0)/(TI01/TO01) P137/TI00/INTP0...
Page 21: Pin Identification
R7F0C806-809 CHAPTER 1 OUTLINE 1.4 Pin Identification ANI0 to ANI7 : Analog input INTP0 to INTP5 : External interrupt input KR0 to KR7 : Key return P00 to P07 : Port 0 P10 to P16 : Port 1 : Port 4...
Page 22: Block Diagram
R7F0C806-809 CHAPTER 1 OUTLINE 1.5 Block Diagram 1.5.1 R7F0C806 and R7F0C807 products TAU (4 ch) Port 0 P00 to P07 ch00 TI00 / TO00 Port 1 P10 to P16 TI01 / TO01 ch01 Port 4 TI02 / TO02 ch02 Port 12...
Page 23: R7F0C808 And R7F0C809 Products
R7F0C806-809 CHAPTER 1 OUTLINE 1.5.2 R7F0C808 and R7F0C809 products TAU (4 ch) Port 0 P00 to P07 ch00 TI00 / TO00 P10 to P16 Port 1 TI01 / TO01 ch01 Port 4 TI02 / TO02 ch02 Port 12 P125 ch03...
Page 24: Outline Of Functions
R7F0C806-809 CHAPTER 1 OUTLINE 1.6 Outline of Functions This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 20-pin R7F0C806, R7F0C807 Products R7F0C808, R7F0C809 Products R7F0C80662ESP R7F0C80762ESP R7F0C80862ESP R7F0C80962ESP R7F0C80662ESN...
Page 25 R7F0C806-809 CHAPTER 1 OUTLINE (2/2) Item 20-pin R7F0C806, R7F0C807 Products R7F0C808, R7F0C809 Products R7F0C80662ESP R7F0C80762ESP R7F0C80862ESP R7F0C80962ESP R7F0C80662ESN R7F0C80762ESN R7F0C80862ESN R7F0C80962ESN <R> Reset ● Reset by RESET pin ● Internal reset by watchdog timer ● Internal reset by selectable power-on-reset ●...
Page 26: Chapter 2 Pin Functions
R7F0C806-809 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Port Functions The input or output, buffer, and pull-up resistor settings are also valid for the alternate functions. 2.1.1 R7F0C806 and R7F0C807 products Function Pin Type After Reset Alternate Function...
Page 27: R7F0C808 And R7F0C809 Products
R7F0C806-809 CHAPTER 2 PIN FUNCTIONS 2.1.2 R7F0C808 and R7F0C809 products Function Pin Type After Reset Alternate Function Function Name Release 7-1-9 Input port INTP5/(KR0)/(SCK00) Port 0. 8-bit I/O port. INTP4/(SO00)/(TXD0) Input/output can be specified in 1-bit units. – Use of an on-chip pull-up resistor can be specified –...
Page 28: Functions Other Than Port Pins
R7F0C806-809 CHAPTER 2 PIN FUNCTIONS 2.2 Functions Other than Port Pins 2.2.1 Functions for each product Function R7F0C806 R7F0C808 Function R7F0C806 R7F0C808 Name R7F0C807 R7F0C809 Name R7F0C807 R7F0C809 ANI0 √ √ RXD0 √ √ ANI1 √ √ TXD0 √ √...
Page 29: Description Of Functions
R7F0C806-809 CHAPTER 2 PIN FUNCTIONS 2.2.2 Description of functions Function Name Functions ANI0 to ANI7 Input Analog input pins of A/D converter (See Figure 10-21 Analog Input Pin Connection.) INTP0 to INTP5 Input External interrupt request input Specified available edge: Rising edge, falling edge, or both rising and falling edges...
Page 30: Connection Of Unused Pins
R7F0C806-809 CHAPTER 2 PIN FUNCTIONS 2.3 Connection of Unused Pins Table 2-2 shows the connections of unused pins. Remark The pins mounted depend on the product. See 1.3 Pin Configuration (Top View) and 2.1 Port Functions. Table 2-2. Connection of Unused Pins...
Page 31: Block Diagrams Of Pins
CHAPTER 2 PIN FUNCTIONS 2.4 Block Diagrams of Pins Figures 2-1 to 2-7 show the block diagrams of the pins described in 2.1.1 R7F0C806 and R7F0C807 products and 2.1.2 R7F0C808 and R7F0C809 products. Figure 2-1. Pin Block Diagram for Pin Type 2-1-2...
Page 32 R7F0C806-809 CHAPTER 2 PIN FUNCTIONS Figure 2-2. Pin Block Diagram for Pin Type 3-1-1 PU register P-ch (PUmn) Alternate function RESET PORTSELB Remark For alternate functions, see 2.1 Port Functions. R01UH0481EJ0140 Rev.1.40 Apr 10, 2018...
Page 33 R7F0C806-809 CHAPTER 2 PIN FUNCTIONS Figure 2-3. Pin Block Diagram for Pin Type 7-1-1 PU register P-ch (PUmn) Alternate function PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU ) Remarks 1. For alternate functions, see 2.1 Port Functions.
Page 34 R7F0C806-809 CHAPTER 2 PIN FUNCTIONS Figure 2-4. Pin Block Diagram for Pin Type 7-1-2 PU register P-ch (PUmn) Alternate function PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) POM register (POMmn) Alternate function (SAU) Alternate function (other than SAU ) Caution The input buffer is enabled even if the type 7-1-2 pin is operating as an output when the N-ch open drain output mode is selected by the corresponding bit in the port output mode register (POMx).
Page 35 R7F0C806-809 CHAPTER 2 PIN FUNCTIONS Figure 2-5. Pin Block Diagram for Pin Type 7-1-9 PU register P-ch (PUmn) Alternate function PORT Output latch (Pmn) P-ch PM register N-ch (PMmn) POM register (POMmn) Alternate function (SAU) Alternate function (other than SAU) Remarks 1.
Page 36 R7F0C806-809 CHAPTER 2 PIN FUNCTIONS Figure 2-6. Pin Block Diagram for Pin Type 7-3-1 PU register (PUmn) P-ch PMC register (PMCmn) Alternate function PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU )
Page 37 R7F0C806-809 CHAPTER 2 PIN FUNCTIONS Figure 2-7. Pin Block Diagram for Pin Type 7-3-2 PU register (PUmn) P-ch PMC register (PMCmn) Alternate function PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) POM register (POMmn) Alternate function (SAU) Alternate function...
Page 38 R7F0C806-809 CHAPTER 2 PIN FUNCTIONS Figure 2-8. Pin Block Diagram for Pin Type 19-1-1 PU register P-ch (PUmn) Alternate function PORT Output latch (Pmn) P-ch PM register N-ch (PMmn) Alternate function (SAU) Alternate function (other than SAU) PD register N-ch...
Page 39 R7F0C806-809 CHAPTER 2 PIN FUNCTIONS Figure 2-9. Pin Block Diagram for Pin Type 19-3-1 PU register (PUmn) P-ch PMC register (PMCmn) Alternate function PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) POM register (POMmn) Alternate function (SAU) Alternate function...
Page 40: Chapter 3 Cpu Architecture
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE R7F0C806-809 have the RL78-S1 core. The features of the RL78-S1 core are as follows. ● CISC architecture with 3-stage pipeline ● Address space: 1 MB ● General-purpose register: 8-bit register × 8 ●...
Page 41: Memory Space
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the R7F0C806-809 can access a 1 MB address space. Figures 3-1 and 3-2 show the memory maps. Figure 3-1. Memory Map for the R7F0C806 and R7F0C808 00FFFH FFFFFH Special function register (SFR)
Page 42 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map for the R7F0C807 and R7F0C809 01FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 8 bytes FFEF8H FFEF7H Reserved FFEE0H FFEDFH 1 KB FFAE0H Program area FFADFH Reserved...
Page 43: Internal Program Memory Space
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The R7F0C806-809 products incorporate internal ROM (flash memory), as shown below. Table 3-1. Internal ROM Capacity Part Number Internal ROM...
Page 44 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area of 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is 2 bytes).
Page 45: Mirror Area
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Mirror area The products with 4/8 KB flash memory mirror the code flash area of 00000H to 00FFFH/01FFFH to the area of F8000H to F8FFFH/F9FFFH. By reading data from F8000H to F8FFFH/F9FFFH, an instruction that does not have the ES register as an operand can be used, and thus the contents of the code flash can be read with the shorter code.
Page 46: Internal Data Memory Space
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space The R7F0C806-809 products incorporate the following RAMs. Table 3-3. Internal RAM Capacity Part Number Internal RAM R7F0C806, R7F0C808 512 bytes (FFCE0H to FFEDFH) R7F0C807, R7F0C809 1 KB (FFAE0H to FFEDFH) The internal RAM can be used as a data area and a program area where instructions are fetched (it is prohibited to use the general-purpose register area for fetching instructions).
Page 47: Data Memory Addressing
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the R7F0C806-809, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are available for use.
Page 48: Processor Registers
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The R7F0C806-809 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
Page 49 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE (d) In-service priority flags (ISP1, ISP0) These flags manage the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PR00L, PR00H, PR10L, PR10H, PR01L, PR11L) (see 13.3.3 Priority specification flag registers (PR00L, PR00H, PR10L,...
Page 50: General-Purpose Registers
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers are a bank of eight 8-bit registers (X, A, C, B, E, D, L, and H) mapped to addresses (FFEF8H to FFEFFH) of the data memory. Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 51: And Cs Registers
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register and CS register are used to specify the higher address for data access and when a branch instruction is executed (register direct addressing), respectively. The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Page 52: Special Function Registers (Sfrs)
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
Page 53 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE Table 3-4. SFR List (1/2) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit FFF00H Port register 0 √ √ FFF01H Port register 1 √ √ FFF04H Port register 4 √...
Page 54 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE Table 3-4. SFR List (2/2) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit FFFA5H Clock output select register 0 CKS0 √ √ Note 1 FFFA8H Reset control flag register RESF –...
Page 55: Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area.
Page 56 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Extended SFR (2nd SFR) List (1/2) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit F0010H A/D converter mode register 2 ADM2 √ √ F0030H Pull-up resistor option register 0 √...
Page 57 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Extended SFR (2nd SFR) List (2/2) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit F0184H Timer counter register 02L TCR02L – √ F0185H Timer counter register 02H TCR02H –...
Page 58: Instruction Address Addressing
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: –128 to +127 or –32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination.
Page 59: Register Direct Addressing
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address.
Page 60: Addressing For Processing Data Addresses
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word.
Page 61: Direct Addressing
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description !addr16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable: automatically...
Page 62: Short Direct Addressing
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. Note that it is prohibited to use the area from FFEE0H to FFEF7H. In the products with 128 bytes of RAM, it is also prohibited to use the area from FFE20H to FFE5FH.
Page 63: Sfr Addressing
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format]...
Page 64: Register Indirect Addressing
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description – [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) –...
Page 65: Based Addressing
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
Page 66 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE Figure 3-24. Example of [HL + byte], [DE + byte] [HL + byte], [DE + byte] <1> <2> <1> <2> FFFFFH Instruction code Target OP-code Target memory <2> array Offset of data <2> byte <1>...
Page 67 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE Figure 3-27. Example of ES:[HL + byte], ES:[DE + byte] ES: [HL + byte] ES: [DE + byte] <1> <2> <3> <1> <2> <3> XFFFFH Instruction code <2> <3> Target memory Target OP-code array Offset...
Page 68 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE Figure 3-29. Example of ES:word[BC] ES: word [BC] <1> <2> <3> XFFFFH Array of Instruction code Target memory <3> word-sized <3> Offset data OP-code rp(BC) <2> Low Addr. Address of a word within an array <2>...
Page 69: Based Indexed Addressing
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address.
Page 70: Stack Addressing
R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) values. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request.
Page 71 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE Figure 3-33. Example of POP POP rp <1> <2> SP + 2 <1> SP +1 (SP+1) Stack Instruction code area (SP) <2> OP-code F0000H Stack addressing is specified <1>. The contents of addresses SP and SP + 1 are stored in the lower-order and higher-order bytes of the pair of registers indicated by rp <2>, respectively.
Page 72 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE Figure 3-35. Example of RET <1> SP+4 <1> SP+3 (SP+3) Instruction code Stack SP+2 (SP+2) OP-code area (SP+1) SP+1 <3> (SP) <2> F0000H Stack addressing is specified <1>. The contents of addresses SP, SP + 1, and SP + 2 are stored in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>.
Page 73 R7F0C806-809 CHAPTER 3 CPU ARCHITECTURE Figure 3-37. Example of RETI, RETB RETI, RETB <1> SP+4 <1> (SP+3) SP+3 Instruction code (SP+2) SP+2 Stack OP-code (SP+1) area SP+1 <3> (SP) <2> F0000H Stack addressing is specified <1>. Memory The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively <2>.
Page 74: Chapter 4 Port Functions
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS. 4.2 Port Configuration 4.2.1 Port configuration of R7F0C806 and R7F0C807 products Ports include the following hardware. Table 4-1. Port Configuration (R7F0C806, R7F0C807)
Page 75 R7F0C806-809 CHAPTER 4 PORT FUNCTIONS (1) Port 0 Port 0 is an I/O port with output latches. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P07 pins are used as input pins, use of the on-chip pull-up resistors can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Page 76: Port Configuration Of R7F0C808 And R7F0C809 Products
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port configuration of R7F0C808 and R7F0C809 products Ports include the following hardware. Table 4-2. Port Configuration (R7F0C808, R7F0C809) Item Configuration Control registers Port mode registers 0, 1, 4 (PM0, PM1,PM4) Port registers 0, 1, 4, 12, 13 (P0, P1, P4, P12, P13)
Page 77 R7F0C806-809 CHAPTER 4 PORT FUNCTIONS (4) Port 12 Port 12 is an input-only port. Use of an on-chip pull-up resistor can be specified for P125 using pull-up resistor option register 12 (PU12) (the on-chip pull-up resistor is always valid when RESET input is selected (PORTSELB = 1)).
Page 78: Registers Controlling Port Function
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers. ● Port mode registers 0, 1, 4 (PM0, PM1, PM4) ● Port registers 0, 1, 4, 12, 13 (P0, P1, P4, P12, P13) ●...
Page 79: Port Mode Registers 0, 1, 4 (Pm0, Pm1, Pm4)
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.3.1 Port mode registers 0, 1, 4 (PM0, PM1, PM4) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 80: Port Registers 0, 1, 4, 12, 13 (P0, P1, P4, P12, P13)
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.3.2 Port registers 0, 1, 4, 12, 13 (P0, P1, P4, P12, P13) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is...
Page 81: Pull-Up Resistor Option Registers 0, 1, 4, 12 (Pu0, Pu1, Pu4, Pu12)
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.3.3 Pull-up resistor option registers 0, 1, 4, 12 (PU0, PU1, PU4, PU12) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits that satisfy the following three conditions for the pins to which the use of an on-chip pull- up resistor has been specified in these registers.
Page 82: Pull-Down Resistor Option Registers 0, 1 (Pd0, Pd1) (R7F0C808 And R7F0C809 Only)
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.3.4 Pull-down resistor option registers 0, 1 (PD0, PD1) (R7F0C808 and R7F0C809 only) These registers specify whether the on-chip pull-down resistors are to be used or not. On-chip pull-down resistors can be used in 1-bit units only for the bits that satisfy the following three conditions for the pins to which the use of an on-chip pull-down resistor has been specified in these registers.
Page 83: Port Output Mode Registers 0, 1 (Pom0, Pom1)
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.3.5 Port output mode registers 0, 1 (POM0, POM1) This register sets CMOS output/N-ch open drain output or CMOS output/P-ch open drain output in 1-bit units. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 84: Port Mode Control Registers 0, 1 (Pmc0, Pmc1)
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.3.6 Port mode control registers 0, 1 (PMC0, PMC1) This register sets the digital I/O or analog input in 1-bit units. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH.
Page 85: Peripheral I/O Redirection Register (Pior)
TI01/TO01 PIOR0 PCLBUZ0 Notes 1. R7F0C806 and R7F0C807 products only. 2. R7F0C808 and R7F0C809 products only. Cautions 1. It is prohibited to set PIOR0 and PIOR1 to 1 at the same time. 2. It is prohibited to set PIOR3 and PIOR4 to 1 at the same time.
Page 86: Port Function Operations
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 87: Register Settings When An Alternate Function Is Used
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.5 Register Settings When an Alternate Function Is Used 4.5.1 Basic concepts on using an alternate function If a given pin is also used alternately for analog input, first in the port mode control register 0 (PMC0) specify whether the pin is to be used in analog input or digital output.
Page 88: Register Settings For Alternate Functions That Do Not Use An Output Function
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.5.2 Register settings for alternate functions that do not use an output function If the output from an alternate function associated with a pin is not used, the settings described below must be specified. If the pin is subject to a peripheral I/O redirect function, the output can be changed to another pin by setting the peripheral I/O redirection register (PIOR).
Page 89 R7F0C806-809 CHAPTER 4 PORT FUNCTIONS Table 4-5. Examples of Register And Output Latch Settings With Pin Functions (R7F0C806, R7F0C807) (1/4) Function PIOR POMz PMCz Alternate Function Output Name SAU Output Non-SAU Function Input – – – × – × Output –...
Page 90 R7F0C806-809 CHAPTER 4 PORT FUNCTIONS Table 4-5. Examples of Register And Output Latch Settings With Pin Functions (R7F0C806, R7F0C807) (2/4) Function PIOR POMz PMCz Alternate Function Output Name SAU Output Non-SAU Function Input – × – × × × Output –...
Page 91 R7F0C806-809 CHAPTER 4 PORT FUNCTIONS Table 4-5. Examples of Register And Output Latch Settings With Pin Functions (R7F0C806, R7F0C807) (3/4) Function PIOR POMz PMCz Alternate Function Output Name SAU Output Non-SAU Function Input – – × – × Output –...
Page 92 R7F0C806-809 CHAPTER 4 PORT FUNCTIONS Table 4-5. Examples of Register And Output Latch Settings With Pin Functions (R7F0C806, R7F0C807) (4/4) Function PIOR POMz PMCz Alternate Function Output Name SAU Output Non-SAU Function Input – – – × – × ×...
Page 93 R7F0C806-809 CHAPTER 4 PORT FUNCTIONS Table 4-6. Examples of Register And Output Latch Settings With Pin Functions (R7F0C808, R7F0C809) (1/4) Function PIOR POMz PMCz Alternate Function Output Name SAU Output Non-SAU Function Input – × – × – × –...
Page 94 R7F0C806-809 CHAPTER 4 PORT FUNCTIONS Table 4-6. Examples of Register And Output Latch Settings With Pin Functions (R7F0C808, R7F0C809) (2/4) Function PIOR POMz PMCz Alternate Function Output Name SAU Output Non-SAU Function Input – × – × × – Output –...
Page 95 R7F0C806-809 CHAPTER 4 PORT FUNCTIONS Table 4-6. Examples of Register And Output Latch Settings With Pin Functions (R7F0C808, R7F0C809) (3/4) Function PIOR POMz PMCz Alternate Function Output Name SAU Output Non-SAU Function Input – × × – × Output –...
Page 96 R7F0C806-809 CHAPTER 4 PORT FUNCTIONS Table 4-6. Examples of Register And Output Latch Settings With Pin Functions (R7F0C808, R7F0C809) (4/4) Function PIOR POMz PMCz Alternate Function Output Name SAU Output Non-SAU Function Input – – – × – – ×...
Page 97: 8-Seg Led Control Example (R7F0C808 And R7F0C809 Only)
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.6 8-Seg LED Control Example (R7F0C808 and R7F0C809 Only) 4.6.1 Overview This chapter describes how a 6-digit 8-segment LED is controlled via a port, by using an example. For details about 8- segment LED control, refer to the application note.
Page 98: Port Output Timing
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS Table 4-7. Pins Used and Their Features (R7F0C808 and R7F0C809 Only) Pin Name Function Output COM output 1 Output COM output 2 Output COM output 3 Output COM output 4 Output COM output 5 Output...
Page 99: Flowcharts
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.6.4 Flowcharts Figures 4-11 and 4-12 show the flowchart for a program when using INTTM00 as the interval timer. (1) Main function Figure 4-11. Flowchart of main Function Processing Start Initialize Set up the interval timer.
Page 100 R7F0C806-809 CHAPTER 4 PORT FUNCTIONS (2) INTTM00 interrupt processing Figure 4-12. Flowchart of INTTM00 Interrupt Processing INTTM00 interrupt entry point INTTM00 interrupt count value + 1 INTTM00 interrupt count value > 5? INTTM00 interrupt count value = 0 Return R01UH0481EJ0140 Rev.1.40...
Page 101: Register Settings
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.6.5 Register settings The following describes the settings for the ports that control the LED. After setting these registers, the LED lights to indicate a number corresponding to the P15 to P10 and P07 to P00 pins.
Page 102: Cautions When Using Port Function
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.7 Cautions When Using Port Function 4.7.1 Cautions on 1-bit manipulation instruction for port register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Page 103: Notes On Specifying The Pin Settings
R7F0C806-809 CHAPTER 4 PORT FUNCTIONS 4.7.2 Notes on specifying the pin settings For an output pin to which multiple alternate functions are assigned, the output of the unused alternate functions must be set to its initial state so as to prevent conflicting outputs. This also applies to the functions assigned by using the peripheral I/O redirection register (PIOR).
Page 104: Chapter 5 Clock Generator
R7F0C806-809 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable.
Page 105: Configuration Of Clock Generator
R7F0C806-809 CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Peripheral enable register 0 (PER0) High-speed on-chip oscillator frequency selection register (HOCODIV) Operation speed mode control register (OSMC)
Page 106 R7F0C806-809 CHAPTER 5 CLOCK GENERATOR R01UH0481EJ0140 Rev.1.40 Apr 10, 2018...
Page 107: Registers Controlling Clock Generator
R7F0C806-809 CHAPTER 5 CLOCK GENERATOR Remark f High-speed on-chip oscillator clock frequency : Main system clock frequency MAIN CPU/peripheral hardware clock frequency Low-speed on-chip oscillator clock frequency 5.3 Registers Controlling Clock Generator The following registers are used to control the clock generator.
Page 108: Peripheral Enable Register 0 (Per0)
● SFR used by the A/D converter can be read and written. Note R7F0C806 and R7F0C807 products only. Caution Be sure to clear the following bits to 0. R7F0C806 and R7F0C807 products: Bits 1, 3, and 4 R7F0C808 and R7F0C809 products: Bits 1, 3, 4, and 6 R01UH0481EJ0140 Rev.1.40...
Page 109: Operation Speed Mode Control Register (Osmc)
Note R7F0C806 and R7F0C807 products only. Caution Be sure to clear the following bits to 0. R7F0C806 and R7F0C807 products: Bits 1, 3, and 4 R7F0C808 and R7F0C809 products: Bits 1, 3, 4, and 6 5.3.2 Operation speed mode control register (OSMC) The OSMC register can be used to control supply of the operation clock for the 12-bit interval timer.
Page 110: High-Speed On-Chip Oscillator Frequency Selection Register (Hocodiv)
R7F0C806-809 CHAPTER 5 CLOCK GENERATOR 5.3.3 High-speed on-chip oscillator frequency selection register (HOCODIV) This register is used to change the frequency of the high-speed on-chip oscillator clock set with the option byte (000C2H). HOCODIV can be set by an 8-bit memory manipulation instruction.
Page 111: System Clock Oscillator
5.4 System Clock Oscillator 5.4.1 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the R7F0C806-809. The frequency can be selected from among 20, 10, 5, 2.5, or 1.25 MHz by using the option byte (000C2H). The high-speed on-chip oscillator automatically starts oscillating after reset release.
Page 112: Clock Generator Operation
R7F0C806-809 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1). ● Main system clock f MAIN - High-speed on-chip oscillator clock f ●...
Page 113: Controlling Clock
R7F0C806-809 CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected by using FRQSEL0 to FRQSEL2 of the option byte (000C2H).
Page 114: Cpu Clock Status Transition Diagram
R7F0C806-809 CHAPTER 5 CLOCK GENERATOR 5.6.2 CPU clock status transition diagram Figure 5-6 shows the CPU clock status transition diagram of this product. Figure 5-6. CPU Clock Status Transition Diagram Power ON High-speed on-chip oscillator: Woken up being greater than the detection voltage for the SPOR circuit and release from the reset state due to any reset source.
Page 115: Chapter 6 Timer Array Unit
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The number of units or channels of the timer array unit is four channels. The timer array unit has four 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used in combination to create a high-accuracy timer.
Page 116 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT For details about each function, see the table below. Independent Channel Operation Function Simultaneous Channel Operation Function ● One-shot pulse output (→ see 6.9.1) ● Interval timer (→ see 6.8.1) ● Square wave output (→ see 6.8.1) ●...
Page 117: Functions Of Timer Array Unit
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.1 Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels.
Page 118 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT (6) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TI0n), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
Page 119: Simultaneous Channel Operation Function
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.1.2 Simultaneous channel operation function By using the combination of a master channel (a reference timer mainly controlling the cycle) and a slave channel (a timer operating according to the master channel), channels can be used for the following purposes.
Page 120 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT (3) PWM (Pulse Width Modulation) output function Two channels are used as a set to generate a pulse with a specified period and a specified duty factor. Compare operation Operation clock Interrupt request signal...
Page 121: 8-Bit Timer Operation Function (Channels 1 And 3 Only)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.1.3 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer in a configuration consisting of two 8-bit timers (higher and lower).
Page 122: Configuration Of Timer Array Unit
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Configuration Timer/counter Timer counter register 0n (TCR0nH, TCR0nL) Register Timer data register 0n (TDR0nH, TDR0nL)
Page 123 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figures 6-1 and 6-2 show the block diagrams of the timer array unit. Figure 6-1. Entire Configuration of Timer Array Unit Timer clock select register 0 (TPS0) PRS013 PRS012 PRS0 11 PRS010 PRS003 PRS002 PRS001 PRS000...
Page 124 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-2. Internal Block Diagram of Channel of Timer Array Unit (a) Channels 0 and 2 Note Interrupt signal from master channel CK00 Timer controller Output TCLK TO00 controller CK01 TO02 Output latch Mode...
Page 125: Timer Counter Register 0N (Tcr0N)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.2.1 Timer counter register 0n (TCR0n) TCR0n register consists of two 8-bit read-only registers (TCR0nH and TCR0nL) and is used to count clocks (f TCLK When data is read from the TCR0n register, the TCR0nH and TCR0nL registers must be accessed consecutively.
Page 126 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT The TCR0n register read value differs as follows according to operation mode changes and the operating status. Table 6-3. Timer Counter Register 0n (TCR0n) Read Value in Various Operation Modes Note Operation Mode Count Mode...
Page 127: Timer Data Register 0N (Tdr0N)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.2.2 Timer data register 0n (TDR0n) The TDR0n register consists of two eight bit registers (TDR0nH, TDR0nL) for which the capture or comparison functions can be selected. Switching between the capture and comparison functions is by using the MD0n3 to MD0n0 bits of the timer mode register 0n (TMR0n) to select the operating mode.
Page 128 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-4. Format of Timer Data Register 0n (TDR0nH, TDR0nL) (n = 0, 2) Address: FFF18H (TDR00L), FFF19H (TDR00H), After reset: 00H FFF64H (TDR02L), FFF65H (TDR02H) FFF19H (TDR00H) FFF18H (TDR00L) TDR0n Figure 6-5. Format of Timer Data Register 0n (TDR0n) (n = 1, 3)
Page 129: Registers Controlling Timer Array Unit
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers. ● Peripheral enable register 0 (PER0) ● Timer clock select register 0 (TPS0) ● Timer channel enable status register 0 (TE0, TEH0) ●...
Page 130: Peripheral Enable Register 0 (Per0)
● Timer mode register 0n (TMR0nH, TMR0nL) ● Timer status register 0n (TSR0n) 2. Be sure to clear the following bits to 0. R7F0C806 and R7F0C807 products: bits 1, 3, 4 R7F0C808 and R7F0C809 products: bits 1, 3, 4, 6 R01UH0481EJ0140 Rev.1.40...
Page 131: Timer Clock Select Register 0 (Tps0)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.2 Timer clock select register 0 (TPS0) The TPS0 register is a 16-bit register that is used to select four types of operation clocks (CK00, CK01) that are commonly supplied to each channel from the prescaler.
Page 132: Timer Mode Register 0N (Tmr0N)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.3 Timer mode register 0n (TMR0n) The TMR0n register consists of two eight-bit registers (TMR0nH, TMR0nL) which set an operation mode of channel n. This register is used to select the operation clock (f...
Page 133 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-8. Format of Timer Mode Register 0n (TMR0n) (1/3) Address: : F0190H (TMR00L), F0191H (TMR00H) After reset: 00H : F0192H (TMR01L), F0193H (TMR01H) : F0194H (TMR02L), F0195H (TMR02H) : F0196H (TMR03L), F0197H (TMR03H)
Page 134 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-8. Format of Timer Mode Register 0n (TMR0n) (2/3) Symbol TMR00H CKS001 CCS00 STS002 STS001 STS000 Symbol TMR02H CKS021 CCS02 MASTER02 STS022 STS021 STS020 Symbol TMR0nH CKS0n1 CCS0n SPLIT0n STS0n2 STS0n1 STS0n0 (n = 1, 3)
Page 135 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-8. Format of Timer Mode Register 0n (TMR0n) (3/3) Symbol TMR0nL CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 (n = 0 to 3) CIS0n1 CIS0n0 Selection of TI0n pin input valid edge Falling edge...
Page 136 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Notes 1. In one-count mode, the interrupt request signal (INTTM0n) when starting a count operation and TO0n output are not controlled. 2. If the start trigger (TS0n = 1) is issued during operation, the counter is initialized, and recounting is started (interrupt request signal (INTTM0n) is not generated).
Page 137: Timer Status Register 0N (Tsr0N)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.4 Timer status register 0n (TSR0n) The TSR0n register indicates the overflow status of the counter of channel n. The TSR0n register is valid only in the capture mode (MD0n3 to MD0n1 = 010B) and capture & one-count mode (MD0n3 to MD0n1 = 110B).
Page 138: Timer Channel Enable Status Register 0 (Te0, Teh0 (8-Bit Mode))
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.5 Timer channel enable status register 0 (TE0, TEH0 (8-bit mode)) The TE0 and TEH0 registers are used to enable or stop the timer operation of each channel. Each bit of the TE0 and TEH0 registers correspond to each bit of the timer channel start register 0 (TS0, TSH0) and the timer channel stop register 0 (TT0, TTH0).
Page 139: Timer Channel Start Register 0 (Ts0, Tsh0 (8-Bit Mode))
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.6 Timer channel start register 0 (TS0, TSH0 (8-bit mode)) The TS0 and TSH0 registers are trigger registers that are used to initialize timer counter register 0n (TCR0n) and start the counting operation of each channel.
Page 140: Timer Channel Stop Register 0 (Tt0, Tth0 (8-Bit Mode))
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.7 Timer channel stop register 0 (TT0, TTH0 (8-bit mode)) The TT0 and TTH0 registers are trigger registers that are used to stop the counting operation of each channel. When a bit of TT0 and TTH0 registers is set to 1, the corresponding bit of timer channel enable status register 0 (TE0, TEH0) is cleared to 0.
Page 141: Timer Output Enable Register 0 (Toe0)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.8 Timer output enable register 0 (TOE0) The TOE0 register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TO0n bit of timer output register 0 (TO0) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TO0n).
Page 142: Timer Output Register 0 (To0)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.9 Timer output register 0 (TO0) The TO0 register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TO0n) of each channel.
Page 143: Timer Output Level Register 0 (Tol0)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.10 Timer output level register 0 (TOL0) The TOL0 register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOE0n = 1) in the Slave channel output mode (TOM0n = 1).
Page 144: Timer Output Mode Register 0 (Tom0)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.11 Timer output mode register 0 (TOM0) The TOM0 register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.
Page 145: Noise Filter Enable Register 1 (Nfen1)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.12 Noise filter enable register 1 (NFEN1) The NFEN1 register is used to set whether the noise filter can be used for the timer input (TI0n) pin signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
Page 146: Input Switch Control Register (Isc)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.13 Input switch control register (ISC) The ISC register is used to implement baud rate correction by using channel 1 in association with the serial array unit. When the ISC1 bit is set to 1, the input signal of the serial data input (RXD0) pin is selected as a timer input (TI01).
Page 147: Timer I/O Control Register (Tiosc)
Disable TO03 output TOEN1 Note TO01 output control for RTO Enable TO01 output Disable TO01 output TINT Input clock source selection for TAU of channel 2 TI02 input INTTM01 input Note R7F0C806 and R7F0C807 products only. R01UH0481EJ0140 Rev.1.40 Apr 10, 2018...
Page 148: Registers Controlling Port Functions Of Pins To Be Used For Timer I/O
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.3.15 Registers controlling port functions of pins to be used for timer I/O Using the timer array unit functions requires setting of the registers that control the port functions multiplexed on the target channels (port mode register (PMxx), port register (Pxx), and port mode control register (PMCxx)). For details, see 4.3.1 Port mode registers 0, 1, 4 (PM0, PM1, PM4), 4.3.2 Port registers 0, 1, 4, 12, 13 (P0, P1, P4, P12, P13), and...
Page 149: Basic Rules Of Timer Array Unit
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.4 Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
Page 150 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Example TAU0 Channel group 1 CK00 Channel 0: Master (Simultaneous channel operation function) Channel 1: Slave Channel group 2 (Simultaneous channel operation function) CK01 Channel 2: Master Channel 3: Slave * The operating clock of channel group 1 may be different from that of channel group 2.
Page 151: Basic Rules Of 8-Bit Timer Operation Function (Only Channels 1 And 3)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (only channels 1 and 3) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8- bit timer channels.
Page 152: Operation Of Counter
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.5 Operation of Counter 6.5.1 Count clock (f TCLK The count clock (f ) of the timer array unit can be selected between following by CCS0n bit of timer mode register 0n TCLK (TMR0n).
Page 153 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TI0n pin is selected (CCS0n = 1) The count clock (f ) is the signal that detects valid edge of input signal via the TI0n pin and synchronizes next...
Page 154: Start Timing Of Counter
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Timer count register 0n (TCR0n) operation becomes enabled by setting of TS0n bit of timer channel start register 0 (TS0). Operations from count operation enabled state to timer count register 0n (TCR0n) count start is shown in Table 6-5.
Page 155: Counter Operation
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.5.3 Counter operation Here, the counter operation in each mode is explained. (1) Interval timer mode operation <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. Timer count register 0n (TCR0n) holds the initial value until count clock (f ) generation.
Page 156 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT (2) Event counter mode operation <1> Timer count register 0n (TCR0n) holds its initial value while operation is stopped (TE0n = 0). <2> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit.
Page 157 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT (3) Capture mode operation (input pulse interval measurement) <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. <2> Timer count register 0n (TCR0n) holds the initial value until count clock (f ) generation.
Page 158 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT (4) One-count mode operation <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. <2> Timer count register 0n (TCR0n) holds the initial value until start trigger generation. <3> Rising edge of the TI0n input is detected.
Page 159 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT (5) Capture & one-count mode operation (high-level width is measured) <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit of timer channel start register 0 (TS0). <2> Timer count register 0n (TCR0n) holds the initial value until start trigger generation.
Page 160: Channel Output (To0N Pin) Control
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.6 Channel Output (TO0n pin) Control 6.6.1 TO0n pin output circuit configuration Figure 6-30. Output Circuit Configuration <5> TO0n register Interrupt signal of the master channel (INTTM0n) TO0n pin Interrupt signal of the slave channel...
Page 161: To0N Pin Output Setting
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TO0n pin output setting The following figure shows the procedure and status transition of the TO0n output pin from initial setting to timer operation start. Figure 6-31. Status Transition from Timer Output Setting to Operation Start...
Page 162: Cautions On Channel Output Operation
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Cautions on channel output operation (1) Changing values set in the registers TO0, TOE0, TOL0, and TOM0 during timer operation Since the timer operations (operations of timer count register 0n (TCR0n) and timer data register 0n (TDR0n)) are...
Page 163 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOM0p = 1) setting (PWM output) When slave channel output mode (TOM0p = 1), the active level is determined by timer output level register 0 (TOL0p) setting.
Page 164 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TO0n pin in slave channel output mode (TOM0n = 1) (a) When timer output level register 0 (TOL0) setting has been changed during timer operation When the TOL0 register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TO0n pin change condition.
Page 165 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-35. Set/Reset Timing Operating Statuses (a) Basic operation timing TCLK INTTM0n Internal reset Master signal channel TO0n pin/ TO0n Toggle Toggle Internal set signal 1 clock delay INTTM0p Slave channel Internal reset signal...
Page 166: Collective Manipulation Of To0N Bit
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TO0n bit In timer output register 0 (TO0), the setting bits for all the channels are located in one register in the same way as timer channel start register 0 (TS0). Therefore, the TO0n bit of all the channels can be manipulated collectively.
Page 167: Timer Interrupt And To0N Pin Output At Count Operation Start
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.6.5 Timer interrupt and TO0n pin output at count operation start In the interval timer mode or capture mode, the MD0n0 bit in timer mode register 0n (TMR0n) sets whether or not to generate a timer interrupt at count start.
Page 168: Timer Input (Ti0N) Control
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.7 Timer Input (TI0n) Control 6.7.1 TI0n input circuit configuration A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer controller.
Page 169: Cautions On Channel Input Operation
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Cautions on channel input operation When a timer input pin is set as unused, the operating clock is not supplied to the noise filter. Therefore, after settings are made to use the timer input pin, the following wait time is necessary before a trigger is specified to enable operation of the channel corresponding to the timer input pin.
Page 170: Independent Channel Operation Function Of Timer Array Unit
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.8 Independent Channel Operation Function of Timer Array Unit 6.8.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates the interrupt request signal (INTTM0n) at fixed intervals.
Page 171 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-41. Block Diagram of Operation as Interval Timer/Square Wave Output CK01 Operation clock Timer counter Output CK00 TO0n pin register 0n (TCR0n) controller Timer data Interrupt Interrupt signal TS0n register 0n (TDR0n) controller (INTTM0n) Figure 6-42.
Page 172 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers for Operation as Interval Timer/Square Wave Output (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0...
Page 173 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers for Operation as Interval Timer/Square Wave Output (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Setting is invalid because master channel output mode is set (TOM0n = 0).
Page 174: Chapter 6 Timer Array Unit
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Procedure for Operating Interval Timer/Outputting Square Wave (1/2) Software operation Hardware status Power-off status default (Clock supply is stopped and writing to SFR of the TAU is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).
Page 175 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Procedure for Operating Interval Timer/Outputting Square Wave (2/2) Software operation Hardware status To hold the TO0n pin output level Clears the TO0n bit to 0 after the value to stop be held (output latch) is set in the port register.
Page 176: Operation As External Event Counter
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TI0n pin. When a specified count value is reached, the event counter generates the interrupt request signal (INTTM0n).
Page 177 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Example of Basic Timing of Operation as External Event Counter TS0n TE0n TI0n TCR0n 0000H TDR0n 0003H 0002H INTTM0n 4 events 4 events 3 events Remarks 1. n: Channel number (n = 0 to 3) 2.
Page 178 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers in External Event Counter Mode (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2...
Page 179 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers in External Event Counter Mode (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Setting is invalid because master channel output mode is set (TOM0n = 0).
Page 180 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Procedure for Operating External Event Counter Software operation Hardware status Power-off status default (Clock supply is stopped and writing to SFR of the TAU setting is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).
Page 181: Operation As Frequency Divider (Only Channels 0 And 3)
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as frequency divider (only channels 0 and 3) The timer array unit can be used as a frequency divider that divides a clock input to the TI0n pin and outputs the result clock from the TO0n pin.
Page 182 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Example of Basic Timing of Operation as Frequency Divider (MD00n = 1) TS00 TE00 TI00 TCR00 0000H TDR00 0002H 0001H TO00 INTTM00 Divided Divided by 6 by 4 Remark n: Channel number (n = 0, 3)
Page 183 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Example of Set Contents of Registers During Operation as Frequency Divider (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2...
Page 184 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Example of Set Contents of Registers During Operation as Frequency Divider (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Setting is invalid because master channel output mode is set (TOM0n = 0).
Page 185 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Procedure for Operating Frequency Divider Software operation Hardware status Power-off status (Clock supply is stopped and writing to SFR of the TAU is default disabled.) setting Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).
Page 186: Operation As Input Pulse Interval Measurement
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.8.4 Operation as input pulse interval measurement The count value can be captured on detection of a valid edge of TI0n pin input and the interval of the pulse input to TI0n pin can be measured. In addition, the count value can be captured by setting TS0n to 1 by software during the period of TE0n = 1.
Page 187 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-54. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MD0n0 = 0) TS0n TE0n TI0n FFFFH TCR0n 0000H TDR0n 0000H INTTM0n Remarks 1. n: Channel number (n = 0 to 3) 2.
Page 188 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-55. Example of Set Contents of Registers to Measure Input Pulse Interval (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note 1 CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3...
Page 189 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-55. Example of Set Contents of Registers to Measure Input Pulse Interval (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Setting is invalid because master channel output mode is set (TOM0n = 0).
Page 190 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Procedure for Measuring Input Pulse Interval Software operation Hardware status Power-off status default (Clock supply is stopped and writing to SFR of the TAU setting is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).
Page 191: Operation As Input Signal High-/Low-Level Width Measurement
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.8.5 Operation as input signal high-/low-level width measurement By starting counting at one edge of the TI0n pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TI0n can be measured. The signal width of TI0n can be calculated by the following expression.
Page 192 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-57. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement CK01 Operation clock Timer counter Interrupt Interrupt signal CK00 register 0n (TCR0n) controller (INTTM0n) TNFEN0n Timer data Noise Edge TI0n pin register 0n (TDR0n)
Page 193 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3...
Page 194 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (2/2) (e) Timer output mode register 0 (TOM0) Bit n TOM0 0: Sets master channel output mode. TOM0n Remark n: Channel number (n = 0 to 3) R01UH0481EJ0140 Rev.1.40...
Page 195 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Procedure for Measuring Input Signal High-/Low-Level Width Software operation Hardware status Power-off status default (Clock supply is stopped and writing to SFR of the TAU setting is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).
Page 196: Operation As Delay Counter
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.8.6 Operation as delay counter It is possible to start counting down when the valid edge of the TI0n pin input is detected (an external event), and then generate the interrupt request signal (INTTM0n) after any specified interval.
Page 197 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Example of Basic Timing of Operation as Delay Counter TS0n TE0n TI0n FFFFH TCR0n 0000H TDR0n INTTM0n Remarks 1. n: Channel number (n = 0 to 3) 2. TS0n: Bit n of timer channel start register 0 (TS0)
Page 198 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note 1 CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1...
Page 199 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Setting is invalid because master channel output mode is set (TOM0n = 0).
Page 200 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Procedure for Operating Delay Counter Software operation Hardware status Power-off status default (Clock supply is stopped and writing to SFR of the TAU setting is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).
Page 201: Simultaneous Channel Operation Function Of Timer Array Unit
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.9 Simultaneous Channel Operation Function of Timer Array Unit 6.9.1 Operation as one-shot pulse output By using two channels as a set, a one-shot pulse having any delay (output delay time) can be generated from the signal input to the TI0n pin.
Page 202 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Block Diagram of Operation for One-shot Pulse Output Master channel (one-count mode) CK01 Operation clock Timer counter register 0n (TCR0n) CK00 TS0n Timer data Interrupt Interrupt signal register 0n (TDR0n) controller Noise...
Page 203 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Example of Basic Timing of Operation for One-shot Pulse Output TS0n TE0n TI0n Master FFFFH channel TCR0n 0000H TDR0n TO0n INTTM0n TS0p TE0p FFFFH TCR0p Slave 0000H channel TDR0p TO0p INTTM0p Remarks 1. n: Master channel number (n = 0, 2) p: Slave channel number (n <...
Page 204 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Set Contents of Registers for One-shot Pulse Output (Master Channel) (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note 1 CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0...
Page 205 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Set Contents of Registers for One-shot Pulse Output (Master Channel) (2/2) (e) Timer output mode register 0 (TOM0) Bit n TOM0 0: Sets master channel output mode. TOM0n Remark n: Master channel number (n = 0, 2) R01UH0481EJ0140 Rev.1.40...
Page 206 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Set Contents of Registers for One-shot Pulse Output (Slave Channel) (1/2) (a) Timer mode register 0p (TMR0pH, TMR0pL) TMR0pH TMR0pL TMR0p Note CKS0p1 CCS0p STS0p2 STS0p1 STS0p0 CIS0p1 CIS0p0 MD0p3...
Page 207 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Set Contents of Registers for One-shot Pulse Output (Slave Channel) (2/2) (e) Timer output mode register 0 (TOM0) Bit p TOM0 1: Sets the slave channel output mode. TOM0p Remark n: Master channel number (n = 0, 2) p: Slave channel number (n <...
Page 208 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Procedure for Outputting One-shot Pulse (1/2) Software operation Hardware status Power-off status default (Clock supply is stopped and writing to SFR of the TAU setting is disabled.) Sets the TAU0EN bit of peripheral enable registers 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write Power-on status.
Page 209 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Procedure for Outputting One-shot Pulse (2/2) Software operation Hardware status Operation Sets the TOE0p bit of the slave channel to 1 to enable start TO0p operation (only when operation is resumed). Sets the target bits of the TS0 register (master and slave) to 1 at the same time.
Page 210: Two-Channel Input With One-Shot Pulse Output Function
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.9.2 Two-channel input with one-shot pulse output function By using signal input to two pins (TI0n and TI0p), a one-shot pulse having any delay pulse width can be generated. The two-channel input with one-shot pulse output function is provided only in the 16-bit products.
Page 211 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Block Diagram of Operation for Two-channel Input with One-shot Pulse Output Function Master channel (one-count mode) CK01 Operation clock Timer counter register 0n (TCR0n) CK00 TS0n Timer data Interrupt Interrupt signal Noise...
Page 212 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Example of Basic Timing of Operation for Two-channel Input with One-shot Pulse Output Function TS0n TE0n TI0n Master channel FFFFH TCR0n 0000H TDR0n TO0n INTTM0n TS0p TE0p TI0p FFFFH TCR0p 0000H Slave...
Page 213 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Set Contents of Registers for Two-channel Input with One-shot Pulse Output Function (Master Channel) (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note 1 CKS0n1 CCS0n STS0n2...
Page 214 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Set Contents of Registers for Two-channel Input with One-shot Pulse Output Function (Master Channel) (2/2) (e) Timer output mode register 0 (TOM0) Bit n TOM0 0: Sets master channel output mode.
Page 215 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Example of Set Contents of Registers for Two-channel Input with One-shot Pulse Output Function (Slave Channel) (1/2) (a) Timer mode register 0p (TMR0pH, TMR0pL) TMR0pH TMR0pL TMR0p CKS0p1 CCS0p STS0p2 STS0p1 STS0p0...
Page 216 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Example of Set Contents of Registers for Two-channel Input with One-shot Pulse Output Function (Slave Channel) (2/2) (e) Timer output mode register 0 (TOM0) Bit p TOM0 1: Sets the slave channel output mode.
Page 217 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Procedure for Two-channel Input with One-shot Pulse Output Function (1/2) Software operation Hardware status Power-off status default (Clock supply is stopped and writing to SFR of the TAU setting is disabled.) Sets the TAU0EN bit of peripheral enable registers 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write Power-on status.
Page 218 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Procedure for Two-channel Input with One-shot Pulse Output Function (2/2) Software operation Hardware status Operation Sets the TOE0p bit of the slave channel to 1 to enable start TO0p operation (only when operation is resumed).
Page 219: Operation As Pwm Output Function
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.9.3 Operation as PWM output function Two channels can be used as a set to generate a pulse of any period and duty factor. When channel 1 or 3 is used as an 8-bit timer (SPLIT0n = 1), only the lower 8-bit timer can be used as the slave channel for the PWM output function.
Page 220 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-75. Block Diagram of Operation as PWM Output Function Master channel (interval timer mode) CK01 Operation clock Timer counter register 0n (TCR0n) CK00 Timer data Interrupt Interrupt signal TS0n register 0n (TDR0n) controller...
Page 221 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-76. Example of Basic Timing of Operation as PWM Output Function TS0n TE0n FFFFH Master TCR0n channel 0000H TDR0n TO0n INTTM0n TS0p TE0p FFFFH TCR0p Slave 0000H channel TDR0p TO0p INTTM0p Remarks 1. n: Master channel number (n = 0, 2) p: Slave channel number (n <...
Page 222 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-77. Example of Set Contents of Registers for PWM Output Function (Master Channel) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2...
Page 223 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-78. Example of Set Contents of Registers for PWM Output Function (Slave Channel) (1/2) (a) Timer mode register 0p (TMR0pH, TMR0pL) TMR0pH TMR0pL TMR0p Note CKS0p1 CCS0p STS0p2 STS0p1 STS0p0 CIS0p1 CIS0p0 MD0p3...
Page 224 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-78. Example of Set Contents of Registers for PWM Output Function (Slave Channel) (2/2) (e) Timer output mode register 0 (TOM0) Bit p TOM0 1: Sets the slave channel output mode. TOM0p Remark n: Master channel number (n = 0, 2) p: Slave channel number (n <...
Page 225 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-79. Procedure for Using PWM Output Function (1/2) Software operation Hardware status Power-off status default (Clock supply is stopped and writing to SFR of the TAU setting is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).
Page 226: Chapter 6 Timer Array Unit
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-79. Procedure for Using PWM Output Function (2/2) Software operation Hardware status Operation Sets the TOE0p bit of the slave register to 1 and enables start operation of TO0n (only when operation is resumed).
Page 227: Operation As Multiple Pwm Output Function
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.9.4 Operation as multiple PWM output function By extending the PWM output function and using multiple slave channels, many PWM waveforms with different duty values can be output. The multiple PWM output function is provided only in the 16-bit products.
Page 228 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-80. Block Diagram of Operation as Multiple PWM Output Function (Output Two Types of PWMs) Master channel (interval timer mode) CK01 Operation clock Timer counter register 0n (TCR0n) CK00 Timer data Interrupt Interrupt signal...
Page 229 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-81. Example of Basic Timing of Operation as Multiple PWM Output Function (Output Two Types of PWMs) TS0n TE0n FFFFH Master TCR0n channel 0000H TDR0n TO0n INTTM0n TS0p TE0p FFFFH TCR0p Slave 0000H...
Page 230 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Remarks 1. n: Channel number (n = 0) p: Slave channel number 1, q: Slave channel number 2 n < p < q ≤ 3 (Where p and q are consecutive integers greater than n) 2.
Page 231 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-82. Example of Set Contents of Registers for Multiple PWM Output Function (Master Channel) (2/2) (b) Timer output register 0 (TO0) Bit 0 0: Outputs 0 from TO00. TO00 (c) Timer output enable register 0 (TOE0)
Page 232 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-83. Example of Set Contents of Registers for Multiple PWM Output Function (Slave Channel) (Output Two Types of PWMs) (1/2) (a) Timer mode register 0p, 0q (TMR0p, TMR0q) TMR0p Note CKS0p1 CCS0p STS0p2...
Page 233 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-83. Example of Set Contents of Registers for Multiple PWM Output Function (Slave Channel) (Output Two Types of PWMs) (2/2) (b) Timer output register 0 (TO0) Bit q Bit p 0: Outputs 0 from TO0p or TO0q.
Page 234 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-84. Procedure for Using Multiple PWM Output Function (Output Two Types of PWMs) (1/2) Software operation Hardware status Power-off status default (Clock supply is stopped and writing to SFR of the TAU setting is disabled.)
Page 235 R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT Figure 6-84. Procedure for Using Multiple PWM Output Function (Output Two Types of PWMs) (2/2) Software operation Hardware status Sets the TOE0p and TOE0q bits of the slave register to 1 Operation and enables the TO0p and TO0q outputs by the count start operation (only when resuming operation).
Page 236: Cautions When Using Timer Array Unit
R7F0C806-809 CHAPTER 6 TIMER ARRAY UNIT 6.10 Cautions When Using Timer Array Unit 6.10.1 Cautions when using timer output Depending on the product, a timer output and other alternate functions may be assigned to some pins. In such case, the outputs of the other alternate functions must be set to their initial states.
Page 237: Chapter 7 12-Bit Interval Timer
R7F0C806-809 CHAPTER 7 12-BIT INTERVAL TIMER CHAPTER 7 12-BIT INTERVAL TIMER 7.1 Functions of 12-bit Interval Timer An interrupt request signal (INTIT) is generated at any previously specified time interval. It can be utilized as the trigger for waking up from STOP mode and HALT mode.
Page 238: Registers Controlling 12-Bit Interval Timer
● Interval timer control register H (ITMCH) ● Interval timer control register L (ITMCL) 3. Be sure to clear the following bits to 0. R7F0C806 and R7F0C807 products: Bits 1, 3, and 4 R7F0C808 and R7F0C809 products: Bits 1, 3, 4, and 6 R01UH0481EJ0140 Rev.1.40...
Page 239: Operation Speed Mode Control Register (Osmc)
R7F0C806-809 CHAPTER 7 12-BIT INTERVAL TIMER 7.3.2 Operation speed mode control register (OSMC) The WUTMMCK0 bit can be used to control supply of the 12-bit interval timer count clock. Set the WUTMMCK0 bit to 1 before operating the 12-bit interval timer.
Page 240: Interval Timer Control Register (Itmch, Itmcl)
R7F0C806-809 CHAPTER 7 12-BIT INTERVAL TIMER 7.3.3 Interval timer control register (ITMCH, ITMCL) This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer compare value. Set the eight lower-order bits (ITCMP7 to ITCMP0) of the value for comparison in the ITMCL register and then set the four higher-order bits (ITCMP11 to ITCMP8) of the value for comparison and make the setting to stop or start counter operation in the ITMCH register.
Page 241: 12-Bit Interval Timer Operation
R7F0C806-809 CHAPTER 7 12-BIT INTERVAL TIMER 7.4 12-bit Interval Timer Operation 7.4.1 12-bit interval timer operation timing The count value specified for the ITCMP11 to ITCMP0 bits is used as an interval to operate a 12-bit interval timer that repeatedly generates interrupt requests (INTIT).
Page 242: Start Of Count Operation And Re-Enter To Halt/Stop Mode After Returned From
R7F0C806-809 CHAPTER 7 12-BIT INTERVAL TIMER 7.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from HALT/STOP mode When setting the RINTE bit after returned from HALT or STOP mode and entering HALT or STOP mode again, write 1 to the RINTE bit, and confirm the written value of the RINTE bit is reflected or wait for at least one cycle of the count clock.
Page 243: Chapter 8 Clock Output/Buzzer Output Controller
CCS00 Clock output select register 0 (CKS0) Internal bus Note R7F0C806,807 products only Caution The PCLBUZ0 pin can output a frequency, see 23.4 AC Characteristics. Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR).
Page 244: Configuration Of Clock Output/Buzzer Output Controller
R7F0C806-809 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 8.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 8-1. Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output select register 0 (CKS0)
Page 245: Clock Output Select Register 0 (Cks0)
R7F0C806-809 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 8.3.1 Clock output select register 0 (CKS0) This register sets output enable/disable for clock output or for the buzzer frequency output pin (PCLBUZ0), and sets the output clock. The CKS0 register is set by a 1-bit or 8-bit memory manipulation instruction.
Page 246: Registers Controlling Port Functions Of Clock Output/Buzzer Output Pin
R7F0C806-809 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 8.3.2 Registers controlling port functions of clock output/buzzer output pin Using the port pin for the clock output/buzzer output controller requires setting of the registers that control the port function multiplexed on the clock output/buzzer output pin (PCLBUZ0 pin): (port mode registers 0, 4 (PM0, PM4), port registers 0, 4 (P0, P4), port mode control register 0 (PMC0), peripheral I/O redirection register (PIOR)).
Page 247: Operations Of Clock Output/Buzzer Output Controller
R7F0C806-809 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 8.4 Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
Page 248: Chapter 9 Watchdog Timer
R7F0C806-809 CHAPTER 9 WATCHDOG TIMER CHAPTER 9 WATCHDOG TIMER 9.1 Functions of Watchdog Timer The count operation is specified by the user option byte (000C0H) in the watchdog timer. The watchdog timer operates on the low-speed on-chip oscillator clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.
Page 249: Configuration Of Watchdog Timer
R7F0C806-809 CHAPTER 9 WATCHDOG TIMER 9.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 9-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled and overflow time are set by the option byte.
Page 250: Register Controlling Watchdog Timer
R7F0C806-809 CHAPTER 9 WATCHDOG TIMER 9.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 9.3.1 Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.
Page 251: Operation Of Watchdog Timer
R7F0C806-809 CHAPTER 9 WATCHDOG TIMER 9.4 Operation of Watchdog Timer 9.4.1 Controlling operation of watchdog timer <1> When the watchdog timer is used, its operation is specified by the option byte (000C0H). ● Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 18).
Page 252: Setting Time Of Watchdog Timer
R7F0C806-809 CHAPTER 9 WATCHDOG TIMER 9.4.2 Setting time of watchdog timer Set the overflow time and interval interrupt time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H). If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts counting again by writing “ACH”...
Page 253: Chapter 10 A/D Converter
R7F0C806-809 CHAPTER 10 A/D CONVERTER CHAPTER 10 A/D CONVERTER The A/D converter has eight analog input channels. 10.1 Function of A/D Converter The A/D converter is used to convert analog input signals into digital values, and is configured to control up to 8 channels of A/D converter analog inputs.
Page 254 R7F0C806-809 CHAPTER 10 A/D CONVERTER R01UH0481EJ0140 Rev.1.40 Apr 10, 2018...
Page 255: Configuration Of A/D Converter
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI7 pins These are the analog input pins of the 7 channels of the A/D converter. They input analog signals to be converted into digital signals.
Page 256 R7F0C806-809 CHAPTER 10 A/D CONVERTER (7) A/D conversion result lower-order bit storage register (ADCRL) ADCRL is an 8-bit register which holds the two lower-order bits (ADCR1, ADCR0) of the result of 10-bit A/D conversion. The six lower-order bits of this register are fixed to 0.
Page 257: Registers Used In A/D Converter
● A/D conversion result lower-order bit storage register (ADCRL) ● Analog input channel specification register (ADS) 2. Be sure to clear the following bits to 0. R7F0C806 and R7F0C807 products: Bits 1, 3, and 4 R7F0C808 and R7F0C809 products: Bits 1, 3, 4, and 6 R01UH0481EJ0140 Rev.1.40...
Page 258: A/D Converter Mode Register 0 (Adm0)
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 259 R7F0C806-809 CHAPTER 10 A/D CONVERTER Table 10-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation Conversion stopped state Conversion standby state Setting prohibited Conversion-in-progress state Figure 10-4. Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables operation...
Page 260 R7F0C806-809 CHAPTER 10 A/D CONVERTER Table 10-3. 8-bit Resolution A/D Conversion Time Selection A/D Converter Mode Conversion Number of Conversion Conversion Time Selection (µs) Register 0 (ADM0) Clock Conversion Time Clock Note 1.25 MHz 2.5 MHz 5 MHz 10 MHz...
Page 261 R7F0C806-809 CHAPTER 10 A/D CONVERTER Figure 10-5. A/D Converter Sampling and A/D Conversion Timing 1 is written to ADCS. ADCS Sampling timing INTAD Sampling Successive conversion Conversion standby status Conversion time R01UH0481EJ0140 Rev.1.40 Apr 10, 2018...
Page 262: A/D Converter Mode Register 2 (Adm2)
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.3.3 A/D converter mode register 2 (ADM2) This register is used to set the resolution of the A/D converter. The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 263: A/D Conversion Result Lower-Order Bit Storage Register (Adcrl)
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.3.5 A/D conversion result lower-order bit storage register (ADCRL) This register is an 8-bit register that holds the two lower-order bits of the result of 10-bit A/D conversion. The six lower- order bits are fixed to 0.
Page 264: Analog Input Channel Specification Register (Ads)
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.3.6 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 265: A/D Converter Conversion Operations
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended.
Page 266 R7F0C806-809 CHAPTER 10 A/D CONVERTER Figure 10-11. Conversion Operation of A/D Converter 1 is written to ADCS ADCS Conversion time Sampling time Conversion Sampling A/D converter Conversion A/D conversion standby operation standby Conversion Undefined result Conversion ADCRH, ADCRL result INTAD A/D conversion is performed once when the bit 7 (ADCS) of the A/D converter mode register 0 (ADM0) is set to 1 by software.
Page 267: Input Voltage And Conversion Results
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the A/D conversion result register (ADCR = ADCRH + ADCRL)) is shown by the following expression.
Page 268: A/D Converter Operation Modes
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.6 A/D Converter Operation Modes The operation of the A/D converter is described below. In addition, the setting procedure is described in 10.7 A/D Converter Setup Flowchart. <1> In the conversion stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the conversion standby status.
Page 269: A/D Converter Setup Flowchart
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.7 A/D Converter Setup Flowchart The A/D converter setup flowchart is described below. 10.7.1 Setting up A/D conversion of voltages on ANI0 to ANI7 Figure 10-14. Setting Up A/D Conversion of Voltages on ANI0 to ANI7 Start of setup The ADCEN bit of the PER0 register is set (1), and a clock is provided to the A/D converter.
Page 270: How To Read A/D Converter Characteristics Table
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.8 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. 10.8.1 Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 271: Zero-Scale Error
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.8.4 Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0..000 to 0..001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0……001 to 0……010.
Page 272: Conversion Time
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.8.8 Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. 10.8.9 Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample &...
Page 273: Cautions For A/D Converter
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.9 Cautions for A/D Converter 10.9.1 Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time.
Page 274: Analog Input (Anin) Pins
R7F0C806-809 CHAPTER 10 A/D CONVERTER Figure 10-21. Analog Input Pin Connection If there is a possibility that noise equal to or higher than or equal to or lower than V may enter, clamp with a diode with a small V value (0.3 V or lower).
Page 275: Internal Equivalent Circuit
R7F0C806-809 CHAPTER 10 A/D CONVERTER 10.9.10 Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10-22. Internal Equivalent Circuit of ANIn Pin ANIn Table 10-4. Resistance and Capacitance Values of Equivalent Circuit ANIn Pins R1 [kΩ]...
Page 276: Chapter 11 Serial Array Unit
CHAPTER 11 SERIAL ARRAY UNIT CHAPTER 11 SERIAL ARRAY UNIT Serial array unit 0 has two serial channels. Each channel can achieve 3-wire serial (CSI) and UART communication. Function assignment of each channel supported by the R7F0C806-809 is as shown below. Unit Channel...
Page 277: Functions Of Serial Array Unit
CHAPTER 11 SERIAL ARRAY UNIT 11.1 Functions of Serial Array Unit Each serial interface supported by the R7F0C806-809 has the following features. 11.1.1 3-wire serial I/O (CSI00) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.
Page 278: Uart (Uart0)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.1.2 UART (UART0) This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception (RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 279: Configuration Of Serial Array Unit
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 11-1. Configuration of Serial Array Unit Item Configuration Shift register 8 bits Buffer register Serial data register 0nL (SDR0nL...
Page 280 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-1 shows the block diagram of the serial array unit 0. Figure 11-1. Block Diagram of Serial Array Unit 0 Noise filter enable Serial output register 0 (SO0) Serial clock output register 0 (CKO0)
Page 281: Shift Register
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (1) Shift register This is an 8-bit register that converts parallel data into serial data or vice versa. During reception, it converts data input to the serial pin into parallel data. When data is transmitted, the value set to this register is output as serial data from the serial output pin.
Page 282: Registers Controlling Serial Array Unit
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers. ● Peripheral enable register 0 (PER0) ● Serial clock select register 0 (SPS0) ● Serial mode register 0n (SMR0nH, SMR0nL) ●...
Page 283: Peripheral Enable Register 0 (Per0)
● Serial output register 0 (SO0) ● Serial clock output register (CKO0) 2. Be sure to clear the following bits to 0. R7F0C806 and R7F0C807 products: Bits 1, 3, and 4 R7F0C808 and R7F0C809 products: Bits 1, 3, 4, and 6 R01UH0481EJ0140 Rev.1.40...
Page 284: Serial Clock Select Register 0 (Sps0)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.2 Serial clock select register 0 (SPS0) The SPS0 register is an 8-bit register that is used to select two types of operation clocks (CK00, CK01) that are commonly supplied to each channel. CK01 is selected by bits 7 to 4 of the SPS0 register, and CK00 is selected by bits 3 to 0.
Page 285: Serial Mode Register 0N (Smr0Nh, Smr0Nl)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.3 Serial mode register 0n (SMR0nH, SMR0nL) The SMR0nH and SMR0nL registers are registers that set an operation mode of channel n. It is also used to select an operation clock (f ), specify whether the serial clock (f ) may be input or not, set a start trigger, an operation mode (CSI or UART), and an interrupt source.
Page 286 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-5. Format of Serial Mode Register 0n (SMR0nH, SMR0nL) (2/2) Address: F0111H (SMR00H), F0113H (SMR01H) Address: F0110H (SMR00L), F0112H (SMR01L) After reset: 00H After reset: 20H Symbol Symbol SMR0nH CKS SMR0nL Note 3...
Page 287: Serial Communication Operation Setting Register 0N (Scr0Nh, Scr0Nl)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.4 Serial communication operation setting register 0n (SCR0nH, SCR0nL) The SCR0nH and SCR0nL registers are communication operation setting registers of channel n. It is used to set a data transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length.
Page 288 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-6. Format of Serial Communication Operation Setting Register 0n (SCR0nH, SCR0nL) (2/2) Address: F0119H (SCR00H) , F011BH (SCR01H) Address: F0118H (SCR00L) , F011AH (SCR01L) After reset: 00H After reset: 87H Symbol Symbol SCR0nH...
Page 289: Serial Data Register 0N (Sdr0Nh, Sdr0Nl)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.5 Serial data register 0n (SDR0nH, SDR0nL) The SDR0nH and SDR0nL registers are the transmit/receive data registers of channel n. The SDR0nH and SDR0nL registers are set by an 8-bit memory manipulation instruction. Reset signal generation clears the SDR0nH and SDR0nL registers to 00H.
Page 290: Serial Flag Clear Trigger Register 0N (Sir0N)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.6 Serial flag clear trigger register 0n (SIR0n) The SIR0n register is a trigger register that is used to clear each error flag of channel n. When each bit (FECT0n, PECT0n, OVCT0n) of this register is set to 1, the corresponding bit (FEF0n, PEF0n, OVF0n) of serial status register 0n (SSR0n) is cleared to 0.
Page 291: Serial Status Register 0N (Ssr0N)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.7 Serial status register 0n (SSR0n) The SSR0n register indicates the communication status and error occurrence status of channel n. The errors indicated by this register are framing errors, parity errors, and overrun errors.
Page 292 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-9. Format of Serial Status Register 0n (SSR0n) (2/2) Address: F0100H (SSR00) - F0102H (SSR01) , After reset: 0000H Symbol Note SSR0n TSF0n BFF0n FEF0n PEF0n OVF0n FEF0n Note Framing error detection flag of channel n No error occurs.
Page 293: Serial Channel Start Register 0 (Ss0)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.8 Serial channel start register 0 (SS0) The SS0 register is a trigger register that is used to enable communication/count for each channel. When 1 is written to a bit of this register (SS0n), the corresponding bit (SE0n) of serial channel enable status register 0 (SE0) is set to 1 (operation is enabled).
Page 294: Serial Channel Stop Register 0 (St0)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.9 Serial channel stop register 0 (ST0) The ST0 register is a trigger register that is used to enable stopping communication/count for each channel. When 1 is written to a bit of this register (ST0n), the corresponding bit (SE0n) of serial channel enable status register 0 (SE0) is cleared to 0 (operation is stopped).
Page 295: Serial Channel Enable Status Register 0 (Se0)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.10 Serial channel enable status register 0 (SE0) The SE0 register indicates whether the data transmission/reception operation of each channel is enabled or disabled. When 1 is written to a bit of serial channel start register 0 (SS0), the corresponding bit of this register is set to 1. When 1 is written to a bit of serial channel stop register 0 (ST0), the corresponding bit of this register is cleared to 0.
Page 296: Serial Output Enable Register 0 (Soe0)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.11 Serial output enable register 0 (SOE0) The SOE0 register is used to enable or disable output of the serial communication operation of each channel. If serial output is enabled for channel n, the value of the SO0n bit of serial output register 0 (SO0) cannot be rewritten by software, and a value is output from the serial data output pin according to the communication operation.
Page 297: Serial Output Register 0 (So0)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.12 Serial output register 0 (SO0) The SO0 register is a buffer register for serial output of each channel. The value of the SO0n bit of this register is output from the serial data output pin of channel n.
Page 298: Serial Clock Output Register (Cko0)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.13 Serial clock output register (CKO0) The CKO0 register is a buffer register for serial clock output of each channel. The value of the CKO0n bit of this register is output from the serial clock output pin of channel n.
Page 299: Serial Output Level Register 0 (Sol0)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.14 Serial output level register 0 (SOL0) The SOL0 register is used to set inversion of the data output level of channel 0. This register can be set only in the UART mode. Be sure to set 0 to corresponding bit in the CSI mode.
Page 300: Noise Filter Enable Register 0 (Nfen0)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.15 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin of UART. Disable the noise filter of the pin used for CSI communication, by clearing the corresponding bit of this register to 0.
Page 301: Input Switch Control Register (Isc)
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.16 Input switch control register (ISC) The ISC1 and ISC0 bits in the ISC register are used to handle the combination of the external interrupt and the timer array unit at the time of baud rate correction of UART0.
Page 302: Registers Controlling Port Functions Of Serial Input/Output Pins
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.3.17 Registers controlling port functions of serial input/output pins Using the serial array unit requires setting of the registers that control the port functions multiplexed on the target channel (port mode registers 0, 1 (PM0, PM1), port registers 0, 1 (P0, P1), port output mode registers 0, 1 (POM0, POM1), port mode control registers 0, 1 (PMC0, PMC1)).
Page 303: Operation Stop Mode
(PM0), port mode control register 0 (PMC0), and port register 0 (P0)). 2. Be sure to clear the following bits to 0. R7F0C806 and R7F0C807 products: Bits 1, 3, and 4 R7F0C808 and R7F0C809 products: Bits 1, 3, 4, and 6...
Page 304: Stopping The Operation By Channels
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 11-21. Each Register Setting When Stopping Operation by Channels (a) Serial channel stop register 0 (ST0) … This register is a trigger register that is used to enable stopping communication/count by each channel.
Page 305: Operation Of 3-Wire Serial I/O (Csi00) Communication
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.5 Operation of 3-Wire Serial I/O (CSI00) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception] ● Data length of 7 or 8 bits ●...
Page 306: Master Transmission
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.5.1 Master transmission Master transmission is that the R7F0C806-809 output a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0 Pins used SCK00, SO00 Interrupt...
Page 307: Register Setting
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-22. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n STS0n SIS0n0...
Page 308 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-22. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00) (2/2) (e) Serial output register 0 (SO0) … Sets only the bits of the target channel. Symbol: SO00 (f) Serial output enable register 0 (SOE0) … Sets only the bits of the target channel to 1.
Page 309 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-23. Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 310 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-24. Procedure for Stopping Master Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSF0n = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the ST0n bit of the target channel.
Page 311 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-25. Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop the communication target (slave) or communication operation (Essential) Slave ready? completed Disable data output and clock output of Port manipulation...
Page 312 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11-26. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0) SS0n ST0n SE0n SDR0nL Transmit data 1 Transmit data 2...
Page 313 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-27. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, see Figure 11-23. SAU default setting (Select Transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag...
Page 314 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11-28. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0) <1> SS0n <6> ST0n SE0n SDR0nL Transmit data 2...
Page 315 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-29. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting <1> For the initial setting, see Figure 11-23. SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag...
Page 316: Master Reception
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.5.2 Master reception Master reception is that the R7F0C806-809 output a transfer clock and receives data from other device. CSI00 3-Wire Serial I/O Target channel Channel 0 of SAU0 Pins used SCK00, SI00 Interrupt...
Page 317 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-30. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n STS0n SIS0n0...
Page 318 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-30. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00) (2/2) (f) Serial output enable register 0 (SOE0) … The register that not used in this mode. Symbol: SOE0 SOE00 ×...
Page 319: Operation Procedure
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-31. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPS0 register Set the operation clock.
Page 320 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-33. Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation Completing slave (Essential) completed preparations? Disable clock output of the target channel by setting a port register and a...
Page 321 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 11-34. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) SS0n ST0n SE0n Receive data 2 Receive data 3 Receive data 1...
Page 322 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-35. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, see Figure 11-31. SAU default setting (Select Transfer end interrupt) Setting storage area of the receive data, number of communication data...
Page 323 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 11-36. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) <1> SS0n <8> ST0n SE0n Receive data 3...
Page 324 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-37. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication For the initial setting, see Figure 11-31. buffer empty (Select interrupt) SAU default setting <1> Setting storage area of the receive data, number of communication data...
Page 325: Master Transmission/Reception
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.5.3 Master transmission/reception Master transmission/reception is that the R7F0C806-809 output a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0 Pins used SCK00, SI00, SO00...
Page 326 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-38. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol:SMR0nH Symbol:SMR0nL CKS0n CCS0n STS0n SIS0n0 MD0n1 MD0n0...
Page 327 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-38. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00) (2/2) (f) Serial output enable register 0 (SOE0) … Sets only the bits of the target channel to 1.
Page 328 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-39. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 329 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-40. Procedure for Stopping Master Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSF0n = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the ST0n bit of the target channel.
Page 330 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-41. Procedure for Resuming Master Transmission/Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation Completing slave (Essential) completed preparations? Disable data output and clock output of (Selective)
Page 331 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 11-42. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAP0n =0, CKP0n = 0) SS0n ST0n SE0n Receive data 2 Receive data 3 Receive data 1...
Page 332 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-43. Flowchart of Master Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication For the initial setting, see Figure 11-39. SAU default setting (Select transfer end interrupt) Setting storage data and number of data for transmission/reception data...
Page 333 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 11-44. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) <1> SS0n ST0n <8> SE0n Receive data 3...
Page 334 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-45. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, see Figure 11-39. <1> SAU default setting (Select buffer empty interrupt) Setting storage data and number of data for transmission/reception data...
Page 335: Slave Transmission
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.5.4 Slave transmission Slave transmission is that the R7F0C806-809 transmit data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0...
Page 336 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-46. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n STS0n SIS0n0...
Page 337 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-46. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00) (2/2) (f) Serial output enable register 0 (SOE0) … Sets only the bits of the target channel to 1.
Page 338 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-47. Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 339 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-48. Procedure for Stopping Slave Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSF0n = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the ST0n bit of the target channel.
Page 340 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-49. Procedure for Resuming Slave Transmission Starting setting for resumption Wait until stop the communication target Completing master (Essential) preparations? (master) Disable data output of the target channel by setting a port register and a port...
Page 341 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11-50. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0) SS0n ST0n SE0n SDR0nL Transmit data 1 Transmit data 2...
Page 342 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-51. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, see Figure 11-47. SAU default setting (Select transfer end interrupt) Set storage area and the number of data for transmit data...
Page 343 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11-52. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0) <1> SS0n ST0n <6> SE0n SDR0nL Transmit data 1...
Page 344 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-53. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, see Figure 11-47. <1> SAU default setting (Select buffer empty interrupt) Setting transmit data Set storage area and the number of data for transmit data...
Page 345: Slave Reception
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.5.5 Slave reception Slave reception is that the R7F0C806-809 receive data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0...
Page 346 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-54. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol:SMR0nH Symbol:SMR0nL CKS0n CCS0n STS0n SIS0n0 MD0n1 MD0n0...
Page 347 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-54. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00) (2/2) (f) Serial output enable register 0 (SOE0) … The Register that not used in this mode. Symbol: SOE0 SOE00 ×...
Page 348 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-55. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 349 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-57. Procedure for Resuming Slave Reception Starting setting for resumption Wait until stop the communication target (master) Completing master (Essential) preparations? Disable clock output of the target channel by setting a port register and a...
Page 350 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 11-58. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) SS0n ST0n SE0n Receive data 3 SDR0nL Receive data 1...
Page 351 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-59. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, see Figure 11-55. SAU default setting (Select transfer end interrupt only) Clear storage area setting and the number of receive data...
Page 352: Slave Transmission/Reception
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.5.6 Slave transmission/reception Slave transmission/reception is that the R7F0C806-809 transmit/receive data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0...
Page 353 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-60. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n STS0n SIS0n0...
Page 354 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-60. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00) (2/2) (f) Serial output enable register 0 (SOE0) … Sets only the bits of the target channel to 1.
Page 355 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-61. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPS0 register Set the operation clock.
Page 356 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-62. Procedure for Stopping Slave Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSF0n = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the ST0n bit of the target channel.
Page 357 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-63. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Wait until stop the communication target Completing master (Essential) (master) preparations? Disable data output of the target channel by setting a port register and a port...
Page 358 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 11-64. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) SS0n ST0n SE0n Receive data 1 Receive data 2 Receive data 3...
Page 359 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-65. Flowchart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication For the initial setting, see Figure 11-61. SAU default setting (Select Transfer end interrupt) Setting storage area and number of data for transmission/reception data...
Page 360 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 11-66. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) <1> SS0n <8> ST0n SE0n Receive data 3...
Page 361 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-67. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, see Figure 11-61. <1> SAU default setting (Select buffer empty interrupt) Setting storage area and number of data for transmission/reception data...
Page 362: Calculating Transfer Clock Frequency
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.5.7 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00) communication can be calculated by the following expressions. (1) Master (Transfer clock frequency) = {Operation clock (f ) frequency of the target channel} ÷ (SDR0nH[7:1] + 1) ÷ 2 [Hz]...
Page 363 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Table 11-2. Selection of Operation Clock For 3-Wire Serial I/O Note SMR0n SPS0 Register Operation Clock (f Register CKS0n = 20 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz...
Page 364: Procedure For Processing Errors That Occurred During 3-Wire Serial I/O (Csi00) Communication
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00) communication is described in Figure 11-68. Figure 11-68. Processing Procedure in Case of Overrun Error...
Page 365: Operation Of Uart (Uart0) Communication
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.6 Operation of UART (UART0) Communication This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception (RXD) lines. By using these two communication lines, each data frame, which consists of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 366: Uart Transmission
CHAPTER 11 SERIAL ARRAY UNIT 11.6.1 UART transmission UART transmission is an operation to transmit data from the R7F0C806-809 to another device asynchronously (start- stop synchronization). Of the two channels used for UART, the even-numbered channel is used for UART transmission.
Page 367: Register Setting
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-69. Example of Contents of Registers for UART Transmission (UART0) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n MD0n1 MD0n0 Interrupt source of channel n...
Page 368 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-69. Example of Contents of Registers for UART Transmission (UART0) (2/2) (e) Serial clock output register 0 (CKO0) … Sets only the bits of the target channel. Symbol: CKO0 CKO00 × (f) Serial output register 0 (SO0) … Sets only the bits of the target channel.
Page 369: Operation Procedure
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-70. Initial Setting Procedure for UART Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 370 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-71. Procedure for Stopping UART Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSF0n = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the ST0n bit of the target channel.
Page 371 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-72. Procedure for Resuming UART Transmission Starting setting for resumption Wait until stop the communication target Completing master (Essential) preparations? or communication operation completed Disable data output of the target channel (Selective) Port manipulation by setting a port register and a port mode register.
Page 372 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11-73. Timing Chart of UART Transmission (in Single-Transmission Mode) SS0n ST0n SE0n SDR0nL Transmit data 1 Transmit data 2 Transmit data 3 TXDq pin Transmit data 1...
Page 373 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-74. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication For the initial setting, see Figure 11-70 . SAU default setting (Select transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag...
Page 374 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11-75. Timing Chart of UART Transmission (in Continuous Transmission Mode) <1> SS0n <6> ST0n SE0n SDR0nL Transmit data 1 Transmit data 2 Transmit data 3 TXDq pin...
Page 375 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-76. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication For the initial setting, see Figure 11-70. <1> SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag...
Page 376: Uart Reception
CHAPTER 11 SERIAL ARRAY UNIT 11.6.2 UART reception UART reception is an operation wherein the R7F0C806-809 asynchronously receives data from another device (start- stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
Page 377 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-77. Example of Contents of Registers for UART Reception (UART0) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n STS0n SIS0n0 MD0n1 MD0n0 Note1 Note2...
Page 378 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-77. Example of Contents of Registers for UART Reception (UART0) (2/2) (e) Serial clock output register 0 (CKO0) … The register that not used in this mode. Symbol: CKO0 CKO00 × (f) Serial output register 0 (SO0) … The register that not used in this mode.
Page 379 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-78. Initial Setting Procedure for UART Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 380 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-80. Procedure for Resuming UART Reception Starting setting for resumption Completing master Stop the target for communication or wait (Essential) preparations? Re-set the register to change the operation (Selective) Changing setting of the SPS0 register clock setting.
Page 381: Processing Flow
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow Figure 11-81. UART Reception Timing Chart SS0n ST0n SE0n Receive data 3 SDR0nL Receive data 1 Receive data 2 RXDq pin Receive data 3 Receive data 2 Receive data 1 Shift...
Page 382 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-82. Flowchart of UART Reception Starting UART communication For the initial setting, see Figure 11-78. SAU default setting (setting to mask for error interrupt) Setting storage area of the receive data, number of communication...
Page 383: Calculating Baud Rate
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.6.3 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (f ) frequency of target channel} ÷ (SDR0nH[7:1] + 1) ÷ 2 [bps] Caution Setting serial data register 0n (SDR0nH) SDR0nH[7:1] = (0000000B, 0000001B) is prohibited.
Page 384 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT Table 11-3. Selection of Operation Clock For UART Note SMR0n SPS0 Register Operation Clock (f Register CKS0n = 20 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.2 kHz...
Page 385 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 386 R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 387: Procedure For Processing Errors That Occurred During Uart (Uart0) Communication
R7F0C806-809 CHAPTER 11 SERIAL ARRAY UNIT 11.6.4 Procedure for processing errors that occurred during UART (UART0) communication The procedure for processing errors that occurred during UART (UART0) communication is described in Figures 11-84 and 11-85. Figure 11-84. Processing Procedure in Case of Parity Error or Overrun Error...
Page 388: Chapter 12 Real-Time Output Controller (R7F0C806 And R7F0C807 Only)
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.1 Functions of Real-Time Output Controller The real-time output controller can control one DC motor or two stepper motors by using the PWM output function of the TAU.
Page 389: Configuration Of Real-Time Output Controller
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.2 Configuration of Real-Time Output Controller The real-time output controller includes the following hardware. Table 12-1. Configuration of Real-Time Output Controller Item Configuration Control registers RTO source selection register (RTOSRC)
Page 390: Rto Source Selection Register (Rtosrc)
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.3.1 RTO source selection register (RTOSRC) The RTOSRC register is used to select the source of the clock input to the real-time output controller. Select the TAU timer output TO01 or TO03 as the source clock to be input to the real-time output controller.
Page 391: Rto Forced Cutoff Control Register (Rtosht)
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.3.2 RTO forced cutoff control register (RTOSHT) The RTOSHT register is used to control whether to cut off the real-time output. The RTOSHT register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 392: Rto Control Register 0 (Rtooutc0)
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.3.3 RTO control register 0 (RTOOUTC0) The RTOOUTC0 register is used to enable or disable outputting the waveforms from RTIO00 to RTIO03 and control whether to invert their logic level.
Page 393: Rto Control Register 1 (Rtooutc1)
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.3.4 RTO control register 1 (RTOOUTC1) The RTOOUTC1 register is used to enable or disable outputting the waveforms from RTIO04 to RTIO07 and control whether to invert their logic level.
Page 394: Rto Forced Cutoff Output Selection Register (Rtocio)
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.3.5 RTO forced cutoff output selection register (RTOCIO) The RTOCIO register is used to select the status of the timer output that has forcibly been cut off. The RTOCIO register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 395: Rto Forced Cutoff Status Register (Rtostr)
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.3.6 RTO forced cutoff status register (RTOSTR) The RTOSTR register is used to clear the output cutoff state, and is used as a flag register that indicates the status of a cutoff signal.
Page 396: Registers Controlling The Port Function Of Real-Time Output Pins
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.3.7 Registers controlling the port function of real-time output pins When using the real-time output controller, specify the settings for port mode register 0 (PM0), port register 0 (P0), and port mode control register 0 (PMC0) that are used to control the port function shared by the real-time output pin (RTIO0n) For details about the registers that control the port function, see 4.3.1 Port mode registers 0, 1, 4 (PM0, PM1, PM4)
Page 397: Operations Of Real-Time Output Controller
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.4 Operations of Real-Time Output Controller 12.4.1 Initial setup Select a TAU output (TO01 or TO03) as the source of the timer waveform by using the RTOSRC register. Whether to invert or not to invert the timer waveform and whether to fix the level to low or high can be specified by using the RTOOUTC0 and RTOOUTC1 registers.
Page 398: Normal Operation
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.4.2 Normal operation The output waveform is not inverted, inverted, fixed to low level, or fixed to high level, according to the register settings. The settings of RTOOUTC0 and RTOOUTC1 can be changed during operation. Set the RTOSELn and RTOACTn bits at the same time.
Page 399 R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) Table 12-2. Operation of Cutoff Trigger Signal INTP0 RTOSHTn RTOSELn RTOACTn RTOSHTFLG RTOCIO RTIO0n Output Setting Not inverted Inverted Low level High level Not inverted Inverted Low level High level...
Page 400: Notes On Use
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.5 Notes on Use (1) Specify the setting in the RTOSRC register before the corresponding RTOSELn bit is set to 1 (enabling output). (2) Specify the setting in the RTOCIO register while the corresponding RTOSHTn bit is 0 (disabling forced cutoff).
Page 401: Example Of Controlling Brushless Dc Electric Motor
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.6 Example of Controlling Brushless DC Electric Motor 12.6.1 Overview This section describes an example of how blushless DC electric motors (BLDC motors) are controlled by using the real- time output (RTO) controller. For details about BLDC motor control, refer to the application note.
Page 402: Timing Of Controlling Three-Phase Bldc Motors
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.6.2 Timing of controlling three-phase BLDC motors Figure 12-12. Timing of Controlling Three-Phase BLDC Motors <1> <2> <3> <4> <5> <6> Carrier wave (sawtooth wave) Hall-effect sensor a Hall-effect sensor b...
Page 403: Flowchart Of Real-Time Output Initialization
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.6.3 Flowchart of real-time output initialization Figure 12-13 shows the flowchart of real-time output (RTO) initialization. Figure 12-13. Flowchart of RTO Initialization Start Set up PWM output from TAU Note 1 channel 1 Set up the ports.
Page 404: Register Setting Example
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.6.4 Register setting example The example below shows the setting for outputting a waveform that rotates BLDC motors in the forward direction by using the signals from RTIO00 to RTIO05 at the same time, by initializing the RTO source selection register (RTOSRC), RTO control register 0 (RTOOUTC0), and RTO control register 1 (RTOOUTC1).
Page 405: Example Of Controlling Stepper Motors
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.7 Example of Controlling Stepper Motors 12.7.1 Overview This section describes an example of how two 2-phase stepper motors are controlled by using eight real-time output (RTO) pins. For details about stepper motor control, refer to the application note.
Page 406: Controlling The Stepper Motors
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.7.3 Controlling the stepper motors Eight RTIO pins are used to rotate and stop stepper motors in the forward and reverse directions in 2-phase excitation mode. PWM mode of the TAU is used to control the rotation speed.
Page 407: Flowchart Of Rto Initialization
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.7.4 Flowchart of RTO initialization Figure 12-16 shows the flowchart of real-time output (RTO) initialization. Figure 12-16. Flowchart of RTO Initialization Start Specify PWM mode Note 1 of TAU RTOEN = 1...
Page 408: Register Settings
R7F0C806-809 CHAPTER 12 REAL-TIME OUTPUT CONTROLLER (R7F0C806 and R7F0C807 only) 12.7.5 Register settings Table 12-6. Example Settings for Registers That Control Stepper Motor 1 State Value Set to RTOSRC Value Set to RTOOUTC0 Value Set to RTOOUTC1 <1> 0x00 0x40 0x40 <2>...
Page 409: Chapter 13 Interrupt Functions
The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. The number of interrupt sources differs, depending on the product. R7F0C806, R7F0C807 Products R7F0C808, R7F0C809 Products Maskable interrupts...
Page 410 R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS Table 13-1. Interrupt Source List Interrupt Source Name Trigger INTWDTI Watchdog timer interval Internal 0004H (75% of overflow time +3/(4 × f INTP0 Pin input edge detection External 0006H INTP1 0008H INTST0/ UART0 transmission transfer end or buffer empty interrupt/CSI00...
Page 411 R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-1. Basic Configuration of Interrupt Function (1/2) (a) Internal maskable interrupt Internal bus ISP1 ISP0 Vector table Interrupt Priority controller address generator request Standby release signal (b) External maskable interrupt (INTPn) Internal bus External interrupt edge...
Page 412 R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-1. Basic Configuration of Interrupt Function (2/2) (c) External maskable interrupt (INTKR) Internal bus Key interrupt mode ISP1 ISP0 control register (KRM0) KRMn Vector table Priority controller interrupt address generator KRn pin input detector...
Page 413: Registers Controlling Interrupt Functions
R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS 13.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. ● Interrupt request flag registers (IF0L, IF0H, IF1L) ● Interrupt mask flag registers (MK0L, MK0H, MK1L) ● Priority specification flag registers (PR00L, PR00H, PR10L, PR10H, PR01L, PR11L) ●...
Page 414: Interrupt Request Flag Registers (If0L, If0H, If1L)
R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS 13.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when the interrupt request is acknowledged, a reset signal is generated, or an instruction is executed.
Page 415: Interrupt Mask Flag Registers (Mk0L, Mk0H, Mk1L)
R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS 13.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. The MK0L, MK0H, and MK1L registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.
Page 416: Priority Specification Flag Registers (Pr00L, Pr00H, Pr10L, Pr10H, Pr01L, Pr11L)
R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS 13.3.3 Priority specification flag registers (PR00L, PR00H, PR10L, PR10H, PR01L, PR11L) The priority specification flag registers are used to set the priority level of the corresponding maskable interrupt. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L).
Page 417: External Interrupt Falling Edge Enable Register 0 (Egn0)
R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS 13.3.4 External interrupt rising edge enable register 0 (EGP0), external interrupt falling edge enable register 0 (EGN0) These registers specify the valid edge for INTP0 to INTP5. The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 418: Program Status Word (Psw)
R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS 13.3.5 Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW.
Page 419: Interrupt Servicing Operations
R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS 13.4 Interrupt Servicing Operations 13.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt servicing is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 420 R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-7. Interrupt Request Acknowledgment Processing Algorithm Start xxIF = 1? Yes (interrupt request generation) xxMK = 0? Interrupt request held pending No (Low priority) (xxPR 1, xx < (ISP1, ISP0) Interrupt request held pending...
Page 421: Software Interrupt Request Acknowledgment
R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-8. Interrupt Request Acknowledgment Timing (Minimum Time) 8 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction Instruction Instruction jump to interrupt program servicing xxIF 11 clocks Remark 1 clock: 1/f : CPU clock) Figure 13-9.
Page 422 R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS Table 13-4. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Maskable Interrupt Request Software Request Interrupt Priority Level 0 Priority Level 1 Priority Level 2 Priority Level 3 Request...
Page 423 R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz...
Page 424 R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 00) INTxx...
Page 425: Interrupt Request Hold
R7F0C806-809 CHAPTER 13 INTERRUPT FUNCTIONS 13.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 426: Chapter 14 Key Interrupt Function
R7F0C806-809 CHAPTER 14 KEY INTERRUPT FUNCTION CHAPTER 14 KEY INTERRUPT FUNCTION 14.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a rising edge/falling edge to the key interrupt input pins (KR0 to KR7).
Page 427 R7F0C806-809 CHAPTER 14 KEY INTERRUPT FUNCTION Figure 14-1. Block Diagram of Key Interrupt KRF0 KREG KRM00 KRMD KRF1 KREG KRM01 KRMD KRF2 KREG KRM02 KRMD KRF3 KRM03 KREG KRMD KRF4 KREG KRM04 INTKR KRMD KRF5 KREG KRM05 KRMD KRF6 KREG...
Page 428: Register Controlling Key Interrupt
R7F0C806-809 CHAPTER 14 KEY INTERRUPT FUNCTION 14.3 Register Controlling Key Interrupt The key interrupt function is controlled by the following five registers: ● Key return control register (KRCTL) ● Key return mode register (KRM0) ● Key return flag register (KRF) ●...
Page 429: Key Return Mode Register (Krm0)
R7F0C806-809 CHAPTER 14 KEY INTERRUPT FUNCTION 14.3.2 Key return mode register (KRM0) This register sets the key interrupt mode. The KRM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
Page 430: Key Return Flag Register (Krf)
R7F0C806-809 CHAPTER 14 KEY INTERRUPT FUNCTION 14.3.3 Key return flag register (KRF) This register controls the key return flags (KRF0 to KRF7). The KRF register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 431: Key Interrupt Operation
R7F0C806-809 CHAPTER 14 KEY INTERRUPT FUNCTION 14.4 Key Interrupt Operation 14.4.1 When not using the key interrupt flag (KRMD = 0) A key interrupt (INTKR) is generated when the valid edge specified by the setting of the KREG bit is input to a key interrupt pin (KR0 to KR7).
Page 432: When Using The Key Interrupt Flag (Krmd = 1)
R7F0C806-809 CHAPTER 14 KEY INTERRUPT FUNCTION 14.4.2 When using the key interrupt flag (KRMD = 1) A key interrupt (INTKR) is generated when the valid edge specified by the setting of the KREG bit is input to a key interrupt pin (KR0 to KR7). The channels to which the valid edge was input can be identified by reading the key return flag register (KRF) after the key interrupt (INTKR) is generated.
Page 433 R7F0C806-809 CHAPTER 14 KEY INTERRUPT FUNCTION The operation when a valid edge is input to multiple key interrupt input pins is shown in Figure 14-8 below. A falling edge is also input to the KR1 and KR5 pins after a falling edge was input to the KR0 pin (when KREG = 0). The KRF1 bit is set when the KRF0 bit is cleared.
Page 434: Chapter 15 Standby Function
R7F0C806-809 CHAPTER 15 STANDBY FUNCTION CHAPTER 15 STANDBY FUNCTION 15.1 Overview The standby function reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high- speed on-chip oscillator is operating before the HALT mode is set, oscillation of clock continues.
Page 435: Standby Function Operation
External interrupt Key interrupt function Note R7F0C806 and R7F0C807 products only. Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode. Operation disabled: Operation is stopped before switching to the HALT mode. High-speed on-chip oscillator clock Low-speed on-chip oscillator clock R01UH0481EJ0140 Rev.1.40...
Page 436 R7F0C806-809 CHAPTER 15 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 437: Stop Mode
Clock output/buzzer output Operation disabled A/D converter Operation disabled Serial array unit (SAU) Selectable power-on-reset Operable function External interrupt Key interrupt function Note R7F0C806 and R7F0C807 products only. (Cautions and Remark are listed on the next page.) R01UH0481EJ0140 Rev.1.40 Apr 10, 2018...
Page 438 R7F0C806-809 CHAPTER 15 STANDBY FUNCTION Cautions 1. To use the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2. To stop the low-speed on-chip oscillator clock in the STOP mode, must previously be set an option byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H = Remark Operation stopped: Operation is automatically stopped before switching to the STOP mode.
Page 439 R7F0C806-809 CHAPTER 15 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
Page 440: Chapter 16 Reset Function
R7F0C806-809 CHAPTER 16 RESET FUNCTION CHAPTER 16 RESET FUNCTION The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of selectable power-on-reset (SPOR) circuit...
Page 441 R7F0C806-809 CHAPTER 16 RESET FUNCTION R01UH0481EJ0140 Rev.1.40 Apr 10, 2018...
Page 442: Timing Of Reset Operation
R7F0C806-809 CHAPTER 16 RESET FUNCTION 16.1 Timing of Reset Operation This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level on the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts.
Page 443 R7F0C806-809 CHAPTER 16 RESET FUNCTION Release from the reset state is automatic in the cases of a reset due to the watchdog timer overflow or a reset due to the execution of an illegal instruction. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts.
Page 444: Operation States During Reset Periods
Operation stopped Key interrupt function Notes 1. R7F0C806 and R7F0C807 products only. Statuses of P40 and P125 pins are as follows ● P40: High-impedance during external reset period or reset period by the data retention power supply voltage. High level during other types of reset period or after receiving a reset (connected to the internal pull-up resistor).
Page 445 R7F0C806-809 CHAPTER 16 RESET FUNCTION Table 16-2. State of Hardware After Acceptance of Reset Hardware After Acceptance of Reset Note Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW)
Page 446: Register For Confirming Reset Source
R7F0C806-809 CHAPTER 16 RESET FUNCTION 16.3 Register for Confirming Reset Source 16.3.1 Reset control flag register (RESF) Many internal reset generation sources exist in the RL78 Microcontroller. The reset control flag register (RESF) is used to store which source has generated the reset request.
Page 447 R7F0C806-809 CHAPTER 16 RESET FUNCTION The RESF register is automatically cleared when it is read by an 8-bit memory manipulation instruction. Figure 16-6 shows the procedure for checking the reset source. Figure 16-6. Procedure for Checking Reset Source After receiving a reset...
Page 448: Chapter 17 Selectable Power-On-Reset Circuit
R7F0C806-809 CHAPTER 17 SELECTABLE POWER-ON-RESET CIRCUIT CHAPTER 17 SELECTABLE POWER-ON-RESET CIRCUIT 17.1 Functions of Selectable Power-on-reset Circuit The selectable power-on-reset (SPOR) circuit has the following functions. ● Generates internal reset signal at power on. The reset signal is released when the supply voltage exceeds the detection voltage (V ≥...
Page 449: Configuration Of Selectable Power-On-Reset Circuit
R7F0C806-809 CHAPTER 17 SELECTABLE POWER-ON-RESET CIRCUIT 17.2 Configuration of Selectable Power-on-reset Circuit The block diagram of the selectable power-on-reset circuit is shown in Figure 17-1. Figure 17-1. Block Diagram of Selectable Power-on-reset Circuit Internal reset signal Option byte (000C1H) Reference...
Page 450: Operation Of Selectable Power-On-Reset Circuit
R7F0C806-809 CHAPTER 17 SELECTABLE POWER-ON-RESET CIRCUIT 17.3 Operation of Selectable Power-on-reset Circuit Specify the voltage detection level by using the option byte 000C1H. The internal reset signal is generated at power on. The internal reset status is retained until the supply voltage (V ) exceeds the voltage detection level (V ).
Page 451: Cautions For Selectable Power-On-Reset Circuit
R7F0C806-809 CHAPTER 17 SELECTABLE POWER-ON-RESET CIRCUIT 17.4 Cautions for Selectable Power-on-reset Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the SPOR detection voltage ), the system may be repeatedly reset and released from the reset status. In this case, the time from release...
Page 452: Chapter 18 Option Byte
CHAPTER 18 OPTION BYTE 18.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory of the R7F0C806-809 form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).
Page 453: Format Of User Option Byte
R7F0C806-809 CHAPTER 18 OPTION BYTE 18.2 Format of User Option Byte The format of user option byte is shown below. Figure 18-1. Format of User Option Byte (000C0H) Address: 000C0H WDTON WDCS2 WDCS1 WDCS0 WDSTBYON WDTON Operation control of watchdog timer counter...
Page 454 R7F0C806-809 CHAPTER 18 OPTION BYTE Figure 18-2. Format of User Option Byte (000C1H) Address: 000C1H PORTSELB SPORS1 SPORS0 ● Setting of SPOR detection voltage Detection voltage Option byte setting value Rising edge Falling edge SPORS1 SPORS0 4.28 V 4.00 V 2.90 V...
Page 455: Format Of On-Chip Debug Option Byte
R7F0C806-809 CHAPTER 18 OPTION BYTE 18.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 18-4. Format of On-chip Debug Option Byte (000C3H) Address: 000C3H OCDENSET OCDENSET Control of on-chip debug operation Disables on-chip debug operation.
Page 456: Setting Of Option Byte
R7F0C806-809 CHAPTER 18 OPTION BYTE 18.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the link option in addition to describing to the source. When doing so, the contents set by using the link option take precedence, even if descriptions exist in the source, as mentioned below.
Page 457: Chapter 19 Flash Memory
R7F0C806-809 CHAPTER 19 FLASH MEMORY CHAPTER 19 FLASH MEMORY The RL78 microcontroller incorporates the flash memory to which a program can be written, erased, and overwritten. Caution The operating voltage during flash memory programming must be in the range from 4.5 V to 5.5 V.
Page 458: Serial Programming By Using Flash Memory Programmer
Remark FL-PR5 and FA series are products of Naito Densei Machida Mfg. Co., Ltd. Table 19-1. Wiring Between R7F0C806-809 and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Programmer Pin Name of Pin No.
Page 459: Programming Environment
R7F0C806-809 CHAPTER 19 FLASH MEMORY 19.1.1 Programming environment The environment required for writing a program to the flash memory of the RL78 microcontroller is illustrated below. Figure 19-1. Environment for Writing Program to Flash Memory PG-FP5, FL-PR5 RS-232C RESET Dedicated flash...
Page 460: Writing To Flash Memory By Using External Device (That Incorporates Uart)
R7F0C806-809 CHAPTER 19 FLASH MEMORY 19.2 Writing to Flash Memory by Using External Device (That Incorporates UART) On-board data writing to the internal flash memory is possible by using the RL78 microcontroller and an external device (a microcontroller or ASIC) connected to a UART.
Page 461: Connection Of Pins On Board
R7F0C806-809 CHAPTER 19 FLASH MEMORY 19.3 Connection of Pins on Board To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
Page 462: Port Pins
R7F0C806-809 CHAPTER 19 FLASH MEMORY 19.3.3 Port pins In the flash memory programming mode, all the pins not used for flash memory programming enter the same status as that immediately after reset. If an external device connected to the ports does not recognize the port status immediately...
Page 463: Serial Programming Method
R7F0C806-809 CHAPTER 19 FLASH MEMORY 19.4 Serial Programming Method 19.4.1 Serial programming procedure The following figure illustrates the procedure to rewrite the contents of the code flash memory by serial programming. Figure 19-6. Code Flash Memory Manipulation Procedure Start Flash memory programming...
Page 464: Flash Memory Programming Mode
R7F0C806-809 CHAPTER 19 FLASH MEMORY 19.4.2 Flash memory programming mode To rewrite the contents of the code flash memory by serial programming, the flash memory programming mode must be entered. <When performing serial programming by using the dedicated flash memory programmer>...
Page 465: Communication Mode
R7F0C806-809 CHAPTER 19 FLASH MEMORY 19.4.3 Communication mode Communication mode of the RL78 microcontroller is as follows. Table 19-4. Communication Mode Communication Standard Setting Note 1 Pin Used Mode Port Speed Note 2 Frequency Multiply Rate 1-line mode UART 115200 bps TOOL0 –...
Page 466: Chapter 20 On-Chip Debug Function
Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
Page 467 R7F0C806-809 CHAPTER 20 ON-CHIP DEBUG FUNCTION For the target system which uses the multi-use feature of RESET pin, its connection to an external circuit should be isolated. Figure 20-2. Connection Example of E1 On-chip Debugging Emulator and R7F0C80112ESP, R7F0C80212ESP (When using to the alternative function of RESET pin)
Page 468: On-Chip Debug Security Id
To perform communication between the RL78 microcontroller and E1 on-chip debugging emulator, as well as each debug function, the securing of memory space must be done beforehand. If Renesas Electronics assembler or compiler is used, the items can be set by using linker options. (1) Securement of memory space The shaded portions in Figure 20-3 are the areas reserved for placing the debug monitor program, so user programs or data cannot be allocated in these spaces.
Page 469 R7F0C806-809 CHAPTER 20 ON-CHIP DEBUG FUNCTION Figure 20-3. Memory Spaces Where Debug Monitor Programs Are Allocated Code flash memory Internal RAM Use prohibited SFR area Note 1 FFEDFH 4 bytes Note 3 FFEDCH 000D8H Stack area for debugging Debug monitor area...
Page 470: Chapter 21 Bcd Correction Circuit
R7F0C806-809 CHAPTER 21 BCD CORRECTION CIRCUIT CHAPTER 21 BCD CORRECTION CIRCUIT 21.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/subtracting the BCD correction result register (BCDADJ).
Page 471: Bcd Correction Circuit Operation
R7F0C806-809 CHAPTER 21 BCD CORRECTION CIRCUIT 21.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1>...
Page 472 R7F0C806-809 CHAPTER 21 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register.
Page 473: Chapter 22 Instruction Set
R7F0C806-809 CHAPTER 22 INSTRUCTION SET CHAPTER 22 INSTRUCTION SET This chapter lists the instructions for the RL78-S1 core of the RL78 microcontroller. For details of each operation and operation code, see the separate document RL78 Microcontrollers User’s Manual: software (R01US0015).
Page 474: Conventions Used In Operation List
R7F0C806-809 CHAPTER 22 INSTRUCTION SET 22.1 Conventions Used in Operation List 22.1.1 Operand identifiers and specification methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (see the assembler specifications for details). When there are two or more description methods, select one of them.
Page 475: Description Of Operation Column
R7F0C806-809 CHAPTER 22 INSTRUCTION SET 22.1.2 Description of operation column The operation when the instruction is executed is shown in the “Operation” column using the following symbols. Table 22-2. Symbols in “Operation” Column Symbol Function A register; 8-bit accumulator X register...
Page 476: Description Of Flag Operation Column
R7F0C806-809 CHAPTER 22 INSTRUCTION SET 22.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols. Table 22-3. Symbols in “Flag” Column Symbol Change of Flag Value...
Page 477: Operation List
R7F0C806-809 CHAPTER 22 INSTRUCTION SET 22.2 Operation List Table 22-5. Operation List (1/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit data r, #byte – r ← byte transfer × × × PSW, #byte –...
Page 478 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (2/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit data A, sfr – A ← sfr transfer sfr, A – sfr ← A A, [DE] A ←...
Page 479 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (3/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit data A, [HL+B] A ← (HL + B) transfer [HL+B], A – (HL + B) ← A A, ES:[HL+B] A ←...
Page 480 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (4/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit data A, [HL+B] – A ←→ (HL+B) transfer A, ES:[HL+B] – A ←→ ((ES, HL)+B) A, [HL+C] –...
Page 481 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (5/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 16-bit MOVW AX, [DE] AX ← (DE) data [DE], AX – (DE) ← AX transfer AX, ES:[DE] AX ←...
Page 482 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (6/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 16-bit MOVW BC, !addr16 BC ← (addr16) data BC, ES:!addr16 BC ← (ES, addr16) transfer DE, !addr16 DE ←...
Page 483 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (7/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit ADDC A, #byte – A, CY ← A+byte+CY × × × operation saddr, #byte –...
Page 484 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (8/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit SUBC A, #byte – A, CY ← A – byte – CY × × ×...
Page 485 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (9/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit A, #byte – A ← A⋁ byte × operation saddr, #byte – (saddr) ← (saddr)⋁ byte ×...
Page 486 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (10/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit A, #byte – A – byte × × × operation !addr16, #byte (addr16) – byte ×...
Page 487 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (11/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 16-bit ADDW AX, #word – AX, CY ← AX+word × × × operation AX, AX –...
Page 488 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (12/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY Increment/ – r ← r+1 × × decrement !addr16 – (addr16) ← (addr16)+1 × × ES:!addr16 –...
Page 489 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (13/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY Rotate A, 1 – (CY, A ← A ← A )×1 × A, 1 – (CY, A ←...
Page 490 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (14/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY XOR1 CY, A.bit – CY ← CY ∨A.bit × manipulate CY ← CY ∨PSW.bit CY, PSW.bit –...
Page 491 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (15/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY Call/ CALL – (SP – 2) ← (PC+2) , (SP – 3) ← (PC+2) return (SP – 4) ← (PC+2) , PC ←...
Page 492 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (16/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 Z AC CY Stack PUSH – (SP – 1) ← PSW, (SP – 2) ← 00H, manipulate SP ← SP–2 –...
Page 493 R7F0C806-809 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (17/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY Conditional saddr.bit, $addr20 Note3 – PC ← PC + 4 + jdisp8 if (saddr).bit = 0...
Page 494: Chapter 23 Electrical Specifications
Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
Page 495: Absolute Maximum Ratings
+ 0.3 Output voltage Note 1 –0.3 to V + 0.3 Output current, high Per pin P00 to P05 R7F0C806, R7F0C807 –40 R7F0C808, R7F0C809 –130 P06, P07, P10 to P16, P40 –40 Total of all P00 to P05 R7F0C806, R7F0C807 –70...
Page 496: Oscillator Characteristics
R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS 23.2 Oscillator Characteristics 23.2.1 On-chip oscillator characteristics = –40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator oscillation 1.25 frequency...
Page 497: Dc Characteristics
R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS 23.3 DC Characteristics 23.3.1 Pin characteristics of R7F0C806 and R7F0C807 = –40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, Per pin for –10...
Page 498: Pin Characteristics Of R7F0C808 And R7F0C809
R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS 23.3.2 Pin characteristics of R7F0C808 and R7F0C809 = –40 to +85°C, 4.5 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, Total of all pins (When duty ≤ 70%) –160...
Page 499 R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS Notes 5. Specification under conditions where (t1/t2*100%) ≤ 45%. The output current when the condition changes to a value in the range of (t1/t2*100%) > 45% can be calculated from the following expression (after replacing (t1/t2*100%) with n%).
Page 500: Common Items
R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS 23.3.3 Common items = –40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high 0.8 V Input voltage, low 0.2 V...
Page 501: Supply Current Characteristics
R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS 23.3.4 Supply current characteristics = –40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1 Operating Supply current Basic operation = 20 MHz = 3.0 V, 5.0 V...
Page 502: Ac Characteristics
R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS 23.4 AC Characteristics = –40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum Main system clock (f 2.7 V ≤ V ≤...
Page 503 R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS AC Timing Test Points Test points TI/TO Timing TI00 to TI03 TO00 to TO03 RESET Input Timing RESET R01UH0481EJ0140 Rev.1.40 Apr 10, 2018...
Page 504: Serial Interface Characteristics
R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS 23.5 Serial Interface Characteristics AC Timing Test Points Test points 23.5.1 Serial array unit (1) UART mode (dedicated baud rate generator output) = –40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V)
Page 505 R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS (2) CSI mode (master mode, SCKp...internal clock output) = –40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time ≥ 4/f 2.7 V ≤...
Page 506 R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS (3) CSI mode (slave mode, SCKp…external clock input) = –40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time 2.7 V ≤ V ≤...
Page 507 R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS CSI mode connection diagram SCK00 RL78 SI00 User's device microcontroller SO00 CSI mode serial transfer timing (When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1.) KCY1, 2 KL1, 2...
Page 508: Analog Characteristics
R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS 23.6 Analog Characteristics 23.6.1 A/D converter characteristics (Target ANI pin: ANI0 to ANI7) = –40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit...
Page 509: Spor Circuit Characteristics
R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS 23.6.2 SPOR circuit characteristics = –40 to +85°C, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection supply voltage Power supply rise time 4.28 4.45 SPOR0 Power supply fall time 4.00 Power supply rise time 2.90...
Page 510: Flash Memory Programming Characteristics
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. When using flash memory programmer. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 23.8 Dedicated Flash Memory Programmer Communication (UART) °C ≤...
Page 511: Timing Of Entry To Flash Memory Programming Modes
R7F0C806-809 CHAPTER 23 ELECTRICAL SPECIFICATIONS 23.9 Timing of Entry to Flash Memory Programming Modes Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication SPOR reset must be released before the SUINIT for the initial setting after the external external reset is released.
Page 512: Chapter 24 Package Drawings
1” and “ 2” 0.10 0.10 2.Dimension “ ” does not include tr 1.15 0.65 0.12 0.10 0.22 0.05 0.05 0.15 0.02 0.50 0.20 0.10 0 to 10 2012 Renesas Electronics Corporation. All rights reserved. R01UH0481EJ0140 Rev.1.40 Apr 10, 2018...
Page 513 R7F0C806-809 CHAPTER 24 PACKAGE DRAWINGS R7F0C80762ESN, R7F0C80962ESN, R7F0C80662ESN, R7F0C80862ESN JEITA Package code RENESAS code Previous code MASS(TYP.)[g] P-SOP20-7.5x12.8-1.27 PRSP0020DP-A T20MR-127-PAB 0.54 detail of lead end θ Dimension in Millimeters Referance Symbol Terminal cross section 12.80 12.60 13.00 7.30 7.50 7.70 2.25...
Page 514: Appendix A Revision History
R7F0C806-809 APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY A.1 Major Revisions in This Edition (1/1) Page Description Classification Throughout – Deletion of product specifications of R7F0C80762ESM, R7F0C80762DSM, R7F0C80962ESM, R7F0C80962DSM, R7F0C80662ESM, R7F0C80662DSM, R7F0C80862ESM and R7F0C80862DSM Remark “Classification” in the above table classifies revisions as follows.
Page 515: Revision History Of Preceding Editions
SPECIFICATIONS Change of conditions in 23.3.1 Pin characteristics of R7F0C806 and R7F0C807 Addition of notes 3 and 4 in 23.3.1 Pin characteristics of R7F0C806 and R7F0C807 Change of conditions in 23.3.2 Pin characteristics of R7F0C808 and R7F0C809 Addition of notes 3, 4, and 5 in 23.3.2 Pin characteristics of R7F0C808 and R7F0C809 Addition of package drawing in 24.1 20-Pin Products...
Page 516 (2/2) Edition Description Chapter Rev.1.10 Change of Figure 1-1. Part Number, Memory Size, and Package of R7F0C806-809 CHAPTER 1 OUTLINE Change of Table 3-5. Extended SFR (2nd SFR) List (1/2) CHAPTER 3 CPU ARCHITECTURE Change of Figure 10-1. Block Diagram of A/D Converter...
Page 517 R7F0C806-809 User’s Manual: Hardware Publication Date: Rev.1.00 Mar 26, 2014 Rev.1.40 Apr 10, 2018 Published by: Renesas Electronics Corporation...
Page 518 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. Tel: +1-408-432-8888, Fax: +1-408-434-5351 Renesas Electronics Canada Limited 9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3...
Page 519 R7F0C806-809 R01UH0481EJ0140...

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