Renesas R7F0C011B User Manual
Renesas R7F0C011B User Manual

Renesas R7F0C011B User Manual

8-bit single-chip microcontrollers
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R7F0C011B, R7F0C012B,
R7F0C013B
8
8-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
User's Manual: Hardware
Rev.0.01 Sep 2012
-Preliminary-

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Summary of Contents for Renesas R7F0C011B

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
  • Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
  • Page 4 #pragma sfr directive in the compiler. • To know details of the R7F0C011B, R7F0C012B, R7F0C013B Microcontroller instructions: → Refer to the separate document 78K0 Series Instructions User’s Manual (U12326E).
  • Page 5 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. R7F0C011B, R7F0C012B, R7F0C013B User’s Manual This manual 78K/0 Series Instructions User’s Manual U12326E 78K0/Kx2 Flash Memory Programming (Programmer) Application Note...
  • Page 6 Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual” website (http://www.renesas.com/prod/package/manual/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing.
  • Page 7: Table Of Contents

    CONTENTS CHAPTER 1 OUTLINE..........................1 Features ............................1 Applications..........................2 Ordering Information ........................2 Pin Configuration (Top View)..................... 3 Pin Identification ......................... 4 Block Diagram ..........................5 Outline of Functions ........................6 CHAPTER 2 PIN FUNCTIONS ......................... 8 Pin Function List ......................... 8 Description of Pin Functions ....................
  • Page 8 3.4.3 Direct addressing.......................... 46 3.4.4 Short direct addressing ......................... 47 3.4.5 Special function register (SFR) addressing................... 48 3.4.6 Register indirect addressing ......................49 3.4.7 Based addressing ......................... 50 3.4.8 Based indexed addressing......................51 3.4.9 Stack addressing .......................... 52 CHAPTER 4 PORT FUNCTIONS ......................53 Port Functions ...........................
  • Page 9 Functions of 16-Bit Timer/Event Counter 00 ................ 110 Configuration of 16-Bit Timer/Event Counter 00..............111 Registers Controlling 16-Bit Timer/Event Counter 00 ............117 Operation of 16-Bit Timer/Event Counter 00 ................ 125 6.4.1 Interval timer operation ....................... 125 6.4.2 Square-wave output operation....................128 6.4.3 External event counter operation ....................
  • Page 10 10.2 Configuration of Watchdog Timer ..................235 10.3 Register Controlling Watchdog Timer .................. 236 10.4 Operation of Watchdog Timer....................237 10.4.1 Controlling operation of watchdog timer..................237 10.4.2 Setting overflow time of watchdog timer ..................238 10.4.3 Setting window open period of watchdog timer................239 CHAPTER 11 A/D CONVERTER ......................
  • Page 11 15.2 Configuration of Serial Interface IIC0..................344 15.3 Registers to Control Serial Interface IIC0 ................347 15.4 I C Bus Mode Functions ......................360 15.4.1 Pin configuration ......................... 360 15.5 I C Bus Definitions and Control Methods ................361 15.5.1 Start conditions ........................... 361 15.5.2 Addresses...........................
  • Page 12 19.3 Operation of Power-on-Clear Circuit..................457 19.4 Cautions for Power-on-Clear Circuit ..................460 CHAPTER 20 LOW-VOLTAGE DETECTOR ..................462 20.1 Functions of Low-Voltage Detector..................462 20.2 Configuration of Low-Voltage Detector ................462 20.3 Registers Controlling Low-Voltage Detector ............... 463 20.4 Operation of Low-Voltage Detector..................466 20.4.1 When used as reset ........................
  • Page 13 CHAPTER 26 CAUTIONS FOR WAIT....................531 26.1 Cautions for Wait........................531 26.2 Peripheral Hardware That Generates Wait ................532...
  • Page 14: Chapter 1 Outline

    R01UH0408EJ0001 R7F0C011B, R7F0C012B, R7F0C013B Rev.0.01 RENESAS MCU Sep 25, 2012 CHAPTER 1 OUTLINE 1.1 Features μ Minimum instruction execution time: 0.2 s (@ 10 MHz operation with high-speed system clock) General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
  • Page 15: Applications

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE 1.2 Applications Household electrical appliances • Air conditioners 1.3 Ordering Information Pin Count Package Semiconductor Material Part Number 32-pin plastic LQF (7 × 7) 32-pin 16 KB 768 B Lead free product R7F0C011B2DFP (External pin finish is Ni/Pd/Au plating)
  • Page 16: Pin Configuration (Top View)

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 32-pin plastic LQFP (fine pitch) (7 × 7) Exposed die pad 24 23 22 21 20 19 18 17 P23/ANI3 P22/ANI2 P31/INTP2 P21/ANI1 P32/INTP3 P20/ANI0 P01/TI010/TO00 P00/TI000 P33/TI51/TO51/INTP4...
  • Page 17: Pin Identification

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE 1.5 Pin Identification ANI0 to ANI3: Analog input RxD0, RxD6: Receive data EXCLK: External clock input SCK10: Serial clock Input/output EXLVI: External potential input SCL0: Serial clock Input/output for Low-voltage detector SDA0: Serial data Input/output...
  • Page 18: Block Diagram

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 16-bit timer/ Port 0 P00, P01 event counter 00 TI000/P00 RxD6/P14 (LINSEL) Port 1 P10 to P17 8-bit timer H0 Port 2 P20 to P23 TOH1/P16 8-bit timer H1 Port 3...
  • Page 19: Outline Of Functions

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE 1.7 Outline of Functions Products R7F0C011B2DFP R7F0C012B2DFP R7F0C013B2DFP Item Flash memory (KB) High-speed RAM (KB) 0.75 Power supply voltage = 4.0 to 5.5 V Regulator Provided μ Minimum instruction execution s (10 MHz: V = 4.0 to 5.5 V)
  • Page 20 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE An outline of the timer is shown below. 16-Bit Timer/ 8-Bit Timer/ 8-Bit Timers H0 and H1 Watch Timer Watchdog Event Counter 00 Event Counters Timer 50 and 51 TM00 TM50 TM51 TMH0 TMH1 −...
  • Page 21: Chapter 2 Pin Functions

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List Pin I/O buffer power supplies include one V system. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies (AV...
  • Page 22 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS (1) Port functions Function Name Function After Reset Alternate Function Port 0. Input port TI000 2-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
  • Page 23 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS (2) Non-port functions Function Name Function After Reset Alternate Function ANI0 to ANI3 Input A/D converter analog input Analog P20 to P23 input EXLVI Input Potential input for external low-voltage detection Input port P120/INTP0 −...
  • Page 24: Description Of Pin Functions

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00, P01 (port 0) P00 and P01 function as an I/O port. These pins also function as timer I/O. The following operation modes can be specified in 1-bit units.
  • Page 25 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS (2) Control mode P10 to P17 function as serial interface data I/O, clock I/O, and timer I/O. (a) SI10 This is a serial data input pin of serial interface CSI10. (b) SO10 This is a serial data output pin of serial interface CSI10.
  • Page 26: P20 To P23 (Port 2)

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS 2.2.3 P20 to P23 (port 2) P20 to P23 function as an I/O port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units.
  • Page 27: P40 And P41 (Port 4)

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS 2.2.5 P40 and P41 (port 4) P40 and P41 function as an I/O port. P40 and P41 can be set to input or output port in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
  • Page 28: P120 To P122 (Port 12)

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS 2.2.8 P120 to P122 (port 12) P120 to P122 function as an I/O port. These pins also function as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, and external clock input for main system clock.
  • Page 29: Regc

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS 2.2.11 REGC This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this pin μ to V via a capacitor (0.47 to 1 REGC Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
  • Page 30: Pin I/O Circuits And Recommended Connection Of Unused Pins

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type.
  • Page 31 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types (2/2) Pin Name I/O Circuit Type Recommended Connection of Unused Pins 5-AQ Input: Independently connect to EV or EV via a resistor. Output: Leave open. P31/INTP2 P32/INTP3...
  • Page 32 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 5-AQ Type 37 Data P-ch Pull-up Output P-ch enable N-ch disable RESET Input Data enable P-ch IN/OUT Data P-ch Output N-ch disable Output N-ch disable...
  • Page 33: Chapter 3 Cpu Architecture

    CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the R7F0C011B, R7F0C012B, and R7F0C013B can access a 64 KB memory space. Figures 3-1 to 3-3 show the memory maps. Cautions 1. Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) of all products in the R7F0C011B, R7F0C012B, and R7F0C013B are fixed (IMS = CFH).
  • Page 34 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (R7F0C011B) FFFFH Special function registers (SFR) × 8 bits FF00H FEFFH General-purpose registers × 8 bits FEE0H 3FFFH FEDFH Internal high-speed RAM × 8 bits Program area FC00H FBFFH...
  • Page 35 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (R7F0C012B) FFFFH Special function registers (SFR) × 8 bits FF00H FEFFH General-purpose registers × 8 bits FEE0H 5FFFH FEDFH Internal high-speed RAM × 1024 8 bits Program area FB00H...
  • Page 36 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (R7F0C013B) FFFFH Special function registers (SFR) × 8 bits FF00H FEFFH General-purpose registers × 8 bits FEE0H 7FFFH FEDFH Internal high-speed RAM × 1024 8 bits Program area FB00H...
  • Page 37 3400H to 37FFH 7400H to 77FFH 3800H to 3BFFH 7800H to 7BFFH 3C00H to 3FFFH 7C00H to 7FFFH Remark R7F0C011B: Block numbers 00H to 07H R7F0C012B: Block numbers 00H to 17H R7F0C013B: Block numbers 00H to 1FH R01UH0408EJ0001 Rev.0.01 Sep 25, 2012...
  • Page 38: Internal Program Memory Space

    3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). R7F0C011B, R7F0C012B, and R7F0C013B incorporate internal ROM (flash memory), as shown below. Table 3-3. Internal ROM Capacity Product Internal ROM (Flash Memory) 16384 ×...
  • Page 39 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area A 5-byte area of 0080H to 0084H can be used as an option byte area. Set the option byte at 0080H to 0084H. For details, see CHAPTER 21 OPTION BYTE.
  • Page 40: Internal Data Memory Space

    Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the R7F0C011B, R7F0C012B, and R7F0C013B, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use.
  • Page 41 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Correspondence Between Data Memory and Addressing (R7F0C011B) FFFFH Special function registers SFR addressing (SFR) × 8 bits FF20H FF1FH FF00H FEFFH General-purpose Register addressing registers × Short direct FEE0H 8 bits...
  • Page 42 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Correspondence Between Data Memory and Addressing (R7F0C012B) F F F F H Special function registers SFR addressing (SFR) × 8 bits F F 2 0 H F F 1 F H...
  • Page 43 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Correspondence Between Data Memory and Addressing (R7F0C013B) F F F F H Special function registers SFR addressing (SFR) × 8 bits F F 2 0 H F F 1 F H...
  • Page 44: Processor Registers

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The R7F0C011B, R7F0C012B, and R7F0C013B incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
  • Page 45 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks.
  • Page 46 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H Register pair higher FEDFH FEDEH Register pair lower FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
  • Page 47: General-Purpose Registers

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH)
  • Page 48 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Configuration of General-Purpose Registers (a) Function name 16-bit processing 8-bit processing FEFFH Register bank 0 FEF8H Register bank 1 FEF0H Register bank 2 FEE8H Register bank 3 FEE0H (b) Absolute name...
  • Page 49: Special Function Registers (Sfrs)

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
  • Page 50 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (1/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port register 0 √...
  • Page 51 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (2/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF31H Pull-up resistor option register 1 √...
  • Page 52 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (3/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF70H Asynchronous serial interface operation mode...
  • Page 53 Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the R7F0C011B, R7F0C012B, and R7F0C013B are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated in Tables 3-1.
  • Page 54: Instruction Address Addressing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by contents of the program counter (PC) and memory bank select register (BANK), and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
  • Page 55: Immediate Addressing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
  • Page 56: Register Addressing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched.
  • Page 57: Operand Address Addressing

    [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the R7F0C011B, R7F0C012B, and R7F0C013B instruction words, the following instructions employ implied addressing. Instruction Register to Be Specified by Implied Addressing...
  • Page 58: Register Addressing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code.
  • Page 59: Direct Addressing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK.
  • Page 60: Short Direct Addressing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
  • Page 61: Special Function Register (Sfr) Addressing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
  • Page 62: Register Indirect Addressing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory.
  • Page 63: Based Addressing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
  • Page 64: Based Indexed Addressing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
  • Page 65: Stack Addressing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request.
  • Page 66: Chapter 4 Port Functions

    Corresponding Pins All pins The R7F0C011B, R7F0C012B, and R7F0C013B, microcontrollers are provided with digital I/O ports, which enable variety of control operations. The functions of each port are shown in Table 4-2. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS.
  • Page 67 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions Function Function After Reset Alternate Function Name Port 0. Input port TI000 2-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
  • Page 68: Port Configuration

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-3. Port Configuration Item Configuration Control registers Port mode register (PMxx): PM0 to PM4, PM6, PM7, PM12 Port register (Pxx): P0 to P4, P6, P7, P12...
  • Page 69: Port 0

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 and P01 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
  • Page 70 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P01 PU01 P-ch Alternate function PORT Output latch P01/TI010/TO00 (P01) PM01 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal...
  • Page 71: Port 1

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
  • Page 72 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P10 PU10 P-ch Alternate function PORT Output latch P10/SCK10/TxD0 (P10) PM10 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal...
  • Page 73 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch P11/SI10/RxD0, (P11, P14) P14/RxD6 PM11, PM14 Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal...
  • Page 74 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P12 and P15 PU12, PU15 P-ch PORT Output latch (P12, P15) P12/SO10, PM12, PM15 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal...
  • Page 75 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P13 PU13 P-ch PORT Output latch (P13) P13/TxD6 PM13 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal R01UH0408EJ0001 Rev.0.01...
  • Page 76 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P16 and P17 PU16, PU17 P-ch Alternate function PORT Output latch P16/TOH1, (P16, P17) P17/TI50/TO50 PM16, PM17 Alternate function Port register 1 PU1: Pull-up resistor option register 1...
  • Page 77: Port 2

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2).
  • Page 78 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P20 to P23 PORT Output latch P20/ANI0 to (P20 to P23) P23/ANI3 PM20 to PM23 A/D converter Port register 2 PM2: Port mode register 2 Read signal WR××: Write signal R01UH0408EJ0001 Rev.0.01...
  • Page 79: Port 3

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
  • Page 80 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P33 PU33 P-ch Alternate function PORT Output latch P33/INTP4/TI51/TO51 (P33) PM33 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal...
  • Page 81: Port 4

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 and P41 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4).
  • Page 82: Port 6

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 6 Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6).
  • Page 83: Port 7

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 and P71 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7).
  • Page 84: Port 12

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 12 Port 12 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
  • Page 85 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P121 and P122 OSCCTL OSCSEL PORT Output latch P122/X2/EXCLK (P122) PM12 PM122 OSCCTL OSCSEL OSCCTL EXCLK, OSCSEL PORT Output latch P121/X1 (P121) PM12 PM121 OSCCTL OSCSEL P12: Port register 12...
  • Page 86: Registers Controlling Port Function

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following four types of registers. • Port mode registers (PMxx) • Port registers (Pxx) • Pull-up resistor option registers (PUxx) • A/D port configuration register (ADPC) (1) Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units.
  • Page 87 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS (2) Port registers (Pxx) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is read.
  • Page 88 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
  • Page 89 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS (4) A/D port configuration register (ADPC) This register switches the P20/ANI0 to P23/ANI3 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 90: Port Function Operations

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
  • Page 91: Settings Of Port Mode Register And Output Latch When Using Alternate Function

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 4-5.
  • Page 92 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Pin Name Alternate Function PM×× P×× Function Name × P31 and P32 INTP2 and INTP3 Input × INTP4 Input ×...
  • Page 93: Cautions On 1-Bit Manipulation Instruction For Port Register N (Pn)

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 4 PORT FUNCTIONS 4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
  • Page 94: Chapter 5 Clock Generator

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable.
  • Page 95: Configuration Of Clock Generator

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode select register (OSCCTL) Processor clock control register (PCC)
  • Page 96 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR R01UH0408EJ0001 Rev.0.01 Sep 25, 2012...
  • Page 97: Registers Controlling Clock Generator

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR Remark f X1 clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency EXCLK High-speed system clock frequency Main system clock frequency Peripheral hardware clock frequency CPU clock frequency Internal low-speed oscillation clock frequency 5.3 Registers Controlling Clock Generator...
  • Page 98 Remark : Main system clock oscillation frequency The fastest instruction can be executed in 2 clocks of the CPU clock in the R7F0C011B, R7F0C012B, and R7F0C013B. Therefore, the relationship between the CPU clock (f ) and the minimum instruction execution time is as shown in Table 5-2.
  • Page 99 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR (3) Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation sets this register to 80H Figure 5-4.
  • Page 100 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock.
  • Page 101 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR (5) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 102 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked.
  • Page 103 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR (7) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
  • Page 104: System Clock Oscillator

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 10 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
  • Page 105 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR Figure 5-10. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched R01UH0408EJ0001 Rev.0.01...
  • Page 106: Internal High-Speed Oscillator

    CHAPTER 5 CLOCK GENERATOR 5.4.2 Internal high-speed oscillator The internal high-speed oscillator is incorporated in the R7F0C011B, R7F0C012B, and R7F0C013B. Oscillation can be controlled by the internal oscillation mode register (RCM). After a reset release, the internal high-speed oscillator automatically starts oscillation (8 MHz (TYP.)).
  • Page 107: Clock Generator Operation

    • Peripheral hardware clock f The CPU starts operation when the internal high-speed oscillator starts outputting after a reset release in the R7F0C011B, R7F0C012B, and R7F0C013B, thus enabling the following. (1) Enhancement of security function When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released.
  • Page 108 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR Figure 5-11. Clock Generator Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Note 1 4.0 V Power supply voltage (V 1.59 V (TYP.)
  • Page 109 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR Figure 5-12. Clock Generator Operation When Power Supply Voltage Is Turned On (When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1)) 2.7 V (TYP.) Power supply voltage (V <1>...
  • Page 110: Controlling Clock

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of controlling high-speed system clock The following two types of high-speed system clocks are available. • X1 clock: Crystal/ceramic resonator is connected across the X1 and X2 pins.
  • Page 111 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR (2) Example of setting procedure when using the external main system clock <1> Setting P121/X1 and P122/X2/EXCLK pins and selecting operation mode (OSCCTL register) When EXCLK and OSCSEL are set to 1, the mode is switched from port mode to external clock input mode.
  • Page 112 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR (4) Example of setting procedure when stopping the high-speed system clock The high-speed system clock can be stopped in the following two ways. • Executing the STOP instruction and stopping the X1 oscillation (disabling clock input if the external clock is used) •...
  • Page 113: Example Of Controlling Internal High-Speed Oscillation Clock

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of controlling internal high-speed oscillation clock The following describes examples of clock setting procedures for the following cases. (1) When restarting oscillation of the internal high-speed oscillation clock (2) When using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-...
  • Page 114 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock <1> • Restarting oscillation of the internal high-speed oscillation clock Note (See 5.6.2 (1) Example of setting procedure when restarting oscillation of the internal high-speed...
  • Page 115 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR (3) Example of setting procedure when stopping the internal high-speed oscillation clock The internal high-speed oscillation clock can be stopped in the following two ways. • Executing the STOP instruction to set the STOP mode •...
  • Page 116: Example Of Controlling Internal Low-Speed Oscillation Clock

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock. • Watchdog timer •...
  • Page 117: Cpu Clock Status Transition Diagram

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR 5.6.5 CPU clock status transition diagram Figure 5-13 shows the CPU clock status transition diagram of this product. Figure 5-13. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)
  • Page 118 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/2) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
  • Page 119 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/2) (4) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register...
  • Page 120: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR 5.6.6 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-5. Changing CPU Clock...
  • Page 121: Time Required For Switchover Of Cpu Clock And Main System Clock

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 5 CLOCK GENERATOR 5.6.7 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC), the CPU clock can be switched the division ratio of the main system clock can be changed.
  • Page 122: Conditions Before Clock Oscillation Is Stopped

    External main system clock 5.6.9 Peripheral hardware and source clocks The following lists peripheral hardware and source clocks incorporated in the R7F0C011B, R7F0C012B, and R7F0C013B. Remark The peripheral hardware depends on the product. See 1.6 Block Diagram and 1.7 Outline of Functions.
  • Page 123: Chapter 6 16-Bit Timer/Event Counter 00

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates an interrupt request at the preset time interval.
  • Page 124: Configuration Of 16-Bit Timer/Event Counter 00

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 includes the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration Time/counter 16-bit timer counter 00 (TM00)
  • Page 125 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 1. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same time. Select either of the functions. 2. If clearing of bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) to 00 and input of the capture trigger conflict, then the captured data is undefined.
  • Page 126 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) 16-bit timer capture/compare register 000 (CR000), 16-bit timer capture/compare register 010 (CR010) CR000 and CR010 are 16-bit registers that are used with a capture function or comparison function selected by using CRC00.
  • Page 127 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010) Address: FF14H, FF15H After reset: 0000H FF15H FF14H CR010 (i) When CR010 is used as a compare register The value set in CR010 is constantly compared with the TM00 count value, and an interrupt request signal (INTTM010) is generated if they match.
  • Page 128 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Timer counter clear TM00 register Compare register set value (0000H) Operation Operation enabled Timer operation enable bit disabled (00) (other than 00) (TMC003, TMC002) Interrupt request signal Interrupt signal Interrupt signal...
  • Page 129 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. Capture Operation of CR000 and CR010 External Input Signal TI000 Pin Input TI010 Pin Input Capture Operation Capture operation of CRC001 = 1 Set values of ES010 and CRC001 bit = 0...
  • Page 130: Registers Controlling 16-Bit Timer/Event Counter 00

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 Registers used to control 16-bit timer/event counter 00 are shown below. • 16-bit timer mode control register 00 (TMC00) • Capture/compare control register 00 (CRC00) •...
  • Page 131 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FF86H After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 Operation enable of 16-bit timer/event counter 00 Disables 16-bit timer/event counter 00 operation.
  • Page 132 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00) Address: FF88H After reset: 00H Symbol CRC00 CRC002 CRC001 CRC000 CRC002 CR010 operating mode selection Operates as compare register Operates as capture register...
  • Page 133 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) TOC00 is an 8-bit register that controls the TO00 output. TOC00 can be rewritten while only OSPT00 is operating (when TMC003 and TMC002 = other than 00). Rewriting the other bits is prohibited during operation.
  • Page 134 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-8. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FF89H After reset: 00H Symbol <6> <5> <3> <2> <0> TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger via software −...
  • Page 135 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) PRM00 is the register that sets the TM00 count clock and TI000 and TI010 pin input valid edges. Rewriting PRM00 is prohibited during operation (when TMC003 and TMC002 = other than 00).
  • Page 136 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-9. Format of Prescaler Mode Register 00 (PRM00) Address: FF87H After reset: 00H Symbol PRM00 ES110 ES100 ES010 ES000 PRM001 PRM000 ES110 ES100 TI010 pin valid edge selection Falling edge...
  • Page 137 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 pin for timer output, set the output latches of PM01 to 0.
  • Page 138: Operation Of 16-Bit Timer/Event Counter 00

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation If bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register (TMC00) are set to 11 (clear & start mode entered upon a match between TM00 and CR000), the count operation is started in synchronization with the count clock.
  • Page 139 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-13. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000.
  • Page 140 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-14. Example of Software Processing for Interval Timer Function TM00 register 0000H Operable bits (TMC003, TMC002) CR000 register INTTM000 signal <1> <2> <1> Count operation start flow START Register initial setting...
  • Page 141: Square-Wave Output Operation

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.2 Square-wave output operation When 16-bit timer/event counter 00 operates as an interval timer (refer to 6.4.1), a square wave can be output from the TO00 pin by setting the 16-bit timer output control register 00 (TOC00) to 03H.
  • Page 142 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-17. Example of Register Settings for Square-Wave Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000.
  • Page 143 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-17. Example of Register Settings for Square-Wave Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) If M is set to CR000, the interval time is as follows.
  • Page 144 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-18. Example of Software Processing for Square-Wave Output Function TM00 register 0000H Operable bits (TMC003, TMC002) CR000 register TO00 output INTTM000 signal TO0n output control bit (TOC001, TOE00) <1> <2>...
  • Page 145: External Event Counter Operation

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 External event counter operation When bits 1 and 0 (PRM001 and PRM000) of the prescaler mode register 00 (PRM00) are set to 11 (for counting up with the valid edge of the TI000 pin) and bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between TM00 and CR000 (INTTM000) is generated.
  • Page 146 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-20. Example of Register Settings in External Event Counter Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000.
  • Page 147 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-20. Example of Register Settings in External Event Counter Mode (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) If M is set to CR000, the interrupt signal (INTTM000) is generated when the number of external events reaches (M + 1).
  • Page 148 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Example of Software Processing in External Event Counter Mode TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) TO00 output Compare match interrupt (INTTM000) TO00 output control bits (TOC004, TOC001, TOE00) <1>...
  • Page 149: Operation In Clear & Start Mode Entered By Ti000 Pin Valid Edge Input

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 10 (clear & start mode entered by the TI000 pin valid edge input) and the count clock (set by PRM00) is supplied to the timer/event counter, TM00 starts counting up.
  • Page 150 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: compare register, CR010: compare register) Figure 6-22. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input...
  • Page 151 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Compare Register) (a) TOC00 = 13H, PRM00 = 10H, CRC00 = 00H, TMC00 = 08H...
  • Page 152 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: compare register, CR010: capture register) Figure 6-24. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input...
  • Page 153 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-25. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Capture Register) (1/2) (a) TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 08H, CR000 = 0001H...
  • Page 154 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-25. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Capture Register) (2/2) (b) TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 0AH, CR000 = 0003H...
  • Page 155 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Operation in clear & start mode by entered TI000 pin valid edge input (CR000: capture register, CR010: compare register) Figure 6-26. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input...
  • Page 156 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-27. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) (1/2) (a) TOC00 = 13H, PRM00 = 10H, CRC00 = 03H, TMC00 = 08H, CR010 = 0001H...
  • Page 157 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-27. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) (2/2) (b) TOC00 = 13H, PRM00 = 10H, CRC00 = 03H, TMC00 = 0AH, CR010 = 0003H...
  • Page 158 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: capture register, CR010: capture register) Figure 6-28. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input...
  • Page 159 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) (1/3) (a) TOC00 = 13H, PRM00 = 30H, CRC00 = 05H, TMC00 = 0AH...
  • Page 160 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) (2/3) (b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 = 0AH...
  • Page 161 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) (3/3) (c) TOC00 = 13H, PRM00 = 00H, CRC00 = 07H, TMC00 = 0AH...
  • Page 162 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 0: Inverts TO00 output on match between TM00 and CR000/CR010.
  • Page 163 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (2/2) (d) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM000...
  • Page 164 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Example of Software Processing in Clear & Start Mode Entered by TI000 Pin Valid Edge Input TM00 register 0000H Operable bits (TMC003, TMC002) Count clear input (TI000 pin input)
  • Page 165: Free-Running Timer Operation

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 Free-running timer operation When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 01 (free-running timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (OVF00) is set to 1 at the next clock, and TM00 is cleared (to 0000H) and continues counting.
  • Page 166 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Timing Example of Free-Running Timer Mode (CR000: Compare Register, CR010: Compare Register) • TOC00 = 13H, PRM00 = 00H, CRC00 = 00H, TMC00 = 04H FFFFH TM00 register 0000H...
  • Page 167 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Free-running timer mode operation (CR000: compare register, CR010: capture register) Figure 6-34. Block Diagram of Free-Running Timer Mode (CR000: Compare Register, CR010: Capture Register) Timer counter Count clock (TM00) Match signal...
  • Page 168 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-35. Timing Example of Free-Running Timer Mode (CR000: Compare Register, CR010: Capture Register) • TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 04H FFFFH TM00 register 0000H...
  • Page 169 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Free-running timer mode operation (CR000: capture register, CR010: capture register) Figure 6-36. Block Diagram of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) Operable bits TMC003, TMC002 Timer counter...
  • Page 170 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-37. Timing Example of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) (1/2) (a) TOC00 = 13H, PRM00 = 50H, CRC00 = 05H, TMC00 = 04H FFFFH TM00 register...
  • Page 171 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-37. Timing Example of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) (2/2) (b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 = 04H FFFFH TM00 register...
  • Page 172 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-38. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 0: Inverts TO00 output on match between TM00 and CR000/CR010.
  • Page 173 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-38. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM000 Count clock selection (setting TI000 valid edge is prohibited)
  • Page 174 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-39. Example of Software Processing in Free-Running Timer Mode FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) Compare match interrupt (INTTM000) Compare register (CR010) Compare match interrupt...
  • Page 175: Ppg Output Operation

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 PPG output operation A square wave having a pulse width set in advance by CR010 is output from the TO00 pin as a PPG (Programmable Pulse Generator) signal during a cycle set by CR000 when bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11 (clear &...
  • Page 176 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-41. Example of Register Settings for PPG Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000.
  • Page 177 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-41. Example of Register Settings for PPG Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) An interrupt signal (INTTM000) is generated when the value of this register matches the count value of TM00.
  • Page 178 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-42. Example of Software Processing for PPG Output Operation TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) Compare match interrupt (INTTM000) Compare register (CR010) Compare match interrupt (INTTM010)
  • Page 179: One-Shot Pulse Output Operation

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.7 One-shot pulse output operation A one-shot pulse can be output by setting bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register 00 (TMC00) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI000 pin valid edge) and setting bit 5 (OSPE00) of 16-bit timer output control register 00 (TOC00) to 1.
  • Page 180 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-44. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 01: Free running timer mode 10: Clear and start mode by valid edge of TI000 pin.
  • Page 181 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-44. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a compare register when a one-shot pulse is output.
  • Page 182 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-45. Example of Software Processing for One-Shot Pulse Output Operation (1/2) FFFFH TM00 register 0000H Operable bits 01 or 10 (TMC003, TMC002) One-shot pulse enable bit (OSPE0) One-shot pulse trigger bit...
  • Page 183 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-45. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM00 register, before setting the TMC003 and TMC002 bits.
  • Page 184: Pulse Width Measurement Operation

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.8 Pulse width measurement operation TM00 can be used to measure the pulse width of the signal input to the TI000 and TI010 pins. Measurement can be accomplished by operating the 16-bit timer/event counter 00 in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI000 pin.
  • Page 185 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 A pulse width can be measured in the following three ways. • Measuring the pulse width by using two input signals of the TI000 and TI010 pins (free-running timer mode) • Measuring the pulse width by using one input signal of the TI000 pin (free-running timer mode) •...
  • Page 186 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Measuring the pulse width by using two input signals of the TI000 and TI010 pins (free-running timer mode) Set the free-running timer mode (TMC003 and TMC002 = 01). When the valid edge of the TI000 pin is detected, the count value of TM00 is captured to CR010.
  • Page 187 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measuring the pulse width by using one input signal of the TI000 pin (free-running timer mode) Set the free-running timer mode (TMC003 and TMC002 = 01). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge detected on the TI000 pin.
  • Page 188 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the TI000 pin valid edge input) Set the clear & start mode entered by the TI000 pin valid edge (TMC003 and TMC002 = 10). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge of the TI000 pin, and the count value of TM00 is captured to CR010 and TM00 is cleared (0000H) when the valid edge of the TI000 pin is detected.
  • Page 189 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-51. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI000 pin.
  • Page 190 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-51. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a capture register.
  • Page 191 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-52. Example of Software Processing for Pulse Width Measurement (1/2) (a) Example of free-running timer mode FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input (TI000) Capture register...
  • Page 192 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-52. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM00 register, before setting the TMC003 and TMC002 bits.
  • Page 193: Special Use Of Tm00

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Special Use of TM00 6.5.1 Rewriting CR010 during TM00 operation In principle, rewriting CR000 and CR010 of the µPD79F7023, 79F7024 microcontrollers when they are used as compare registers is prohibited while TM00 is operating (TMC003 and TMC002 = other than 00).
  • Page 194 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Setting LVS00 and LVR00 Set LVS00 and LVR00 using the following procedure. Figure 6-53. Example of Flow for Setting LVS00 and LVR00 Bits Setting TOC00.OSPE00, TOC004, TOC001 bits <1> Setting of timer output operation Setting TOC00.TOE00 bit...
  • Page 195: Cautions For 16-Bit Timer/Event Counter 00

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.6 Cautions for 16-Bit Timer/Event Counter 00 (1) Restrictions for each channel of 16-bit timer/event counter 00 Table 6-3 shows the restrictions for each channel. Table 6-3. Restrictions for Each Channel of 16-Bit Timer/Event Counter 00...
  • Page 196 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI000/TI010 pin and the reverse phase of the TI000 pin is detected while CR000/CR010 is read, CR010 performs a capture operation but the read value of CR000/CR010 is not guaranteed.
  • Page 197 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (7) Operation of OVF00 flag (a) Setting OVF00 flag (1) The OVF00 flag is set to 1 in the following case, as well as when TM00 overflows. Select the clear & start mode entered upon a match between TM00 and CR000.
  • Page 198 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (9) Capture operation (a) When valid edge of TI000 is specified as count clock When the valid edge of TI000 is specified as the count clock, the capture register for which TI000 is specified as a trigger does not operate correctly.
  • Page 199 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (12) Reading of 16-bit timer counter 00 (TM00) TM00 can be read without stopping the actual counter, because the count values captured to the buffer are fixed when it is read. The buffer, however, may not be updated when it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up.
  • Page 200: Chapter 7 8-Bit Timer/Event Counters 50 And 51

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. • Interval timer •...
  • Page 201 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus 8-bit timer compare Selector INTTM50 register 50 (CR50) To TMH0 To UART0 TI50/TO50/P17 Note 1 Match To UART6...
  • Page 202 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock.
  • Page 203: Registers Controlling 8-Bit Timer/Event Counters 50 And 51

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock selection register 5n (TCL5n) •...
  • Page 204 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Count clock selection = 2 MHz...
  • Page 205 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2>...
  • Page 206 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Note Address: FF43H After reset: 00H Symbol <7> <3> <2> <0> TMC51 TCE51 TMC516 LVS51 LVR51 TMC511 TOE51...
  • Page 207 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0.
  • Page 208: Operations Of 8-Bit Timer/Event Counters 50 And 51

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51 7.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n).
  • Page 209 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n Interval time (c) When CR5n = FFH Count clock TM5n FEH FFH 00H...
  • Page 210: Operation As External Event Counter

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n).
  • Page 211: Square-Wave Output Operation

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1.
  • Page 212: Pwm Output Operation

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-13. Square-Wave Output Operation Timing Count clock N − 1 N − 1 TM5n count value Count start CR5n Note TO5n Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
  • Page 213 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. • Clear the port output latch (P17 or P33) Note Note and port mode register (PM17 or PM33) to 0.
  • Page 214 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-14. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H...
  • Page 215 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 7-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH → Value is transferred to CR5n at overflow immediately after change.
  • Page 216: Cautions For 8-Bit Timer/Event Counters 50 And 51

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
  • Page 217: Chapter 8 8-Bit Timers H0 And H1

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 CHAPTER 8 8-BIT TIMERS H0 AND H1 8.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. • Interval timer • Square-wave output •...
  • Page 218 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 R01UH0408EJ0001 Rev.0.01 Sep 25, 2012...
  • Page 219 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 R01UH0408EJ0001 Rev.0.01 Sep 25, 2012...
  • Page 220 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes.
  • Page 221: Registers Controlling 8-Bit Timers H0 And H1

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 8.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. • 8-bit timer H mode register n (TMHMDn) • 8-bit timer H carrier control register 1 (TMCYC1) Note •...
  • Page 222 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H After reset: 00H <7> <1> <0> TMHMD0 TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 Timer operation enable...
  • Page 223 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. However, TMHMD0 can be refreshed (the same value is written). 2. In the PWM output mode, be sure to set the 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).
  • Page 224 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be refreshed (the same value is written). 2. In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare...
  • Page 225 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P16/TOH1 pins for timer output, clear PM16 and the output latches of P16 to 0.
  • Page 226: Operation Of 8-Bit Timers H0 And H1

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4 Operation of 8-Bit Timers H0 and H1 8.4.1 Operation as interval timer/square-wave output When the 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and the 8-bit timer counter Hn is cleared to 00H.
  • Page 227 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (Operation When 01H ≤ CMP0n ≤ FEH) Count clock Count start 01H 00H 8-bit timer counter Hn Clear...
  • Page 228 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn TOHn Interval time...
  • Page 229: Operation As Pwm Output

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.2 Operation as PWM output In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited.
  • Page 230 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of the 8-bit timer counter Hn and the CMP0n register match, the 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and an active level is output.
  • Page 231 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H 8-bit timer counter Hn...
  • Page 232 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H...
  • Page 233 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter Hn...
  • Page 234 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 02H → 03H, CMP0n = A5H) Count clock 8-bit timer 00H 01H 02H A5H 00H 01H 02H 03H...
  • Page 235: Carrier Generator Operation (8-Bit Timer H1 Only)

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.3 Carrier generator operation (8-bit timer H1 only) In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count).
  • Page 236 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal.
  • Page 237 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Setting <1> Set each register. Figure 8-14. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHMD1...
  • Page 238 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 <7> The INTTM51 signal is synchronized with count clock of the 8-bit timer H1 and output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit.
  • Page 239 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer H1 count clock 8-bit timer counter N 00H N 00H N 00H...
  • Page 240 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer H1 count clock 8-bit timer counter N 00H 01H M 00H...
  • Page 241 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3>...
  • Page 242: Chapter 9 Watch Timer

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 9 WATCH TIMER CHAPTER 9 WATCH TIMER 9.1 Functions of Watch Timer The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously.
  • Page 243: Configuration Of Watch Timer

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 9 WATCH TIMER (1) Watch timer When the peripheral hardware clock or subsystem clock is used, interrupt request signals (INTWT) are generated at preset intervals. Table 9-1. Watch Timer Interrupt Time Interrupt Time When Operated at...
  • Page 244: Register Controlling Watch Timer

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 9 WATCH TIMER 9.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM). • Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control.
  • Page 245: Watch Timer Operations

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 9 WATCH TIMER 9.4 Watch Timer Operations 9.4.1 Watch timer operation The watch timer generates an interrupt request signal (INTWT) at a specific time interval by using the peripheral hardware clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts.
  • Page 246: Interval Timer Operation

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 9 WATCH TIMER 9.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt request signals (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM).
  • Page 247: Chapter 10 Watchdog Timer

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 10 WATCHDOG TIMER CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.
  • Page 248: Configuration Of Watchdog Timer

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 10-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte.
  • Page 249: Register Controlling Watchdog Timer

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 10 WATCHDOG TIMER 10.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
  • Page 250: Operation Of Watchdog Timer

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Controlling operation of watchdog timer When the watchdog timer is used, its operation is specified by the option byte (0080H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 21).
  • Page 251: Setting Overflow Time Of Watchdog Timer

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 10 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. LSROSC = 0 (Internal Low-Speed...
  • Page 252: Setting Window Open Period Of Watchdog Timer

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 10 WATCHDOG TIMER 10.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows.
  • Page 253 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 10 WATCHDOG TIMER Remark If the overflow time is set to 2 , the window close time and open time are as follows. Setting of Window Open Period 100% Window close time 0 to 7.11 ms 0 to 4.74 ms...
  • Page 254: Chapter 11 A/D Converter

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER CHAPTER 11 A/D CONVERTER 11.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to ANI3) with a resolution of 10 bits.
  • Page 255: Configuration Of A/D Converter

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER 11.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI3 pins These are the analog input pins of the 4-channel A/D converter. They input analog signals to be converted into digital signals.
  • Page 256 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER (8) Controller This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller generates INTAD.
  • Page 257: Registers Used In A/D Converter

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER 11.3 Registers Used in A/D Converter The A/D converter uses the following six registers. • A/D converter mode register (ADM) • A/D port configuration register (ADPC) • Analog input channel specification register (ADS) •...
  • Page 258 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER Figure 11-4. Timing Chart When Comparator Is Used Comparator operation ADCE Comparator Conversion Conversion Conversion Conversion operation waiting operation stopped ADCS Note Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be 1 μ...
  • Page 259 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER Figure 11-5. A/D Converter Sampling and A/D Conversion Timing ← ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait Sampling Successive conversion Sampling Transfer Note period clear to ADCR, clear INTAD generation...
  • Page 260 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER (3) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored. ADCRH can be read by an 8-bit memory manipulation instruction.
  • Page 261 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER (5) A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI3/P23 pins to analog input of A/D converter or digital I/O of port. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 262 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER (6) Port mode register 2 (PM2) When using the ANI0/P20 to ANI3/P23 pins for analog input port, set PM20 to PM23 to 1. The output latches of P20 to P23 at this time may be 0 or 1.
  • Page 263: A/D Converter Operations

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER 11.4 A/D Converter Operations 11.4.1 Basic operations of A/D converter <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the comparator. <2> Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set to input mode by using port mode register 2 (PM2).
  • Page 264: Input Voltage And Conversion Results

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER Figure 11-11. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
  • Page 265 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER Figure 11-12 shows the relationship between the analog input voltage and the A/D conversion result. Figure 11-12. Relationship Between Analog Input Voltage and A/D Conversion Result ADCR 1023 FFC0H 1022 FF80H 1021 FF40H...
  • Page 266: A/D Converter Operation Mode

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER 11.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed.
  • Page 267 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER The setting methods are described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Set the channel to be used in the analog input mode by using bits 3 to 0 (ADPC3 to ADPC0) of the A/D port configuration register (ADPC) and bits 3 to 0 (PM23 to PM20) of port mode register 2 (PM2).
  • Page 268: How To Read A/D Converter Characteristics Table

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER 11.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
  • Page 269 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0..000 to 0..001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0……001 to 0……010.
  • Page 270 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER Figure 11-18. Integral Linearity Error Figure 11-19. Differential Linearity Error 1 …… 1 1 …… 1 Ideal 1LSB width Ideal line Differential Integral linearity linearity error error 0 …… 0 0 …… 0...
  • Page 271: Cautions For A/D Converter

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER 11.6 Cautions for A/D Converter (1) Operating current in STOP mode The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0.
  • Page 272 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER Figure 11-20. Analog Input Pin Connection If there is a possibility that noise equal to or higher than V equal to or lower than V may enter, clamp with a diode with a small V value (0.3 V or lower).
  • Page 273 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre- change analog input may be set just before the ADS rewrite.
  • Page 274 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 11 A/D CONVERTER (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 11-22. Internal Equivalent Circuit of ANIn Pin ANIn Table 11-5. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) 4.0 V ≤...
  • Page 275: Chapter 12 Serial Interface Uart0

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 CHAPTER 12 SERIAL INTERFACE UART0 12.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
  • Page 276: Configuration Of Serial Interface Uart0

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 12.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 12-1. Configuration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0)
  • Page 277 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 R01UH0408EJ0001 Rev.0.01 Sep 25, 2012...
  • Page 278 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0).
  • Page 279: Registers Controlling Serial Interface Uart0

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 12.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. • Asynchronous serial interface operation mode register 0 (ASIM0) • Asynchronous serial interface reception error status register 0 (ASIS0) •...
  • Page 280 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 Figure 12-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
  • Page 281 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0).
  • Page 282 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction.
  • Page 283 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the MDL04 to MDL00 bits. 2. Make sure that bit 7 (POWER0) of the ASIM0 register = 0 when rewriting the TPS01 and TPS00 bits.
  • Page 284: Operation Of Serial Interface Uart0

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 12.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 12.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode.
  • Page 285: Asynchronous Serial Interface (Uart) Mode

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 12.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
  • Page 286 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 12-6 and 12-7 show the format and waveform example of the normal transmit/receive data. Figure 12-6. Format of Normal UART Transmit/Receive Data...
  • Page 287 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
  • Page 288 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 (c) Transmission If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0).
  • Page 289 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the R D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1.
  • Page 290 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt (INTSR0) is generated.
  • Page 291: Dedicated Baud Rate Generator

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 12.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception.
  • Page 292 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 Figure 12-11. Configuration of Baud Rate Generator POWER0 Baud rate generator POWER0, TXE0 (or RXE0) Selector 5-bit counter XCLK0 8-bit timer/ event counter 50 output Match detector Baud rate BRGC0: TPS01, TPS00...
  • Page 293: Calculation Of Baud Rate

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 12.4.4 Calculation of baud rate (1) Baud rate calculation expression The baud rate can be calculated by the following expression. XCLK0 • Baud rate = [bps] 2 × k : Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register XCLK0 Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31)
  • Page 294 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 (2) Error of baud rate The baud rate error can be calculated by the following expression. Actual baud rate (baud rate with error) • Error (%) = − 1 × 100 [%] Desired baud rate (correct baud rate) Cautions 1.
  • Page 295 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
  • Page 296 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 12 SERIAL INTERFACE UART0 Similarly, the maximum permissible data frame length can be calculated as follows. 21k − 2 k + 2 × FLmax = 11 × FL − × FL = 2 × k 2 × k 21k –...
  • Page 297: Chapter 13 Serial Interface Uart6

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 CHAPTER 13 SERIAL INTERFACE UART6 13.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
  • Page 298 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
  • Page 299 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Figures 13-1 and 13-2 outline the transmission and reception operations of LIN. Figure 13-1. LIN Transmission Operation Wakeup Sync Sync field Identifier Data field Data field Checksum signal frame break field field...
  • Page 300 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-2. LIN Reception Operation Wakeup Sync Sync field Identifier Data field Data field Checksum signal frame break field field field LIN Bus 13-bit Data Data Data SBF reception reception reception reception...
  • Page 301 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-3 shows the port configuration for LIN reception operation. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0). The length of the sync field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated.
  • Page 302: Configuration Of Serial Interface Uart6

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 The peripheral functions used in the LIN communication operation are shown below. <Peripheral functions used> • External interrupt (INTP0); wakeup signal detection Use: Detects the wakeup signal edges and detects start of communication.
  • Page 303 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 R01UH0408EJ0001 Rev.0.01 Sep 25, 2012...
  • Page 304 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the data length is set to 7 bits, data is transferred as follows.
  • Page 305: Registers Controlling Serial Interface Uart6

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 13.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...
  • Page 306 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) Address: FF50H After reset: 01H R/W Symbol <7> <6> <5> ASIM6 POWER6 TXE6 RXE6 PS61 PS60 ISRM6 POWER6 Enables/disables operation of internal operation clock...
  • Page 307 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) PS61 PS60 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
  • Page 308 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6).
  • Page 309 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
  • Page 310 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
  • Page 311 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction.
  • Page 312 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H.
  • Page 313 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length.
  • Page 314 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The signal input from the P14/R D6 pin is selected as the input source of INTP0 and TI000 when ISC0 and ISC1 are set to 1.
  • Page 315: Operation Of Serial Interface Uart6

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 13.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 13.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
  • Page 316: Asynchronous Serial Interface (Uart) Mode

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 13.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
  • Page 317 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 13-13 and 13-14 show the format and waveform example of the normal transmit/receive data. Figure 13-13. Format of Normal UART Transmit/Receive Data 1.
  • Page 318 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (ASIM6). Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial interface control register 6 (ASICL6).
  • Page 319 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-14. Example of Normal UART Transmit/Receive Data Waveform (2/2) 4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start Parity...
  • Page 320 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (ii) Odd parity • Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are “1” is odd. If transmit data has an odd number of bits that are “1”: 0 If transmit data has an even number of bits that are “1”: 1...
  • Page 321 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-15. Normal Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 D6 (output) Parity Start Stop INTST6 2. Stop bit length: 2 D6 (output) Start Parity Stop INTST6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation.
  • Page 322 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 TXBF6 Writing to TXB6 Register Writing enabled Writing disabled Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte) to the TXB6 register.
  • Page 323 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-16 shows an example of the continuous transmission processing flow. Figure 13-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Read ASIF6 TXBF6 = 0? Write TXB6.
  • Page 324 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-17 shows the timing of starting continuous transmission, and Figure 13-18 shows the timing of ending continuous transmission. Figure 13-17. Timing of Starting Continuous Transmission Start Start Start Data (1) Parity...
  • Page 325 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Remark T D6 pin (output) INTST6: Interrupt request signal TXB6: Transmit buffer register 6 TXS6: Transmit shift register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6...
  • Page 326 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
  • Page 327 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RxD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
  • Page 328 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (h) SBF transmission When the device is use in LIN communication operation, the SBF (Synchronous Break Field) transmission control function is used for transmission. For the transmission operation of LIN, see Figure 13-1 LIN Transmission Operation.
  • Page 329 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 SBF reception When the device is used in LIN communication operation, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 13-2 LIN Reception Operation.
  • Page 330: Dedicated Baud Rate Generator

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 13.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception.
  • Page 331: Calculation Of Baud Rate

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-24. Configuration of Baud Rate Generator POWER6 Baud rate generator POWER6, TXE6 (or RXE6) Selector 8-bit counter XCLK6 Match detector Baud rate 8-bit timer/ event counter 50 output CKSR6: TPS63 to TPS60...
  • Page 332 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 Table 13-4. Set Value of TPS63 to TPS60 TPS63 TPS62 TPS61 TPS60 Base Clock (f ) Selection XCLK6 2 MHz 5 MHz 10 MHz 2 MHz 5 MHz 10 MHz 1 MHz 2.5 MHz...
  • Page 333 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 13-5. Set Data of Baud Rate Generator Baud Rate = 2.0 MHz = 5.0 MHz = 10.0 MHz [bps] TPS63 to Calculated TPS63 to Calculated...
  • Page 334 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
  • Page 335 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows.
  • Page 336 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 13 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.
  • Page 337: Chapter 14 Serial Interface Csi10

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 CHAPTER 14 SERIAL INTERFACE CSI10 14.1 Functions of Serial Interface CSI10 Serial interface CSI10 has the following two modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption.
  • Page 338 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-1. Block Diagram of Serial Interface CSI10 Internal bus Serial I/O shift Transmit buffer Output SI10/P11/R register 10 (SIO10) register 10 (SOTB10) selector SO10/P12 Output latch PM12 (P12) Transmit data Output latch...
  • Page 339: Registers Controlling Serial Interface Csi10

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 14.3 Registers Controlling Serial Interface CSI10 Serial interface CSI10 is controlled by the following four registers. • Serial operation mode register 10 (CSIM10) • Serial clock selection register 10 (CSIC10) • Port mode register 1 (PM1) •...
  • Page 340 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-2. Format of Serial Operation Mode Register 10 (CSIM10) Note 1 Address: FF80H After reset: 00H R/W Symbol <7> CSIM10 CSIE10 TRMD10 DIR10 CSOT10 CSIE10 Operation control in 3-wire serial I/O mode...
  • Page 341 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 (2) Serial clock selection register 10 (CSIC10) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 342 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using P10/SCK10 as the clock output pin of the serial interface, clear PM10 to 0, and set the output latches of P10 to 1.
  • Page 343: Operation Of Serial Interface Csi10

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 14.4 Operation of Serial Interface CSI10 Serial interface CSI10 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 14.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition,...
  • Page 344: 3-Wire Serial I/O Mode

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 14.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and serial input (SI10) lines.
  • Page 345 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins CSIE10 TRMD10 PM11 PM12 PM10 CSI10 Pin Function Operation SI10/RxD0/ SCK10/ SO10/P12 TxD0/P10 ×...
  • Page 346 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock.
  • Page 347 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-5. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2: TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1) SCK10 Read/write trigger SOTB10 55H (communication data)
  • Page 348 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-6. Timing of Clock/Data Phase (a) Type 1: CKP10 = 0, DAP10 = 0, DIR10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 (b) Type 2: CKP10 = 0, DAP10 = 1, DIR10 = 0...
  • Page 349 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 (3) Timing of output to SO10 pin (first bit) When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin. The output operation of the first bit at this time is described below.
  • Page 350 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-7. Output Operation of First Bit (2/2) (c) Type 2: CKP10 = 0, DAP10 = 1 SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch First bit 2nd bit...
  • Page 351 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 (4) Output value of SO10 pin (last bit) After communication has been completed, the SO10 pin holds the output value of the last bit. Figure 14-8. Output Value of SO10 Pin (Last Bit) (1/2)
  • Page 352 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-8. Output Value of SO10 Pin (Last Bit) (2/2) (c) Type 2: CKP10 = 0, DAP10 = 1 SCK10 Writing to SOTB10 or ( ← Next request is issued.) reading from SIO10...
  • Page 353 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 14 SERIAL INTERFACE CSI10 (5) SO10 output (see (a) in Figure 14-1) The status of the SO10 output is as follows if bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) is cleared to 0.
  • Page 354: Chapter 15 Serial Interface Iic0

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 CHAPTER 15 SERIAL INTERFACE IIC0 15.1 Functions of Serial Interface IIC0 Serial interface IIC0 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
  • Page 355 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-1. Block Diagram of Serial Interface IIC0 Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0...
  • Page 356 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-2 shows a serial bus configuration example. Figure 15-2. Serial Bus Configuration Example Using I C Bus Serial data bus Master CPU1 Master CPU2 SDA0 SDA0 Slave CPU1 Slave CPU2 Serial clock...
  • Page 357: Configuration Of Serial Interface Iic0

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.2 Configuration of Serial Interface IIC0 Serial interface IIC0 includes the following hardware. Table 15-1. Configuration of Serial Interface IIC0 Item Configuration Registers IIC shift register 0 (IIC0) Slave address register 0 (SVA0)
  • Page 358 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (2) Slave address register 0 (SVA0) This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode. This register can be set by an 8-bit memory manipulation instruction.
  • Page 359 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (10) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits generate and detect each status. (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
  • Page 360: Registers To Control Serial Interface Iic0

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.3 Registers to Control Serial Interface IIC0 Serial interface IIC0 is controlled by the following seven registers. • IIC control register 0 (IICC0) • IIC flag register 0 (IICF0) • IIC status register 0 (IICS0) •...
  • Page 361 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-5. Format of IIC Control Register 0 (IICC0) (1/4) Address: FFA6H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0...
  • Page 362 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-5. Format of IIC Control Register 0 (IICC0) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected Disable Enable Condition for clearing (SPIE0 = 0) Condition for setting (SPIE0 = 1) •...
  • Page 363 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-5. Format of IIC Control Register 0 (IICC0) (3/4) Note STT0 Start condition trigger Do not generate a start condition. When bus is released (in standby state, when IICBSY = 0): If this bit is set (1), a start condition is generated (startup as the master).
  • Page 364 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-5. Format of IIC Control Register 0 (IICC0) (4/4) SPT0 Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing •...
  • Page 365 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-6. Format of IIC Status Register 0 (IICS0) (1/3) Address: FFAAH After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICS0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0...
  • Page 366 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-6. Format of IIC Status Register 0 (IICS0) (2/3) COI0 Detection of matching addresses Addresses do not match. Addresses match. Condition for clearing (COI0 = 0) Condition for setting (COI0 = 1) •...
  • Page 367 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-6. Format of IIC Status Register 0 (IICS0) (3/3) ACKD0 Detection of acknowledge (ACK) Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1) •...
  • Page 368 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-7. Format of IIC Flag Register 0 (IICF0) Note Address: FFABH After reset: 00H <7> <6> <1> <0> Symbol IICF0 STCF IICBSY STCEN IICRSV STCF STT0 clear flag Generate start condition...
  • Page 369 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (4) IIC clock selection register 0 (IICCL0) This register is used to set the transfer clock for the I C bus. IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only.
  • Page 370 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (5) IIC function expansion register 0 (IICX0) This register sets the function expansion of I IICX0 is set by a 1-bit or 8-bit memory manipulation instruction. The CLX0 bit is set in combination with bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) (see 15.3 (6) I...
  • Page 371 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0).
  • Page 372 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (7) Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0.
  • Page 373: I C Bus Mode Functions

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.4 I C Bus Mode Functions 15.4.1 Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. (1) SCL0..This pin is used for serial clock input and output.
  • Page 374: I C Bus Definitions And Control Methods

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. Figure 15-12 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I bus’s serial data bus.
  • Page 375: Addresses

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
  • Page 376: Acknowledge (Ack)

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.
  • Page 377: Stop Condition

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5.5 Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed.
  • Page 378: Wait

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin.
  • Page 379 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-18. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master and slave both wait after output of ninth clock...
  • Page 380: Canceling Wait

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5.7 Canceling wait The I C usually cancels a wait state by the following processing. • Writing data to IIC shift register 0 (IIC0) • Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait) •...
  • Page 381: Interrupt Request (Intiic0) Generation Timing And Wait Control

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5.8 Interrupt request (INTIIC0) generation timing and wait control The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated and the corresponding wait control, as shown in Table 15-3.
  • Page 382: Address Match Detection Method

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (4) Wait cancellation method The four wait cancellation methods are as follows. • Writing data to IIC shift register 0 (IIC0) • Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait) •...
  • Page 383: Extension Code

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5.11 Extension code (1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXC0) is set to 1 for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge of the eighth clock.
  • Page 384: Arbitration

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5.12 Arbitration When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration.
  • Page 385 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Table 15-5. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 During address transmission At falling edge of eighth or ninth clock following byte transfer...
  • Page 386: Wakeup Function

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5.13 Wakeup function The I C bus slave function is a function that generates an interrupt request signal (INTIIC0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIIC0 signal from occurring when addresses do not match.
  • Page 387 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Table 15-6. Wait Periods CLX0 SMC0 CL01 CL00 Wait Period 46 clocks 86 clocks 172 clocks 34 clocks 30 clocks 60 clocks 12 clocks 18 clocks 36 clocks Figure 15-20 shows the communication reservation timing.
  • Page 388 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-21. Timing for Accepting Communication Reservations SCL0 SDA0 STD0 SPD0 Standby mode Figure 15-22 shows the communication reservation protocol. Figure 15-22. Communication Reservation Protocol SET1 STT0 Sets STT0 flag (communication reservation)
  • Page 389 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (2) When communication reservation function is disabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 1) When bit 1 (STT0) of IIC control register 0 (IICC0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.
  • Page 390: Cautions

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5.15 Cautions (1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0 Immediately after I C operation is enabled (IICE0 = 1), the bus communication status (IICBSY flag (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status.
  • Page 391: Communication Operations

    The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the R7F0C011B, R7F0C012B, and R7F0C012B as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup.
  • Page 392 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (1) Master operation in single-master system Figure 15-23. Master Operation in Single-Master System START Note Initializing I C bus IICX0 ← 0XH Selects a transfer clock. IICCL0 ← XXH SVA0 ← XXH Sets a local address.
  • Page 393 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (2) Master operation in multi-master system Figure 15-24. Master Operation in Multi-Master System (1/3) START IICX0 ← 0XH Selects a transfer clock. IICCL0 ← XXH SVA0 ← XXH Sets a local address.
  • Page 394 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-24. Master Operation in Multi-Master System (2/3) Enables reserving communication. Prepares for starting communication STT0 = 1 (generates a start condition). Secure wait time by software Wait (see Table 15-6). MSTS0 = 1?
  • Page 395 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-24. Master Operation in Multi-Master System (3/3) Starts communication Writing IIC0 (specifies an address and transfer direction). INTIIC0 interrupt occurs? Waits for detection of ACK. MSTS0 = 1? ACKD0 = 1?
  • Page 396 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIIC0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary.
  • Page 397 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 The main processing of the slave operation is explained next. Start serial interface IIC0 and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt.
  • Page 398 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the following operations are performed.
  • Page 399: Timing Of I 2 C Interrupt Request (Intiic0) Occurrence

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.5.17 Timing of I C interrupt request (INTIIC0) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIIC0, and the value of the IICS0 register when the INTIIC0 signal is generated are shown below.
  • Page 400 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 1000×110B...
  • Page 401 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 SPT0 = 1 ↓ ↓ AD6 to AD0 R/W ACK...
  • Page 402 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 1010×110B...
  • Page 403 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0001×110B...
  • Page 404 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) AD6 to AD0 R/W ACK D7 to D0...
  • Page 405 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) AD6 to AD0 R/W ACK...
  • Page 406 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK...
  • Page 407 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIM0 = 0...
  • Page 408 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0010×010B...
  • Page 409 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) AD6 to AD0 R/W ACK D7 to D0...
  • Page 410 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK...
  • Page 411 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1...
  • Page 412 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0101×110B 2: IICS0 = 0001×100B 3: IICS0 = 0001××00B 4: IICS0 = 00000001B...
  • Page 413 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0110×010B 2: IICS0 = 0010×110B 3: IICS0 = 0010×100B 4: IICS0 = 0010××00B...
  • Page 414 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (b) When arbitration loss occurs during transmission of extension code AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0110×010B Sets LREL0 = 1 by software 2: IICS0 = 00000001B...
  • Page 415 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 10001110B 2: IICS0 = 01000100B 3: IICS0 = 00000001B Remark : Always generated...
  • Page 416 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (ii) Extension code AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 01100010B Sets LREL0 = 1 by software 3: IICS0 = 00000001B...
  • Page 417 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0...
  • Page 418 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 1: IICS0 = 1000×110B...
  • Page 419 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0...
  • Page 420: Timing Charts

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 15.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
  • Page 421 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 ← address IIC0 ← data Note 1...
  • Page 422 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (2) Data Processing by master device IIC0 ← data Note 1 IIC0 ← data Note 1...
  • Page 423 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (3) Stop condition Processing by master device IIC0 ← data Note 1 IIC0 ← address...
  • Page 424 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-28. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 ← address IIC0 ←...
  • Page 425 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-28. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Data Processing by master device IIC0 ← FFH Note 1 IIC0 ←...
  • Page 426 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 15 SERIAL INTERFACE IIC0 Figure 15-28. Example of Slave to Master Communication (When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Stop condition Processing by master device IIC0 ← address IIC0 ←...
  • Page 427: Chapter 16 Interrupt Functions

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS CHAPTER 16 INTERRUPT FUNCTIONS 16.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H).
  • Page 428 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (1/2) Interrupt Internal/ Basic Default Interrupt Source Vector Note 2 Type External Configuration Priority Table Name Trigger Note 1 Type Address Note 3 Maskable Internal INTLVI Low-voltage detection...
  • Page 429 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (2/2) Interrupt Internal/ Basic Default Interrupt Source Vector Note 2 Type External Configuration Priority Table Name Trigger Note 1 Type Address Maskable Internal INTWT Watch timer overflow 002EH...
  • Page 430 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal (B) External maskable interrupt (INTPn) Internal bus External interrupt edge...
  • Page 431 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (2/2) (C) Software interrupt Internal bus Interrupt Vector table Priority controller address generator request Interrupt request flag Interrupt enable flag ISP: In-service priority flag Interrupt mask flag Priority specification flag R01UH0408EJ0001 Rev.0.01...
  • Page 432: Registers Controlling Interrupt Functions

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS 16.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L, IF1H) • Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H) •...
  • Page 433 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources (2/2) Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register Register INTAD ADIF IF1L ADMK MK1L ADPR PR1L INTSR0 SRIF0 SRMK0...
  • Page 434 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
  • Page 435 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) Address: FFE0H After reset: 00H R/W Symbol <7> <5> <4> <3> <1> <0> IF0L SREIF6 PIF4 PIF3 PIF2 PIF0 LVIIF Address: FFE1H...
  • Page 436 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction.
  • Page 437 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction.
  • Page 438 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTPn. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 439 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.
  • Page 440: Interrupt Servicing Operations

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS 16.4 Interrupt Servicing Operations 16.4.1 Maskable interrupt acknowledgment A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
  • Page 441 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority...
  • Page 442: Software Interrupt Request Acknowledgment

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing jump to interrupt Instruction Instruction program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0)
  • Page 443: Multiple Interrupt Servicing

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS 16.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1).
  • Page 444 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx...
  • Page 445 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0)
  • Page 446: Interrupt Request Hold

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 16 INTERRUPT FUNCTIONS 16.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
  • Page 447: Chapter 17 Standby Function

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION CHAPTER 17 STANDBY FUNCTION 17.1 Standby Function and Configuration 17.1.1 Standby function The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode.
  • Page 448: Registers Controlling Standby Function

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION 17.1.2 Registers controlling standby function The standby function is controlled by the following two registers. • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
  • Page 449 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
  • Page 450: Standby Function Operation

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION 17.2 Standby Function Operation 17.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock or internal high-speed oscillation clock.
  • Page 451 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
  • Page 452 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
  • Page 453: Stop Mode

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION 17.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the main system clock.
  • Page 454 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION Table 17-3. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on...
  • Page 455 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware.
  • Page 456 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
  • Page 457 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION Figure 17-6. STOP Mode Release by Interrupt Request Generation (2/2) (3) When internal high-speed oscillation clock is used as CPU clock Interrupt request STOP instruction Standby release signal Normal operation Normal operation (internal high-speed...
  • Page 458 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 17 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
  • Page 459: Chapter 18 Reset Function

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 18 RESET FUNCTION CHAPTER 18 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
  • Page 460 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 18 RESET FUNCTION R01UH0408EJ0001 Rev.0.01 Sep 25, 2012...
  • Page 461 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 18 RESET FUNCTION Figure 18-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization μ (86 to 361 s) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected)
  • Page 462 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 18 RESET FUNCTION Figure 18-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation accuracy stabilization STOP instruction execution μ (86 to 361 s) Internal high-speed oscillation clock Starting X1 oscillation is specified by software.
  • Page 463 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 18 RESET FUNCTION Table 18-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped Operation stopped (pin is I/O port mode) Clock input invalid (pin is I/O port mode)
  • Page 464 The initial value of the internal memory size switching register (IMS) after a reset release is constant (IMS = CFH) in all products of the R7F0C011B, R7F0C012B, and R7F0C013B, regardless of the internal memory capacity. Therefore, set the value corresponding to each product as indicated in Tables 3-1 and 3-2.
  • Page 465 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 18 RESET FUNCTION Table 18-2. Hardware Statuses After Reset Acknowledgment (2/4) Hardware Status After Reset Note 1 Acknowledgment Clock operation mode select register (OSCCTL) Processor clock control register (PCC) Internal oscillation mode register (RCM) Main OSC control register (MOC)
  • Page 466 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 18 RESET FUNCTION Table 18-2. Hardware Statuses After Reset Acknowledgment (3/4) Hardware Status After Reset Note Acknowledgment Serial interface UART6 Receive buffer register 6 (RXB6) Transmit buffer register 6 (TXB6) Asynchronous serial interface operation mode register 6 (ASIM6)
  • Page 467 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 18 RESET FUNCTION Table 18-2. Hardware Statuses After Reset Acknowledgment (4/4) Hardware Status After Reset Note 1 Acknowledgment Note 2 Reset function Reset control flag register (RESF) Note 2 Low-voltage detector Low-voltage detection register (LVIM) Note 2...
  • Page 468: Register For Confirming Reset Source

    CHAPTER 18 RESET FUNCTION 18.1 Register for Confirming Reset Source Many internal reset generation sources exist in the R7F0C011B, R7F0C012B, and R7F0C013B. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction.
  • Page 469: Chapter 19 Power-On-Clear Circuit

    Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. Remark R7F0C011B, R7F0C012B, and R7F0C013B incorporate multiple hardware functions that generate an internal reset signal. A flag that indicates the reset source is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT) or low-voltage- detector (LVI).
  • Page 470: Configuration Of Power-On-Clear Circuit

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 19 POWER-ON-CLEAR CIRCUIT 19.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 19-1. Figure 19-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Reference voltage source 19.3 Operation of Power-on-Clear Circuit (1) In 1.59 V POC mode (option byte: POCMODE = 0)
  • Page 471 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 19 POWER-ON-CLEAR CIRCUIT Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Set LVI to be Set LVI to be...
  • Page 472 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 19 POWER-ON-CLEAR CIRCUIT Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Set LVI to be Set LVI to be...
  • Page 473: Cautions For Power-On-Clear Circuit

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 19 POWER-ON-CLEAR CIRCUIT 19.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
  • Page 474 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 19 POWER-ON-CLEAR CIRCUIT Figure 19-3. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1?
  • Page 475: Chapter 20 Low-Voltage Detector

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR CHAPTER 20 LOW-VOLTAGE DETECTOR 20.1 Functions of Low-Voltage Detector The low-voltage detector has the following functions. • The LVI circuit compares the supply voltage (V ) with the detection voltage (V ) or the input voltage from an external input pin (EXLVI) with the detection voltage (V = 1.21 V (TYP.): fixed), and generates an internal reset...
  • Page 476: Registers Controlling Low-Voltage Detector

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR Figure 20-1. Block Diagram of Low-Voltage Detector N-ch Internal reset signal EXLVI/P120/ INTP0 − INTLVI Reference voltage source Low-voltage detection level Low-voltage detection register selection register (LVIS) (LVIM) Internal bus 20.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers.
  • Page 477 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR Figure 20-2. Format of Low-Voltage Detection Register (LVIM) Note 1 Note 2 Address: FFBEH After reset: 00H <7> <2> <1> <0> Symbol LVION LVISEL LVIMD LVIF LVIM Notes 3, 4 LVION Enables low-voltage detection operation...
  • Page 478 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. The generation of a reset signal other than an LVI reset clears this register to 00H.
  • Page 479: Operation Of Low-Voltage Detector

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR (3) Port mode register 12 (PM12) When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time, the output latch of P120 may be 0 or 1.
  • Page 480: When Used As Reset

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR 20.4.1 When used as reset (1) When detecting level of supply voltage (V • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (V (default value).
  • Page 481 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR Figure 20-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (V )) (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Supply voltage (V = 1.59 V (TYP.)
  • Page 482 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR Figure 20-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (V )) (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (V 2.7 V (TYP.)
  • Page 483 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)).
  • Page 484 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR Figure 20-6. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) LVI detection voltage EXLVI Time LVIMK flag...
  • Page 485: When Used As Interrupt

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR 20.4.2 When used as interrupt (1) When detecting level of supply voltage (V • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (V (default value).
  • Page 486 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR Figure 20-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (V )) (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Supply voltage (V = 1.59 V (TYP.)
  • Page 487 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR Figure 20-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (V )) (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (V 2.7 V(TYP.) = 1.59 V (TYP.)
  • Page 488 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)).
  • Page 489 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR Figure 20-8. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) EXLVI Note 3 Time Note 3 LVIMK flag (set by software) <1>...
  • Page 490: Cautions For Low-Voltage Detector

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR 20.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used.
  • Page 491 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR Figure 20-9. Example of Software Processing After Reset Release (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Note ; Check the reset source Initialization Initialize the port.
  • Page 492 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 20 LOW-VOLTAGE DETECTOR Figure 20-9. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source Yes: Reset generation by LVI LVION of LVIM register = 1? No: Reset generation other than by LVI...
  • Page 493: Chapter 21 Option Byte

    21.1 Functions of Option Bytes The flash memory at 0080H to 0084H of the R7F0C011B, R7F0C012B, and R7F0C013B is an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions.
  • Page 494: Format Of Option Byte

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 21 OPTION BYTE 21.2 Format of Option Byte The format of the option byte is shown below. Figure 21-1. Format of Option Byte (1/2) Address: 0080H WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 LSROSC WINDOW1 WINDOW0 Watchdog timer window open period...
  • Page 495 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 21 OPTION BYTE Figure 21-1. Format of Option Byte (2/2) Note Address: 0081H POCMODE POCMODE POC mode selection 1.59 V POC mode (default) 2.7 V/1.59 V POC mode Note To change the setting for the POC mode, set the value to 0081H again after batch erasure (chip erasure) of the flash memory.
  • Page 496: Chapter 22 Flash Memory

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 22 FLASH MEMORY CHAPTER 22 FLASH MEMORY The R7F0C011B, R7F0C012B, and R7F0C013B incorporate the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 22.1 Internal Memory Size Switching Register Select the internal memory capacity using the internal memory size switching register (IMS).
  • Page 497: Writing With Flash Memory Programmer

    (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the R7F0C011B, R7F0C012B, and R7F0C013B is mounted on the target system. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
  • Page 498: Communication Mode

    22.4 Communication Mode Communication between the dedicated flash memory programmer and the R7F0C011B, R7F0C012B, and R7F0C013B is established by serial communication via CSI10 or UART6 of the R7F0C011B, R7F0C012B, and R7F0C013B. (1) CSI10 Transfer rate: 2.4 kHz to 2.5 MHz Figure 22-3.
  • Page 499 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 22 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the R7F0C011B, R7F0C012B, and R7F0C013B. For details, refer to the user’s manual for the PG-FP5 or FL-PR5. Table 22-2. Pin Connection Dedicated Flash memory programmer...
  • Page 500: Connection Of Pins On Board

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 22 FLASH MEMORY For the pins not to be used when the dedicated program adapter (FA series) is used, perform the processing described under the recommended connection of unused pins shown in Table 22-3 Processing of Unused Pins When the Flash Memory Write Adapter Is Connected (Required).
  • Page 501: Flmd0 Pin

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 22 FLASH MEMORY 22.5.1 FLMD0 pin In the normal operation mode, 0 V is input to the FLMD0 pin. In the flash memory programming mode, the V write voltage is supplied to the FLMD0 pin. An FLMD0 pin connection example is shown below.
  • Page 502: Reset Pin

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 22 FLASH MEMORY (2) Malfunction of other device If the dedicated flash memory programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction. To avoid this malfunction, isolate the connection with the other device.
  • Page 503: Port Pins

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 22 FLASH MEMORY Figure 22-8. Signal Collision (RESET Pin) R7F0C011B, R7F0C012B, R7F0C013B Dedicated flash memory Signal collision programmer connection signal RESET Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash memory programmer.
  • Page 504: Programming Method

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 22 FLASH MEMORY 22.6 Programming Method 22.6.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 22-9. Flash Memory Manipulation Procedure Start Flash memory programming mode is set Selecting communication mode...
  • Page 505: Flash Memory Programming Mode

    22.6.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the R7F0C011B, R7F0C012B, and R7F0C013B in the flash memory programming mode. To set the mode, set the FLMD0 pin to V clear the reset signal.
  • Page 506: Selecting Communication Mode

    R7F0C013B memory programmer The flash memory control commands of the R7F0C011B, R7F0C012B, and R7F0C013B are listed in the table below. All these commands are issued from the programmer and the R7F0C011B, R7F0C012B, and R7F0C013B perform processing corresponding to the respective commands.
  • Page 507 Oscillating Frequency Set Specifies an oscillation frequency. The R7F0C011B, R7F0C012B, and R7F0C013B return a response for the command issued by the dedicated flash memory programmer. The response names sent from the R7F0C011B, R7F0C012B, and R7F0C013B are listed below. Table 22-8. Response Names...
  • Page 508: Security Settings

    Prohibition of erasing blocks and writing is cleared by executing the batch erase (chip erase) command. Table 22-9 shows the relationship between the erase and write commands when the R7F0C011B, R7F0C012B, and R7F0C013B security function is enabled.
  • Page 509 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 22 FLASH MEMORY Table 22-9. Relationship Between Enabling Security Function and Command • During on-board/off-board programming Valid Security Executed Command Batch Erase (Chip Erase) Block Erase Write Note Prohibition of batch erase (chip erase) Cannot be erased in batch Blocks cannot be erased.
  • Page 510: Chapter 23 Instruction Set

    CHAPTER 23 INSTRUCTION SET CHAPTER 23 INSTRUCTION SET This chapter lists each instruction set of the R7F0C011B, R7F0C012B, and R7F0C013B in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E).
  • Page 511: Conventions Used In Operation List

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET 23.1 Conventions Used in Operation List 23.1.1 Operand identifiers and specification methods Operands are written in the “Operand” column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more methods, select one of them.
  • Page 512: Description Of Operation Column

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET 23.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair...
  • Page 513: Operation List

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET 23.2 Operation List Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − r ← byte 8-bit data r, #byte transfer (saddr) ← byte saddr, #byte −...
  • Page 514 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − rp ← word 16-bit data MOVW rp, #word transfer (saddrp) ← word saddrp, #word − sfrp ← word sfrp, #word AX ←...
  • Page 515 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A, CY ← A − byte × × × 8-bit A, #byte operation (saddr), CY ← (saddr) − byte ×...
  • Page 516 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A ← A ∨ byte × 8-bit A, #byte operation (saddr) ← (saddr) ∨ byte × saddr, #byte −...
  • Page 517 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − AX, CY ← AX + word × × × 16-bit ADDW AX, #word operation − AX, CY ← AX − word ×...
  • Page 518 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 CY ← CY ∧ (saddr.bit) × AND1 CY, saddr.bit manipulate − CY ← CY ∧ sfr.bit × CY, sfr.bit −...
  • Page 519 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) Call/return CALL !addr16 PC ←...
  • Page 520 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 Conditional saddr.bit, $addr16 branch − PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16...
  • Page 521: Instructions Listed By Addressing Type

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET 23.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ R01UH0408EJ0001 Rev.0.01...
  • Page 522 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET Note Second Operand #byte saddr !addr16 [DE] [HL] [HL + byte] $addr16 None [HL + B] First Operand [HL + C] ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC SUBC SUBC...
  • Page 523 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW...
  • Page 524 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 23 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ...
  • Page 525: Chapter 24 Electrical Specifications (Target)

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) Caution These specifications show target values, which may change after device evaluation. Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit −0.5 to +6.5 Supply voltage −0.5 to +0.3...
  • Page 526 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit −10 Output current, high Per pin P00, P01, P10 to P17, P30 to P33, P40, P41, P70, P71, P120 −25...
  • Page 527 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) X1 Oscillator Characteristics = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Note 2 Ceramic X1 clock 10.0...
  • Page 528 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (1/5) = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit −3.0 Note 1 Output current, high Per pin for P00, P01, P10 to P17, P30 to P33, P40, P41, P70, P71, P120 −20.0...
  • Page 529 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (2/5) = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high P40, P41, P121, P122 0.7V...
  • Page 530 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (3/5) = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output voltage, low = 8.5 mA P00, P01, P10 to P17,...
  • Page 531 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (4/5) = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1 Operating = 10 MHz, Supply current...
  • Page 532 The current value of the R7F0C011B, R7F0C012B, and R7F0C013B is the sum of I or I and I when the watchdog timer operates. Current flowing only to the LVI circuit. The current value of the R7F0C011B, R7F0C012B, and R7F0C013B is the sum of I or I and I when the LVI circuit operates.
  • Page 533 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) AC Characteristics (1) Basic operation = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit μ Instruction cycle (minimum Main system clock (f...
  • Page 534 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) vs. V (Main System Clock Operation) 0.01 Supply voltage V R01UH0408EJ0001 Rev.0.01 Sep 25, 2012...
  • Page 535 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) AC Timing Test Points Test points External Main System Clock Timing, External Subsystem Clock Timing EXCLK EXCLKL EXCLKH 0.7V (MIN.) EXCLK 0.3V (MAX.) TI Timing TIL0 TIH0 TI000, TI010 TIL5 TIH5 TI50, TI51...
  • Page 536 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) (2) Serial interface = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = 0 V) (a) UART6 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. MAX. Unit...
  • Page 537 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) (d) CSI10 (master mode, SCK10... internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK10 cycle time KCY1 /2 − SCK10 high-/low-level width KCY1 Note 1 SI10 setup time (to SCK10↑) SIK1 SI10 hold time (from SCK10↑)
  • Page 538 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) Serial Transfer Timing IIC0: SCL0 HD: DAT HIGH SU: STA HD: STA SU: STO HD: STA SU: DAT SDA0 Stop Start Restart Stop condition condition condition condition CSI10: KCYm SCK10 SIKm KSIm...
  • Page 539 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) A/D Converter Characteristics = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution ±0.4 Notes 1, 2 Overall error %FSR μ...
  • Page 540 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C, V Supply Voltage Rise Time (T = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Maximum time to rise to 4.0 V (V (MIN.)) POCMODE (option byte) = 0, PUP1 : 0 V →...
  • Page 541 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C, V ≤ V ≤ 5.5 V, V LVI Circuit Characteristics (T = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection Supply voltage level 4.14 4.24 4.34...
  • Page 542 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET) Flash Memory Programming Characteristics = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = 0 V) • Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit supply current 11.0...
  • Page 543: Chapter 25 Package Drawings

    R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 25 PACKAGE DRAWINGS CHAPTER 25 PACKAGE DRAWINGS • R7F0C011B2DFP R7F0C012B2DFP R7F0C013B2DFP 32-PIN PLASTIC LQFP(7x7) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 7.00±0.10 7.00±0.10 9.00±0.20 9.00±0.20 1.70 MAX. 0.10±0.10 1.40 0.37±0.05 0.145 ±0.055 0.50±0.20 NOTE θ...
  • Page 544 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 26 CAUTIONS FOR WAIT CHAPTER 26 CAUTIONS FOR WAIT 26.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware.
  • Page 545 R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 26 CAUTIONS FOR WAIT 26.2 Peripheral Hardware That Generates Wait Table 26-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 26-1. Registers That Generate Wait and Number of CPU Wait Clocks...
  • Page 546 R7F0C011B, R7F0C012B, R7F0C013B User’s Manual: Hardware Publication Date: Rev.0.01 Sep 25, 2012 Published by: Renesas Electronics Corporation...
  • Page 547 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada...
  • Page 548 R7F0C011B, R7F0C012B, R7F0C013B R01UH0408EJ0001...

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