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Renesas Synergy S3A3 Series User Manual

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S3A3 Microcontroller Group

Renesas Synergy™ Platform

Synergy Microcontrollers

S3 Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual

Rev.1.10

Jul 2018

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Summary of Contents for Renesas Synergy S3A3 Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.
Page 3 General Precautions 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs.
Page 4 Audience This manual is written for system designers who are designing and programming applications using the Renesas Synergy Microcontroller. The user is expected to have basic knowledge of electrical circuits, logic circuits, and the MCU.
Page 5 Numbering Notation The following numbering notation is used throughout this manual: Example Description 011b Binary number. For example, the binary equivalent of the number 3 is 011b. Hexadecimal number. For example, the hexadecimal equivalent of the number 31 is described 1Fh. In some cases, a hexadecimal number is shown with the prefix 0x, based on C/C++ formatting.
Page 6 Register Description Each register description includes both a register diagram that shows the bit assignments and a register bit table that describes the content of each bit. The example of symbols used in these tables are described in the sections that follow. The following is an example of a register description and associated bit field definition.
Page 7 Abbreviations Abbreviations used in this manual are shown in the following table: Abbreviation Description Advanced Encryption Standard Advanced High-Performance Bus AHB-AP AHB Access Port Advanced Peripheral Bus Alleged RC Advanced Trace Bus Binary Coded Decimal BSDL Boundary Scan Description Language Data Encryption Standard Digital Signature Algorithm Elliptic Curve Cryptography...
Page 8 All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein,...
Page 9 If you have any comments on the document such as general suggestions for improvements, go to renesassynergy.com/support, and provide: - The title of the Renesas Synergy document - The document number - If applicable, the page number(s) to which your comments refer...
Page 10 Contents Features ..............................53 Overview ............................54 Function Outline........................54 Block Diagram ........................60 Part Numbering........................60 Function Comparison......................62 Pin Functions ........................63 Pin Assignments ........................67 Pin Lists ..........................74 CPU ..............................79 Overview..........................79 2.1.1 CPU ..........................79 2.1.2 Debug ...........................
Page 11 Flash Patch and Break Unit ....................90 SysTick System Timer ......................90 2.10 CoreSight Time Stamp Generator ..................90 2.11 OCD Emulator Connection ....................90 2.11.1 DBGEN......................... 91 2.11.2 Unlock ID Code ......................91 2.11.3 Restrictions on Connecting an OCD Emulator ............. 91 2.11.3.1 Starting connection while in low power mode ............
Page 12 6.3.4 Independent Watchdog Timer Reset................113 6.3.5 Watchdog Timer Reset....................113 6.3.6 Software Reset ......................113 6.3.7 Determination of Cold/Warm Start................114 6.3.8 Determination of Reset Generation Source..............114 Option-Setting Memory ......................... 116 Overview..........................116 Register Descriptions......................116 7.2.1 Option Function Select Register 0 (OFS0) ..............
Page 13 Clock Generation Circuit ....................... 140 Overview..........................140 Register Descriptions......................143 9.2.1 System Clock Division Control Register (SCKDIVCR) ..........143 9.2.2 System Clock Source Control Register (SCKSCR)............ 145 9.2.3 PLL Clock Control Register 2 (PLLCCR2)..............146 9.2.4 PLL Control Register (PLLCR) ................... 146 9.2.5 External Bus Clock Control Register (BCKCR) ............
Page 14 9.7.2 Peripheral Module Clock (PCLKA, PCLKB, PCLKC, PCLKD) ........170 9.7.3 Flash Interface Clock (FCLK) ..................170 9.7.4 External Bus Clock (BCLK) ..................170 9.7.5 USB Clock (UCLK) ..................... 170 9.7.6 CAN Clock (CANMCLK) ..................... 170 9.7.7 CAC Clock (CACCLK) ....................171 9.7.8 RTC-Dedicated Clock (RTCSCLK, RTCLCLK) ............
Page 15 11.2.4 Module Stop Control Register C (MSTPCRC)............188 11.2.5 Module Stop Control Register D (MSTPCRD)............189 11.2.6 Operating Power Control Register (OPCCR) ............. 190 11.2.7 Sub Operating Power Control Register (SOPCCR) ........... 190 11.2.8 Snooze Control Register (SNZCR)................191 11.2.9 Snooze End Control Register (SNZEDCR) ..............
Page 16 11.9.14 Module-Stop Function for ADC140................214 11.9.15 Module-Stop Function for an Unused Circuit.............. 214 Battery Backup Function....................... 215 12.1 Overview..........................215 12.1.1 Features of Battery Backup Function ................. 215 12.1.2 Battery Power Supply Switch ..................215 12.1.3 VBATT Pin Low Voltage Detection................215 12.1.4 VBATT_R Low Voltage Detection ................
Page 17 14.2 Register Descriptions......................237 14.2.1 IRQ Control Register i (IRQCRi) (i = 0 to 15) ............. 238 14.2.2 Non-Maskable Interrupt Status Register (NMISR)............239 14.2.3 Non-Maskable Interrupt Enable Register (NMIER) ............ 242 14.2.4 Non-Maskable Interrupt Status Clear Register (NMICLR).......... 243 14.2.5 NMI Pin Interrupt Control Register (NMICR) ..............
Page 18 15.3.4 CSn Mode Register (CSnMOD) (n = 0 to 3) ............... 272 15.3.5 CSn Wait Control Register 1 (CSnWCR1) (n = 0 to 3) ..........274 15.3.6 CSn Wait Control Register 2 (CSnWCR2) (n = 0 to 3) ..........276 15.3.7 Master Bus Control Register (BUSMCNT<master>) ..........
Page 19 16.4.1.2 Group A Region n End Address Register (MMPUEAn) (n = 0 to 15) ....321 16.4.1.3 Group A Region n Access Control Register (MMPUACAn) (n = 0 to 15)... 321 16.4.1.4 Bus Master MPU Control Register (MMPUCTLA)..........323 16.4.1.5 Group A Protection of Register (MMPUPTA) .............
Page 20 DMA Controller (DMAC) ....................... 343 17.1 Overview..........................343 17.2 Register Descriptions......................345 17.2.1 DMA Source Address Register (DMSAR) ..............345 17.2.2 DMA Destination Address Register (DMDAR) ............345 17.2.3 DMA Transfer Count Register (DMCRA)..............346 17.2.4 DMA Block Transfer Count Register (DMCRB) ............
Page 21 Data Transfer Controller (DTC)..................... 373 18.1 Overview..........................373 18.2 Register Descriptions......................374 18.2.1 DTC Mode Register A (MRA) ..................375 18.2.2 DTC Mode Register B (MRB) ..................375 18.2.3 DTC Transfer Source Register (SAR) ................ 376 18.2.4 DTC Transfer Destination Register (DAR) ..............377 18.2.5 DTC Transfer Count Register A (CRA) ..............
Page 22 19.2.3 Event Link Setting Register n (ELSRn) (n = 0 to 9, 12, 14 to 18) ....... 400 19.3 Operation ..........................405 19.3.1 Relation between Interrupt Handling and Event Linking..........405 19.3.2 Linking Events ......................405 19.3.3 Example of Procedure for Linking Events ..............406 19.4 Usage Notes ........................
Page 23 21.2.3 Key Return Mode Register (KRM)................436 21.3 Operation ..........................437 21.3.1 Operation When Not Using Key Interrupt Flag (KRMD = 0) ........437 21.3.2 Operation When Using Key Interrupt Flag (KRMD = 1) ..........437 21.4 Usage Notes ........................439 Port Output Enable for GPT (POEG) ....................
Page 24 23.2.18 General PWM Timer Counter (GTCNT) ..............483 23.2.19 General PWM Timer Compare Capture Register n (GTCCRn) (n = A to F)....484 23.2.20 General PWM Timer Cycle Setting Register (GTPR)..........484 23.2.21 General PWM Timer Cycle Setting Buffer Register (GTPBR)........485 23.2.22 General PWM Timer Dead Time Control Register (GTDTCR)........
Page 25 23.4 Interrupt Sources ........................ 557 23.4.1 Interrupt Sources ......................557 23.4.2 DMAC/DTC Activation ....................561 23.5 Operations Linked by ELC....................561 23.5.1 Event Signal Output to ELC..................561 23.5.2 Event Signal Inputs from ELC ..................562 23.6 Noise Filter Function......................562 23.7 Protection Function......................
Page 26 24.3.8 Compare Match Function ................... 585 24.3.9 Output Settings for each Mode................... 587 24.3.10 Standby Mode ......................588 24.3.11 Interrupt Sources ......................588 24.3.12 Event Signal Output to ELC..................589 24.4 Usage Notes ........................589 24.4.1 Count Operation Start and Stop Control..............589 24.4.2 Access to Counter Register..................
Page 27 25.2.19 RTC Control Register 4 (RCR4) ................. 611 25.2.20 Frequency Register (RFRH/RFRL) ................612 25.2.21 Time Error Adjustment Register (RADJ)..............613 25.2.22 Time Capture Control Register y (RTCCRy) (y = 0 to 2) ..........613 25.2.23 Second Capture Register y (RSECCPy) (y = 0 to 2)/BCNT0 Capture Register y (BCNT0CPy) (y = 0 to 2) ....................
Page 28 26.2.2 WDT Control Register (WDTCR)................633 26.2.3 WDT Status Register (WDTSR) ................. 635 26.2.4 WDT Reset Control Register (WDTRCR)..............636 26.2.5 WDT Count Stop Control Register (WDTCSTPR)............637 26.2.6 Option Function Select Register 0 (OFS0) ..............637 26.3 Operation ..........................637 26.3.1 Count Operation in Each Start Mode................
Page 29 28.2.3 Device State Control Register 0 (DVSTCTR0) ............658 28.2.4 CFIFO Port Register (CFIFO/CFIFOL) D0FIFO Port Register (D0FIFO/D0FIFOL) D1FIFO Port Register (D1FIFO/D1FIFOL)..............660 28.2.5 CFIFO Port Select Register (CFIFOSEL) D0FIFO Port Select Register (D0FIFOSEL) D1FIFO Port Select Register (D1FIFOSEL)............... 662 28.2.6 CFIFO Port Control Register (CFIFOCTR)
Page 30 28.3.1.3 Controlling the USBFS data bus using resistors ..........702 28.3.1.4 Example of USBFS power supply connection............ 703 28.3.1.5 Example of USB external connection circuits............. 705 28.3.2 Interrupt Sources ......................711 28.3.3 Interrupt Descriptions ....................715 28.3.3.1 BRDY interrupt ....................715 28.3.3.2 NRDY interrupt ....................
Page 31 28.3.11 Interrupt Transfers (Pipes 6 to 9)................733 28.3.11.1 Interval counter for interrupt transfers in host controller mode......734 28.3.12 Isochronous Transfers (Pipes 1 and 2) ..............734 28.3.12.1 Error detection in isochronous transfers............. 734 28.3.12.2 DATA-PID......................735 28.3.12.3 Interval counter....................735 28.3.13 SOF Interpolation Function..................
Page 32 29.2.16 Smart Card Mode Register (SCMR)................770 29.2.17 Bit Rate Register (BRR) ..................... 772 29.2.18 Modulation Duty Register (MDDR) ................779 29.2.19 Serial Extended Mode Register (SEMR) ..............781 29.2.20 Noise Filter Setting Register (SNFR)................783 29.2.21 C Mode Register 1 (SIMR1)..................
Page 33 29.6.4 Receive Data Sampling Timing and Reception Margin ..........843 29.6.5 SCI Initialization......................844 29.6.6 Serial Data Transmission (Except in Block Transfer Mode) ........846 29.6.7 Serial Data Reception (Except in Block Transfer Mode) ........... 848 29.6.8 Clock Output Control ....................850 29.7 Operation in Simple IIC Mode.....................
Page 34 C Bus Interface (IIC)........................878 30.1 Overview..........................878 30.2 Register Descriptions......................881 30.2.1 C Bus Control Register 1 (ICCR1) ................881 30.2.2 C Bus Control Register 2 (ICCR2) ................883 30.2.3 C Bus Mode Register 1 (ICMR1) ................886 30.2.4 C Bus Mode Register 2 (ICMR2) ................
Page 35 30.8.4 Precautions for WFI Instruction Execution ..............936 30.9 Automatic Low-Hold Function for SCL................936 30.9.1 Function to Prevent Wrong Transmission of Transmit Data........936 30.9.2 NACK Reception Transfer Suspension Function ............937 30.9.3 Function to Prevent Failure to Receive Data.............. 938 30.10 Arbitration-Lost Detection Functions...................
Page 36 31.2.10 Message Control Register for Receive (MCTL_RXj) (j = 0 to 31)....... 970 31.2.11 Receive FIFO Control Register (RFCR) ..............971 31.2.12 Receive FIFO Pointer Control Register (RFPCR) ............973 31.2.13 Transmit FIFO Control Register (TFCR)..............974 31.2.14 Transmit FIFO Pointer Control Register (TFPCR)............
Page 37 32.2.3 SPI Pin Control Register (SPPCR)................1006 32.2.4 SPI Status Register (SPSR) ..................1007 32.2.5 SPI Data Register (SPDR/SPDR_HA) ..............1010 32.2.6 SPI Sequence Control Register (SPSCR)..............1014 32.2.7 SPI Sequence Status Register (SPSSR)..............1014 32.2.8 SPI Bit Rate Register (SPBR) ..................
Page 38 32.3.9.2 Initialization by system reset ................1049 32.3.10 SPI Operation ......................1049 32.3.10.1 Master mode operation ..................1049 32.3.10.2 Slave mode operation ..................1060 32.3.11 Clock Synchronous Operation.................. 1064 32.3.11.1 Master mode operation ..................1064 32.3.11.2 Slave mode operation ..................1071 32.3.12 Loopback mode ......................
Page 39 33.4 SPI Bus..........................1089 33.4.1 SPI Protocol......................1089 33.4.2 SPI Mode........................1091 33.5 SPI Bus Timing Adjustment ....................1092 33.5.1 SPI Bus Reference Cycles ..................1092 33.5.2 QSPCLK Signal Duty Ratio ..................1093 33.5.3 Minimum High-Level Width of QSSL Signal ............. 1094 33.5.4 QSSL Signal Setup Time..................
Page 40 33.12 Interrupt ..........................1112 33.13 Usage Note........................1112 33.13.1 Setting for the Module-Stop State ................1112 Cyclic Redundancy Check (CRC) Calculator................1113 34.1 Overview........................... 1113 34.2 Register Descriptions......................1114 34.2.1 CRC Control Register 0 (CRCCR0) ................. 1114 34.2.2 CRC Control Register 1 (CRCCR1) .................
Page 41 35.6.1 Idle State ........................1166 35.6.2 Communication States ..................... 1167 35.6.2.1 Data communication state................1168 35.6.2.2 Padding communication ................... 1170 35.7 Communication Operation ....................1171 35.7.1 Start Communication ....................1171 35.7.2 Transmission ......................1173 35.7.3 Reception ......................... 1173 35.7.4 Transmission and Reception ..................1174 35.7.5 Halt Communication ....................
Page 42 36.2.3 SD Command Argument Register 1 (SD_ARG1)............. 1187 36.2.4 Data Stop Register (SD_STOP) ................1187 36.2.5 Block Count Register (SD_SECCNT)............... 1188 36.2.6 SD Card Response Register 10 (SD_RSP10), SD Card Response Register 32 (SD_RSP32), SD Card Response Register 54 (SD_RSP54) ............1189 36.2.7 SD Card Response Register 1 (SD_RSP1),...
Page 43 36.3.7.1 Single block write operation ................1221 36.3.8 Multiple Block Read (SD/MMC)................1221 36.3.8.1 Multiple block read operation ................1222 36.3.9 Multiple Block Write (SD/MMC using internal timer)..........1223 36.3.9.1 Multiple block write operation using an internal timer........1224 36.3.10 Multiple Block Write (MMC using external timer)............
Page 44 38.2.3 A/D Control Register (ADCSR).................. 1252 38.2.4 A/D Channel Select Register A0 (ADANSA0) ............1256 38.2.5 A/D Channel Select Register A1 (ADANSA1) ............1257 38.2.6 A/D Channel Select Register B0 (ADANSB0) ............1257 38.2.7 A/D Channel Select Register B1 (ADANSB1) ............1258 38.2.8 A/D-Converted Value Addition/Average Channel Select Register 0 (ADADS0) ..
Page 45 38.3.2.4 A/D conversion in double trigger mode ............1285 38.3.2.5 Extended operations when double trigger mode is selected......1286 38.3.3 Continuous Scan Mode .................... 1287 38.3.3.1 Basic operation....................1287 38.3.3.2 Channel selection and self-diagnosis............... 1288 38.3.4 Group Scan Mode ....................1289 38.3.4.1 Basic operation....................
Page 46 12-Bit D/A Converter (DAC12)....................1315 39.1 Overview........................... 1315 39.2 Register Descriptions......................1316 39.2.1 D/A Data Register 0 (DADR0) .................. 1316 39.2.2 D/A Control Register (DACR) ................... 1316 39.2.3 DADR0 Format Select Register (DADPR)..............1317 39.2.4 D/A A/D Synchronous Start Control Register (DAADSCR) ........
Page 47 Low Power Analog Comparator (ACMPLP)................1339 42.1 Overview........................... 1339 42.2 Register Descriptions......................1342 42.2.1 ACMPLP Mode Setting Register (COMPMDR)............1342 42.2.2 ACMPLP Filter Control Register (COMPFIR)............1343 42.2.3 ACMPLP Output Control Register (COMPOCR)............1343 42.2.4 Comparator Input Select Register (COMPSEL0) ............. 1344 42.2.5 Comparator Reference Voltage Select Register (COMPSEL1)........
Page 48 44.2.11 CTSU Channel Enable Control Register 4 (CTSUCHAC4)........1364 44.2.12 CTSU Channel Transmit/Receive Control Register 0 (CTSUCHTRC0)....1364 44.2.13 CTSU Channel Transmit/Receive Control Register 1 (CTSUCHTRC1)....1365 44.2.14 CTSU Channel Transmit/Receive Control Register 2 (CTSUCHTRC2)....1365 44.2.15 CTSU Channel Transmit/Receive Control Register 3 (CTSUCHTRC3)....
Page 49 45.3.2 Data Addition Mode ....................1391 45.3.3 Data Subtraction Mode..................... 1391 45.4 Interrupt Request and Output to the Event Link Controller (ELC) ........1392 45.5 Usage Notes ........................1392 45.5.1 Settings for the Module-Stop State................1392 SRAM............................1393 46.1 Overview........................... 1393 46.2 Register Descriptions.......................
Page 50 47.6 Overview of Functions ...................... 1409 47.6.1 Configuration Area Bit Map ..................1411 47.6.2 Startup Area Select ....................1411 47.6.3 Protection by Access Window .................. 1412 47.7 Programming Commands....................1413 47.8 Suspend Operation......................1413 47.9 Protection.......................... 1413 47.10 Serial Programming Mode ....................1413 47.10.1 SCI Boot Mode ......................
Page 51 48.6 Operation Stop Procedure ....................1435 48.7 Supplying LCD Drive Voltages VL1, VL2, VL3, and VL4..........1435 48.7.1 External Resistance Division Method ............... 1435 48.7.2 Internal Voltage Boosting Method ................1437 48.7.3 Capacitor Split Method ..................... 1438 48.8 Common and Segment Signals ..................1439 48.9 Display Modes ........................
Page 52 51.3.5 NMI and IRQ Noise Filter ..................1507 51.3.6 Bus Timing........................ 1508 51.3.7 I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing ......1515 51.3.8 CAC Timing ......................1516 51.3.9 SCI Timing........................ 1517 51.3.10 SPI Timing ........................ 1523 51.3.11 QSPI Timing ......................
Page 53 S3A3 Microcontroller Group User’s Manual ® ® High efficiency 48-MHz Arm Cortex -M4 core, 512-KB code flash memory, 96-KB SRAM, Segment LCD Controller, Capacitive Touch Sensing Unit, USB 2.0 Full-Speed, 14-Bit A/D Converter, 12-Bit D/A Converter, security and safety features. Features Features ■...
Page 54 The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. ® The MCU in this series incorporates a low-power and high-performance Arm Cortex...
Page 55 S3A3 User’s Manual 1. Overview Table 1.3 System (1 of 2) Feature Functional description Operating modes Two operating modes:  Single-chip mode  SCI/USB boot mode. section 3, Operating Modes. Resets 14 resets:  RES pin reset  Power-on reset ...
Page 56 S3A3 User’s Manual 1. Overview Table 1.3 System (2 of 2) Feature Functional description Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT.
Page 57 S3A3 User’s Manual 1. Overview Table 1.7 Timers Feature Functional description General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 4 channels and a 16-bit timer with 6 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter.
Page 58 S3A3 User’s Manual 1. Overview Table 1.8 Communication interfaces (2 of 2) Feature Functional description USB 2.0 Full-Speed (USBFS) module The USB 2.0 Full-Speed (USBFS) module can operate as a host controller or device controller. The module supports full-speed and low-speed (only for the host controller) transfer as defined in the Universal Serial Bus Specification 2.0.
Page 59 S3A3 User’s Manual 1. Overview Table 1.10 Human machine interfaces Feature Functional description Segment LCD Controller (SLCDC) The SLCDC provides the following functions:  Waveform A or B selectable  The LCD driver voltage generator can switch between an internal voltage boosting method, a capacitor split method, and an external resistance division method ...
Page 60 S3A3 User’s Manual 1. Overview Block Diagram Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group may have a subset of the features. Memory Arm Cortex-M4 System Clocks 512 KB code flash POR/LVD External MOSC/SOSC 8 KB data flash...
Page 61 Code flash memory size A: 512 KB Feature set 7: Superset Group name A3: S3A3 Group, Arm Cortex-M4, 48 MHz Series name 3: High efficiency Renesas Synergy family Flash memory Renesas microcontroller Renesas Figure 1.2 Part numbering scheme Table 1.13 Product list...
Page 62 S3A3 User’s Manual 1. Overview Function Comparison Table 1.14 Function comparison R7FS3A37A3A01CFM Part numbers R7FS3A37A2A01CLK R7FS3A37A3A01CFB R7FS3A37A2A01CBJ R7FS3A37A3A01CFP R7FS3A37A2A01CLJ R7FS3A37A3A01CNB Pin count Package LQFP LQFP LQFP/QFN Code flash memory 512 KB Data flash memory 8 KB SRAM 96 KB Parity 80 KB 16 KB 48 MHz...
Page 63 S3A3 User’s Manual 1. Overview Pin Functions Function Signal Description Power supply Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-μF capacitor. The capacitor should be placed close to the pin.
Page 64 S3A3 User’s Manual 1. Overview Function Signal Description GTETRGA, Input External trigger input pin GTETRGB GTIOC0A to Input capture, Output capture, or PWM output pin GTIOC9A, GTIOC0B to GTIOC9B GTIU Input Hall sensor input pin U GTIV Input Hall sensor input pin V GTIW Input Hall sensor input pin W...
Page 65 S3A3 User’s Manual 1. Overview Function Signal Description QSPI QSPCLK Output QSPI clock output pin QSSL Output QSPI slave output pin QIO0 Master transmit data/data 0 QIO1 Master input data/data 1 QIO2, QIO3 Data 2, Data 3 CRX0 Input Receive data CTX0 Output Transmit data...
Page 66 S3A3 User’s Manual 1. Overview Function Signal Description I/O ports P000 to P015 General-purpose input/output pins P100 to P115 General-purpose input/output pins P200 Input General-purpose input pin P201 to P206, General-purpose input/output pins P212, P213 P214, P215 Input General-purpose input pins P300 to P315 General-purpose input/output pins P400 to P415...
Page 67 S3A3 User’s Manual 1. Overview Pin Assignments Figure 1.3 Figure 1.9 show the pin assignments. R7FS3A37A2A01CLK P212 P215 P407 P409 P412 P708 P711 P702 P405 P402 P400 /EXTAL /XCIN P915/ P914/ P213 P214 P410 P414 P710 VBATT P701 P404 P511 USB_DM USB_DP /XTAL...
Page 68 S3A3 User’s Manual 1. Overview P800 P300/TCK/SWCLK P801 P301 P802 P302 P803 P303 P809 P500 P808 P501 P304 P502 P305 P503 P504 P306 P505 P307 P308 P506 P309 P507 P310 P311 P312 P015 P014 P200 P201/MD P013/VREFL R7FS3A37A3A01CFB P012/VREFH AVCC0 AVSS0 P902 P011/VREFL0...
Page 69 S3A3 User’s Manual 1. Overview R7FS3A37A2A01CBJ P212/ P215/ P407 P408 P411 P414 P406 P403 P401 P400 EXTAL XCIN P915/ P914/ P213/ P214/ P410 P415 VBATT P405 P402 P511 P512 USB_DM USB_DP XTAL XCOUT VCC_ VSS_ P409 P412 P708 P404 P002 P001 P000 VCC_...
Page 70 S3A3 User’s Manual 1. Overview P500 P300/TCK/SWCLK P301 P501 P502 P302 P503 P303 P504 P809 P505 P808 P304 P305 P015 P306 P014 P307 P013/VREFL P200 P012/VREFH P201/MD R7FS3A37A3A01CFP AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P202 P008 P203 P007 P204 P006 P205 P005 P206 P004 VCC_USB_LDO...
Page 71 S3A3 User’s Manual 1. Overview R7FS3A37A2A01CLJ P212/ P215/ P407 P409 P412 P403 P400 P000 EXTAL XCIN P915/ P914/ P213/ P214/ P413 VBATT P405 P401 P001 USB_DM USB_DP XTAL XCOUT VCC_ VSS_ VCC_US P411 P415 P708 P404 P003 P004 P002 B_LDO P205 P204 P206...
Page 72 S3A3 User’s Manual 1. Overview P500 P300/TCK/SWCLK P501 P301 P502 P302 P015 P303 P014 P304 P013/VREFL P200 P012/VREFH P201/MD AVCC0 R7FS3A37A3A01CFM AVSS0 P204 P011/VREFL0 P205 P010/VREFH0 P206 P004 VCC_USB_LDO P003 VCC_USB P002 P914/USB_DP P001 P915/USB_DM P000 VSS_USB Figure 1.8 Pin assignment for LQFP 64-pin (top view) R01UM0006EU0110 Rev.1.10 Page 72 of 1618 Jul 3, 2018...
Page 73 S3A3 User’s Manual 1. Overview P500 P300/TCK/SWCLK P501 P301 P502 P302 P015 P303 P014 P304 P013/VREFL P200 P012/VREFH P201/MD R7FS3A37A3A01CNB AVCC0 AVSS0 P204 P011/VREFL0 P205 P010/VREFH0 P206 P004 VCC_USB_LDO P003 VCC_USB P002 P914/USB_DP P001 P915/USB_DM P000 VSS_USB Figure 1.9 Pin assignment for QFN 64-pin (top view) R01UM0006EU0110 Rev.1.10 Page 73 of 1618 Jul 3, 2018...
Page 74 S3A3 User’s Manual 1. Overview Pin Lists Pin number Timers Communication interfaces Analogs CACR IRQ0 P400 AGTIO GTIOC SCK1 SCL0 AUDIO SEG4 TS20 SCK4 _CLK IRQ5 P401 GTET GTIOC CTX0 TXD1/ SDA0 SEG5 TS19 MOSI1 /SDA1 CTS4_ RTS4/ VBAT IRQ4 P402 AGTIO RTCIC...
Page 75 S3A3 User’s Manual 1. Overview Pin number Timers Communication interfaces Analogs IRQ4 P411 AGTO GTOV GTIOC TXD0/ MOSIA SD0D SEG7 TS7 MOSI0 /SDA0 CTS3_ RTS3/ IRQ5 P410 AGTO GTOV GTIOC SCK3 MISOA SD0D SEG8 TS6 RXD0/ MISO0 /SCL0 IRQ6 P409 GTOW GTIOC USB_E...
Page 76 S3A3 User’s Manual 1. Overview Pin number Timers Communication interfaces Analogs P200 P312 AGTO CTS3_ RTS3/ P311 AGTO SCK3 P310 AGTE TXD3/ QIO3 MOSI3 /SDA3 P309 RXD3/ QIO2 MISO3 /SCL3 P308 QIO1 SEG13 P307 QIO0 SEG14 P306 QSSL SEG15 IRQ8 P305 QSPC SD0C...
Page 77 S3A3 User’s Manual 1. Overview Pin number Timers Communication interfaces Analogs P610 GTIOC SD0D SEG30 P611 SEG31 P612 SEG32 P613 SEG33 P614 SEG34 P606 RTCO SEG35 P605 GTIOC SEG36 P604 GTIOC SEG37 P603 GTIOC CTS9_ SD0D SEG38 RTS9/ P602 EBCLK GTIOC TXD9/ SD0D...
Page 78 S3A3 User’s Manual 1. Overview Pin number Timers Communication interfaces Analogs P503 GTET USB_E CTS2_ QIO1 AN023 CMPIN SEG51 XICEN RTS2/ SCK3 P504 GTET USB_I SCK2 QIO2 AN024 CTS3_ RTS3/ IRQ14 P505 RXD2/ QIO3 AN025 MISO2 /SCL2 IRQ15 P506 TXD2/ AN026 MOSI2 /SDA2...
Page 79 S3A3 User’s Manual 2. CPU ® ® The MCU is based on the Arm Cortex -M4 core. Overview 2.1.1  Arm Cortex-M4  Revision: r0p1-01rel0  Armv7E-M architecture profile  Single Precision Floating-Point Unit compliant with the ANSI/IEEE Std 754-2008. ...
Page 80 S3A3 User’s Manual 2. CPU  CoreSight Trace Memory Controller with ETB configuration  Buffer size: 1 KB. reference 1. for details. 2.1.3 Operating Frequency The operating frequencies for the MCU are as follows:  CPU: maximum 48 MHz  Serial Write Output (SWO) trace interface: maximum 12.5 MHz ...
Page 81 S3A3 User’s Manual 2. CPU MCU Implementation Options Table 2.1 shows the implementation options of the MCU and is based on the configurable options in reference 2. Table 2.1 Implementation options Option Description Included, 8 protect regions Flash Patch (remap) function is unavailable, only breakpoint function is available. Included Included Included...
Page 82 S3A3 User’s Manual 2. CPU JTAG/SWD Interface Table 2.3 shows the JTAG/SWD pins. Table 2.3 JTAG/SWD pins Name Width Function When not in use TCK/SWCLK Input Pos. 1 bit JTAG clock pin Pull-up SWD clock pin TMS/SWDIO Neg. 1 bit JTAG TMS pin Pull-up SWD I/O pin...
Page 83 S3A3 User’s Manual 2. CPU Table 2.5 Reset or interrupt and mode setting (2 of 2) Control in On-Chip Debug (OCD) mode Reset or Interrupt name OCD break mode OCD run mode Watchdog timer reset/interrupt Does not occur* Depends on DBGSTOPCR setting* Voltage monitor 0 reset Depends on DBGSTOPCR setting* Voltage monitor 1 reset/interrupt...
Page 84 S3A3 User’s Manual 2. CPU Table 2.6 Cortex-M4 peripheral address map Component name Start address End address Note E000 0000h E000 0FFFh reference 2. E000 1000h E000 1FFFh reference 2. E000 2000h E000 2FFFh reference 2. E000 E000h E000 EFFFh reference 2.
Page 85 S3A3 User’s Manual 2. CPU Table 2.8 CoreSight component registers in the CoreSight ROM Table (2 of 2) Name Address Access size Initial value PID7 E00F FFDCh 32 bits 0000 0000h PID0 E00F FFE0h 32 bits 0000 0013h PID1 E00F FFE4h 32 bits 0000 0030h PID2...
Page 86 S3A3 User’s Manual 2. CPU 2.6.4.2 Debug Stop Control Register (DBGSTOPCR) Address(es): DBG.DBGSTOPCR 4001 B010h DBGSTO DBGSTO — — — — — — — — — — — DBGSTOP_LVD[2:0] P_RECC P_RPER Value after reset: DBGSTO DBGSTO — — — — —...
Page 87 S3A3 User’s Manual 2. CPU Symbol Bit name Description ENETBFULL Enable bit for halt 0: ETB full does not cause a CPU halt request on ETB full 1: ETB full causes a CPU halt. 2.6.4.4 DBGREG CoreSight component registers The DBGREG module provides the CoreSight component registers defined in the Arm CoreSight architecture. Table 2.10 shows these registers.
Page 88 S3A3 User’s Manual 2. CPU IAUTH0: AID 31-0 bits Value after reset: IAUTH1 8000 0100h Address(es): IAUTH1: AID 63-32 bits Value after reset: IAUTH2 8000 0200h Address(es): IAUTH2: AID 95-64 bits Value after reset: IAUTH3 8000 0300h Address(es): IAUTH3: AID 127-96 bits Value after reset: 2.6.5.2 MCU Status Register...
Page 89 S3A3 User’s Manual 2. CPU 2.6.5.3 MCU Control Register (MCUCTRL) Address(es): MCUCTRL 8000 0410h — — — — — — — — — — — — — — — — Value after reset: EDBGR — — — — — — —...
Page 90 S3A3 User’s Manual 2. CPU CoreSight ATB Funnel There is one CoreSight ATB funnel in the MCU. The funnel has two ATB slaves and one ATB master, and it selects the debug trace source from ETM and ITM to ETB. Figure 2.3 shows the CoreSight ATB connection in the MCU.
Page 91 S3A3 User’s Manual 2. CPU Emulator host PC To: CPU bus To: CPU debug SWJ-DP AHB-AP emulator JTAG/SWD APB-AP OCDREG comparator Option-setting memory IAUTH output Unlock ID Compare result (debug enable) Figure 2.4 Authentication mechanism block diagram An ID comparator is available in the MCU for authentication. The comparator compares the 128-bit IAUTH output from OCDREG and the 128-bit unlock ID code from the option-setting memory.
Page 92 S3A3 User’s Manual 2. CPU Table 2.14 Restrictions by mode (2 of 2) Start OCD emulator Change low power Access AHB-AP and Access APB-AP and Active mode connection mode system bus OCDREG Sleep Software Standby Snooze If system bus access is required in Software Standby or Snooze mode, set the MCUCTRL.DBIRQ bit in OCDREG to wake up the MCU from the low power modes.
Page 93 S3A3 User’s Manual 2. CPU (4) When OSIS[127:126] is 11b OCD authentication is required and the OCD must write the unlock ID code to IAUTH registers 0 to 3 in OCDREG. The connection sequence is the same as when OSIS[127:126] is 10b except for ALeRASE capability. When IATUH0-3 are ALeRASE in ASCII code, the content of code flash, data flash, and the configuration area are erased at once.
Page 94 S3A3 User’s Manual 3. Operating Modes Operating Modes Overview Table 3.1 shows the selection of operating modes by the mode-setting pin. For details, see section 3.2, Details of Operating Modes. Operation starts with the on-chip flash memory enabled, regardless of the mode in which operation started.
Page 95 S3A3 User’s Manual 4. Address Space Address Space Overview The MCU supports a 4-GB linear address space ranging from 0000 0000h to FFFF FFFFh that can contain both program and data. Figure 4.1 shows the memory map. FFFF FFFFh ® System for Cortex E000 0000h Reserved area*...
Page 96 S3A3 User’s Manual 4. Address Space 83FF FFFFh FFFF FFFFh System for Cortex-M4 CS3 (16 Mbytes) E000 0000h 8300 0000h 82FF FFFFh Reserved area* CS2 (16 Mbytes) 8200 0000h 8400 0000h 81FF FFFFh External address space (CS area) 8000 0000h CS1 (16 Mbytes) Reserved area* 6800 0000h...
Page 97 S3A3 User’s Manual 5. Memory Mirror Function (MMF) Memory Mirror Function (MMF) Overview The MCU provides a Memory Mirror Function (MMF). You can configure the MMF to map an application image load address in the code flash memory to the application image link address in the unused 23-bit memory mirror space addresses.
Page 98 S3A3 User’s Manual 5. Memory Mirror Function (MMF) 5.2.2 MemMirror Enable Register (MMEN) Address(es): MMF.MMEN 4000 1004h KEY[7:0] — — — — — — — — Value after reset: — — — — — — — — — — — —...
Page 99 S3A3 User’s Manual 5. Memory Mirror Function (MMF) b24 b23 Address bus Memory mirror space [0200 0000h to 027F FFFFh] MemMirror SFR MEMMIRADDR[15:0] — — — — — — — — — Address bus[22:0] + MEMMIRADDR[22:0] Code flash address 027F FFFFh MEMMIRADDR - 1 0042 237Fh Memory Mirror Space...
Page 100 S3A3 User’s Manual 5. Memory Mirror Function (MMF) Figure 5.3 shows the addresses handled by each module. The Arm MPU uses the original address of the CPU. The ® Security MPU and code flash memory each use an address after conversion through the Memory Mirror Function. Original address of CPU ARM MPU Memory Mirror Function...
Page 101 S3A3 User’s Manual 5. Memory Mirror Function (MMF) Start Set MMSFR.MEMMIRADDR [15:0] (start address of the application in code flash area) Set MMEN.EN = 1 Figure 5.5 MMF setup flow 5.3.2 Setting Example The target application code on the code flash can be accessed from the address of 0200 0000h on the memory mirror space by setting up the code flash start address in MMSFR.MEMMIRADDR and setting MMEN.EN to 1.
Page 102 S3A3 User’s Manual 5. Memory Mirror Function (MMF) 027F FFFFh Memory mirror space 0201 0000h Application code 0200 0000h 003F FFFFh Code Flash You can choose any version of application code with the MMSFR register Application code ver3 0012 0000h Application code ver2 0011 0000h Application code ver1...
Page 103 S3A3 User’s Manual 6. Resets Resets Overview The MCU provides 14 resets:  RES pin reset  Power-on reset  VBATT-selected voltage power-on reset  Independent watchdog timer reset  Watchdog timer reset  Voltage monitor 0 reset  Voltage monitor 1 reset ...
Page 104 S3A3 User’s Manual 6. Resets Table 6.2 Reset detect flags initialized by each reset source Reset source Voltage Independent Voltage Voltage RES pin Power-on monitor 0 watchdog Watchdog monitor 1 monitor 2 Software Flags to be initialized reset reset reset timer reset timer reset reset...
Page 105 S3A3 User’s Manual 6. Resets Table 6.3 Module-related registers initialized by each reset source Reset source Independent Voltage watchdog Watchdog Voltage Voltage RES pin Power-on monitor 0 timer timer monitor 1 monitor 2 Software Registers to be initialized reset reset reset reset reset...
Page 106 S3A3 User’s Manual 6. Resets Reset source SRAM SRAM master Bus slave Stack parity ECC error MPU error MPU error pointer VBATT_ Registers to be initialized error reset reset reset reset error reset POR* × × × × × × Battery backup VBTCR1 ×...
Page 107 S3A3 User’s Manual 6. Resets Register Descriptions 6.2.1 Reset Status Register 0 (RSTSR0) Address(es): SYSTEM.RSTSR0 4001 E410h LVD2R LVD1R LVD0R — — — — PORF Value after reset: x: Undefined Symbol Bit name Description PORF Power-On Reset Detect Flag 0: Power-on reset not detected R(/W) 1: Power-on reset detected.
Page 108 S3A3 User’s Manual 6. Resets LVD2RF flag (Voltage Monitor 2 Reset Detect Flag) The LVD2RF flag indicates that the VCC voltage fell below Vdet2. [Setting condition]  When a voltage monitor 2 reset occurs. [Clearing conditions]  When a reset listed in Table 6.2 occurs ...
Page 109 S3A3 User’s Manual 6. Resets WDTRF flag (Watchdog Timer Reset Detect Flag) The WDTRF flag indicates that a watchdog timer reset occurred. [Setting condition]  When a watchdog timer reset occurs. [Clearing conditions]  When a reset listed in Table 6.2 occurs ...
Page 110 S3A3 User’s Manual 6. Resets  When a bus master MPU error reset occurs. [Clearing conditions]  When a reset listed in Table 6.2 occurs  When 1 is read from and then 0 is written to BUSMRF. SPERF flag (SP Error Reset Detect Flag) The SPERF flag indicates that a stack pointer error reset occurred.
Page 111 S3A3 User’s Manual 6. Resets For details, see section 51, Electrical Characteristics. 6.3.2 Power-On Reset The power-on reset (POR) is an internal reset generated by the power-on reset circuit. If the RES pin is in a high level state when power is supplied, a power-on reset is generated. After VCC exceeds VPOR and the specified power-on reset time elapses, the internal reset is canceled and the CPU starts the reset exception handling.
Page 112 S3A3 User’s Manual 6. Resets 6.3.3 Voltage Monitor Reset The voltage monitor 0 reset is an internal reset generated by the voltage monitor circuit. If the Voltage Detection 0 Circuit Start (LVDAS) bit in Option Function Select register 1 (OFS1) is 0 (voltage monitor 0 reset is enabled after a reset) and VCC falls below Vdet0, the RSTSR0.LVD0RF flag becomes 1 and the voltage detection circuit generates a voltage monitor 0 reset.
Page 113 S3A3 User’s Manual 6. Resets Vdeti* RES pin LVDi valid setting LVCMPCR.LVDiE Voltage detection i signal (active-low) LVDiCR0.RN = 0 RES pin reset RSTSR0.LVDiRF tLVDi* Internal reset signal LVDiCR0.RN = 1 RES pin reset RSTSR0.LVDiRF tLVDi* Internal reset signal Note: For details on the electrical characteristics, see section 51, Electrical Characteristics.
Page 114 S3A3 User’s Manual 6. Resets For details on the SYSRESETREQ bit, see the ARM ® ® Cortex -M4 Technical Reference Manual. 6.3.7 Determination of Cold/Warm Start Read the CWSF flag in RSTSR2 to determine the cause of reset processing. The flag indicates whether a power-on reset caused the reset processing (cold start) or a reset signal input during operation caused the reset processing (warm start).
Page 115 S3A3 User’s Manual 6. Resets Reset exception handling RSTSR1  00h RSTSR0.LVD1RF = 1 RSTSR0.LVD2RF = 1 RSTSR0. LVD0RF = 1 RSTSR0. PORF = 1 Reset corresponding to Voltage Power-on RES pin reset each bit of RSTSR1, monitor 0 reset RSTSR0.LVD1RF, or reset RSTSR0.LVD2RF...
Page 116 S3A3 User’s Manual 7. Option-Setting Memory Option-Setting Memory Overview The option-setting memory determines the state of the MCU after a reset. The option-setting memory is allocated to the configuration setting area and the program flash area of the flash memory, and the available methods of setting are different for the two areas.
Page 117 S3A3 User’s Manual 7. Option-Setting Memory Symbol Bit name Description b7 to b4 IWDTCKS[3:0] IWDT-Dedicated Clock 0 0 0 0: × 1 Frequency Division Ratio 0 0 1 0: × 1/16 Select 0 0 1 1: × 1/32 0 1 0 0: × 1/64 1 1 1 1: ×...
Page 118 S3A3 User’s Manual 7. Option-Setting Memory Note 1. The value in a blank product is FFFF FFFFh. It is set to the value written by your application. IWDTSTRT (IWDT Start Mode Select) The IWDTSTRT bit selects the mode in which the IWDT is activated after a reset (stopped state or activated state). IWDTTOPS[1:0] bits (IWDT Timeout Period...
Page 119 S3A3 User’s Manual 7. Option-Setting Memory For details, see section 26, Watchdog Timer (WDT). WDTCKS[3:0] bits (WDT Clock Frequency Division Ratio Select) The WDTCKS[3:0] bits specify the division ratio of the prescaler to divide the frequency of PCLKB as 1/4, 1/64, 1/128, 1/512, 1/2048, or 1/8192.
Page 120 S3A3 User’s Manual 7. Option-Setting Memory Symbol Bit name Description b5 to b3 VDSEL1[2:0] Voltage Detection 0 Level 0 0 0: Selects 3.84 V Select 0 0 1: Selects 2.82 V 0 1 0: Selects 2.51 V 0 1 1: Selects 1.90 V 1 0 0: Selects 1.70 V.
Page 121 S3A3 User’s Manual 7. Option-Setting Memory Table 7.1 MPU registers (2 of 2) Size Register name Symbol Function Address (byte) Security MPU Program Counter Start SECMPU Specifies the security fetch region of flash or 0000 0410h Address Register 1 PCS1 SRAM Security MPU Program Counter End SECMPU...
Page 122 S3A3 User’s Manual 7. Option-Setting Memory Symbol Bit name Description FSPR Protection of Access Window This bit controls the programming of the write/erase protection for and Startup Area Select the access window, the Startup Area Select Flag (BTFLG), and Function the temporary boot swap control.
Page 123 S3A3 User’s Manual 7. Option-Setting Memory Address Protected area Block 7 (FAWE[11:0] = 007h) Block 6 Access Non-protected Block 5 area window Block 4 (FAWS[11:0] = 004h) Block 3 Block 2 Protected area Block 1 Block 0 Figure 7.2 Access window overview 7.2.6 OCD/Serial Programmer ID Setting Register (OSIS)
Page 124 S3A3 User’s Manual 7. Option-Setting Memory Table 7.2 Specifications for ID code protection Operating mode on boot Operations on connection to programmer or ID code State of protection on-chip debugger Serial programming mode FFh, …, FFh Protection disabled The ID code is not checked, the ID code always (SCI/USB boot mode) (all bytes are FFh) matches, and the connection to the programmer or...
Page 125 S3A3 User’s Manual 7. Option-Setting Memory Usage Note 7.4.1 Data for Programming Reserved Areas and Reserved Bits in the Option-Setting Memory When reserved areas and reserved bits in the option-setting memory are within the scope of programming, write 1 to all bits of reserved areas and all reserved bits.
Page 126 S3A3 User’s Manual 8. Low Voltage Detection (LVD) Low Voltage Detection (LVD) Overview The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin, and the detection level can be selected using a software program. The LVD module consists of three separate voltage level detectors, 0, 1, and 2, which measure the voltage level input to the VCC pin.
Page 127 S3A3 User’s Manual 8. Low Voltage Detection (LVD) OFS1.LVDAS Voltage detection 0 reset signal Level selection  Vdet0 Internal reference voltage circuit (for detecting Vdet0) OFS1.VDSEL1[2:0] LVCMPCR.LVD1E LVD1CR0.CMPE Voltage detection 1 signal Internal reference voltage Level selection  Vdet1 (for detecting Vdet1) circuit LVDLVLR.LVD1LVL[4:0] LVCMPCR.LVD2E...
Page 128 S3A3 User’s Manual 8. Low Voltage Detection (LVD) Voltage monitor 2 The setting of the LVD2SR.DET bit is 0 if 0 (undetected) is written by the program Voltage detection 2 LVD2SR.MON LVCMPCR.LVD2E LVD2CR0.RIE LVD2CR0.CMPE LVD2CR0.RI LVD2CR0.RN = 0 Voltage monitor 2 Fixed Voltage reset signal...
Page 129 S3A3 User’s Manual 8. Low Voltage Detection (LVD) 8.2.2 Voltage Monitor 1 Circuit Status Register (LVD1SR) Address(es): SYSTEM.LVD1SR 4001 E0E1h — — — — — — Value after reset: Symbol Bit name Description Voltage Monitor 1 Voltage Change 0: Not detected R(/W) Detection Flag 1: Vdet1 passage detected.
Page 130 S3A3 User’s Manual 8. Low Voltage Detection (LVD) 8.2.4 Voltage Monitor 2 Circuit Status Register (LVD2SR) Address(es): SYSTEM.LVD2SR 4001 E0E3h — — — — — — Value after reset: Symbol Bit name Description Voltage Monitor 2 Voltage Change 0: Not detected Detection Flag 1: Vdet2 passage detected.
Page 131 S3A3 User’s Manual 8. Low Voltage Detection (LVD) LVD2E (Voltage Detection 2 Enable) When using voltage detection 2 interrupt/reset or the LVD2SR.MON bit, set the LVD2E bit to 1. The voltage detection 2 circuit starts when td(E-A) elapses after the LVD2E bit value is changed from 0 to 1. 8.2.6 Voltage Detection Level Select Register (LVDLVLR)
Page 132 S3A3 User’s Manual 8. Low Voltage Detection (LVD) 8.2.7 Voltage Monitor 1 Circuit Control Register 0 (LVD1CR0) Address(es): SYSTEM.LVD1CR0 4001 E41Ah — — — CMPE — Value after reset: Symbol Bit name Description Voltage Monitor 1 Interrupt/Reset 0: Disable Enable 1: Enable.
Page 133 S3A3 User’s Manual 8. Low Voltage Detection (LVD) Symbol Bit Name Description — Reserved The read value is undefined. The write value should be 1. b5, b4 — Reserved These bits are read as 0. The write value should be 0. Voltage Monitor 2 Circuit Mode 0: Generate voltage monitor 2 interrupt on Vdet2 passage Select...
Page 134 S3A3 User’s Manual 8. Low Voltage Detection (LVD) Reset from Voltage Monitor 0 When using the reset from voltage monitor 0, clear the OFS1.LVDAS bit to 0 to enable the voltage monitor 0 reset after a reset. However, at boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit.
Page 135 S3A3 User’s Manual 8. Low Voltage Detection (LVD) Table 8.4 Procedure for setting bits related to the voltage monitor 1 interrupt and voltage monitor 1 reset so that voltage monitor operates Voltage monitor 1 interrupt Step (voltage monitor 1 ELC event output) Voltage monitor 1 reset Setting the voltage Set LVCMPCR.LVD1E = 0 to disable voltage detection 1 before writing to the LVDLVLR register.
Page 136 S3A3 User’s Manual 8. Low Voltage Detection (LVD) Vdet1 Lower limit on VCC voltage (VCCmin)* LVD1SR.MON Set to 0 by software LVD1SR.DET bit LVD1CR1.IDTSEL[1:0] bits are set to 10b (when drop and rise are detected) Voltage monitor 1 interrupt request Set to 0 by software LVD1SR.DET bit LVD1CR1.IDTSEL[1:0] bits are...
Page 137 S3A3 User’s Manual 8. Low Voltage Detection (LVD) Table 8.6 Procedure for setting bits related to voltage monitor 2 interrupt and voltage monitor 2 reset so that voltage monitor operates (2 of 2) Voltage monitor 2 interrupt Step (voltage monitor 2 ELC event output) Voltage monitor 2 reset ...
Page 138 S3A3 User’s Manual 8. Low Voltage Detection (LVD) Vdet2 Lower limit on VCC voltage (VCCmin)* LVD2SR.MON bit Set to 0 by software LVD2SR.DET bit LVD2CR1.IDTSEL[1:0] bits are set to 10b (when drop and rise are detected) Voltage monitor 2 interrupt request Set to 0 by software LVD2SR.DET bit LVD2CR1.IDTSEL[1:0] bits are...
Page 139 S3A3 User’s Manual 8. Low Voltage Detection (LVD) flags are saved, when the clock supply resumes after returning from Software Standby mode, the event signals for the ELC are output based on the state of the Vdet1 and Vdet2 detection flags. R01UM0006EU0110 Rev.1.10 Page 139 of 1618 Jul 3, 2018...
Page 140 S3A3 User’s Manual 9. Clock Generation Circuit Clock Generation Circuit Overview The MCU provides a clock generation circuit. Table 9.1 Table 9.2 list the clock generation circuit specifications. Figure 9.1 shows a block diagram, and Table 9.3 lists the I/O pins. Table 9.1 Clock generation circuit specifications for the clock sources Clock source...
Page 141 S3A3 User’s Manual 9. Clock Generation Circuit Table 9.2 Clock Generation Circuit Specifications for the internal clocks Parameter Clock source Clock supply Specification System clock (ICLK) MOSC/SOSC/HOCO/MOCO/ CPU, DTC, DMAC, Flash, Up to 48 MHz LOCO/PLL SRAM Division ratios: 1, 2, 4, 8, 16, 32, 64 Peripheral module clock A MOSC/SOSC/HOCO/MOCO/...
Page 142 S3A3 User’s Manual 9. Clock Generation Circuit ICLK:FCLK = N:1, ICLK:BCLK = N: 1, ICLK:PCLKA = N: 1, ICLK:PCLKB = N: 1 ICLK:PCLKC = N:1 or 1:N, ICLK:PCLKD = N:1 or 1:N PCLKB:PCLKC = 1:1 or 1:2 or 1:4 or 2:1 or 4:1 or 8:1 Note: Minimum FCLK frequency is 1 MHz in Programming/Erasure (P/E) mode.
Page 143 S3A3 User’s Manual 9. Clock Generation Circuit Table 9.3 Clock generation circuit input/output pins Pin name Description XTAL Output These pins are used to connect a crystal resonator. The EXTAL pin can also be used to input an external clock. For details, see section 9.3.2, External Clock Input.
Page 144 S3A3 User’s Manual 9. Clock Generation Circuit Symbol Bit name Description b14 to b12 PCKA[2:0] Peripheral Module Clock A 0 0 0: ×1/1 (PCLKA) Select* 0 0 1: ×1/2 0 1 0: ×1/4 0 1 1: ×1/8 1 0 0: ×1/16 1 0 1: ×1/32 1 1 0: ×1/64.
Page 145 S3A3 User’s Manual 9. Clock Generation Circuit PCKB[2:0] bits (Peripheral Module Clock B (PCLKB) Select* The PCKB[2:0] bits select the frequency of peripheral module clock B (PCLKB). PCKA[2:0] bits (Peripheral Module Clock A (PCLKA) Select* The PCKA[2:0] bits select the frequency of peripheral module clock A (PCLKA). BCK[2:0] bits (External Bus Clock (BCLK) Select*...
Page 146 S3A3 User’s Manual 9. Clock Generation Circuit  PLL circuit. Transitions to clock sources that are not in operation are prohibited. 9.2.3 PLL Clock Control Register 2 (PLLCCR2) Address(es): SYSTEM.PLLCCR2 4001 E02Bh PLODIV[1:0] — PLLMUL[4:0] Value after reset: Symbol Bit name Description b4 to b0 PLLMUL[4:0]...
Page 147 S3A3 User’s Manual 9. Clock Generation Circuit The PLLCR register controls the operation of the PLL circuit. PLLSTP (PLL Stop Control) The PLLSTP bit starts or stops the PLL circuit. After setting the PLLSTP bit to 0, confirm that the OSCSF.PLLSF bit is set to 1 before using the PLL clock. A fixed stabilization wait is required after setting the PLL to start operation.
Page 148 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.6 Memory Wait Cycle Control Register (MEMWAIT) Address(es): SYSTEM.MEMWAIT 4001 E031h MEMW — — — — — — — Value after reset: Symbol Bit name Description MEMWAIT Memory Wait Cycle Select 0: No wait 1: Wait.
Page 149 S3A3 User’s Manual 9. Clock Generation Circuit ICLK  32 MHz, MEMWAIT = 0, FCACHEEN = 0 Start Operation mode Set operation mode to = high-speed mode high-speed mode Set MEMWAIT bit to 1 Set ICLK > 32 MHz Write FCACHEIV bit to 1 FCACHEIV = 0 ? (Do not invalidate) Set FCACHEEN bit to 1...
Page 150 S3A3 User’s Manual 9. Clock Generation Circuit ICLK > 32 MHz, MEMWAIT = 1, Start FCACHEEN = 1, High-speed mode FCACHEEN bit to 0 Set ICLK  32 MHz Clear MEMWAIT bit to 0 Change the operation mode from High-speed mode Change the operation mode Figure 9.3 When setting the ICLK ≤...
Page 151 S3A3 User’s Manual 9. Clock Generation Circuit MOSCCR.MOSTP bit setting is modified for the main clock to run, only use the main clock after confirming that the OSCSF.MOSCSF bit is set to 1. A fixed time is required for oscillation to become stable after setting the main clock oscillator. A fixed time is also required for oscillation to stop after stopping the main clock oscillator.
Page 152 S3A3 User’s Manual 9. Clock Generation Circuit  Confirm that the sub-clock oscillator is stable when setting the sub-clock oscillator to stop.  Regardless of whether the sub-clock oscillator is selected as the system clock, ensure that oscillation by the sub- clock oscillator is stable before executing a WFI instruction to place the MCU in Software Standby mode ...
Page 153 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.10 High-Speed On-Chip Oscillator Control Register (HOCOCR) Address(es): SYSTEM.HOCOCR 4001 E036h — — — — — — — HCSTP Value after reset: Symbol Bit name Description HCSTP HOCO Stop 0: Operate the HOCO clock* 1: Stop the HOCO clock.
Page 154 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.11 Middle-Speed On-Chip Oscillator Control Register (MOCOCR) Address(es): SYSTEM.MOCOCR 4001 E038h — — — — — — — MCSTP Value after reset: Symbol Bit name Description MCSTP MOCO Stop 0: Operate MOCO 1: Stop MOCO. b7 to b1 —...
Page 155 S3A3 User’s Manual 9. Clock Generation Circuit Symbol Bit name Description b2, b1 — Reserved These bits are read as 0. MOSCSF Main Clock Oscillation 0: The main clock oscillation is stopped (MOSTP = 1) or Stabilization Flag is not stable yet 1: The main clock oscillator is stable, so is available for use as the system clock.
Page 156 S3A3 User’s Manual 9. Clock Generation Circuit  When the PLL operates, it is deactivated when the PLLCR.PLLSTP bit is set to 1. 9.2.13 Oscillation Stop Detection Control Register (OSTDCR) Address(es): SYSTEM.OSTDCR 4001 E040h OSTDI OSTDE — — — — —...
Page 157 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.14 Oscillation Stop Detection Status Register (OSTDSR) Address(es): SYSTEM.OSTDSR 4001 E041h — — — — — — — OSTDF Value after reset: Symbol Bit name Description OSTDF Oscillation Stop Detection Flag 0: Main clock oscillation stop not detected R(/W) 1: Main clock oscillation stop detected.
Page 158 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.15 Main Clock Oscillator Wait Control Register (MOSCWTCR) Address(es): SYSTEM.MOSCWTCR 4001 E0A2h — — — — MSTS[3:0] Value after reset: Symbol Bit name Description b3 to b0 MSTS[3:0] Main Clock Oscillator Wait 0 0 0 0: Wait time = 2 cycles (0.25 μs) Time Setting 0 0 0 1: Wait time = 1024 cycles (128 μs) 0 0 1 0: Wait time = 2048 cycles (256 μs)
Page 159 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.16 High-Speed On-Chip Oscillator Wait Control Register (HOCOWTCR) Address(es): SYSTEM.HOCOWTCR 4001 E0A5h — — — — — HSTS[2:0] Value after reset: Symbol Bit name Description b2 to b0 HSTS[2:0] HOCO wait time setting 1 0 1: ...
Page 160 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.17 Main Clock Oscillator Mode Oscillation Control Register (MOMCR) Address(es): SYSTEM.MOMCR 4001 E413h MODR — MOSEL — — — — — Value after reset: Symbol Bit name Description b2 to b0 — Reserved These bits are read as 0.
Page 161 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.19 Segment LCD Source Clock Control Register (SLCDSCKCR) Address(es): SYSTEM.SLCDSCKCR 4001 E050h LCDSC — — — — LCDSCKSEL[2:0] Value after reset: Symbol Bit name Description b2 to b0 LCDSCKSEL[2:0] LCD Source Clock 0 0 0: LOCO (LCDSRCCLK) Select 0 0 1: SOSC 0 1 0: MOSC...
Page 162 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.20 Clock Out Control Register (CKOCR) Address(es): SYSTEM.CKOCR 4001 E03Eh CKOEN CKODIV[2:0] — CKOSEL[2:0] Value after reset: Symbol Bit name Description b2 to b0 CKOSEL[2:0] Clock Out Source Select 0 0 0: HOCO 0 0 1: MOCO 0 1 0: LOCO 0 1 1: MOSC...
Page 163 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.21 External Bus Clock Output Control Register (EBCKOCR) Address(es): SYSTEM.EBCKOCR 4001 E052h EBCKO — — — — — — — Value after reset: Symbol Bit name Description EBCKOEN EBCLK Pin Output Control 0: EBCLK pin output is disabled (fixed high) 1: EBCLK pin output is enabled.
Page 164 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.23 MOCO User Trimming Control Register (MOCOUTCR) Address(es): SYSTEM.MOCOUTCR 4001 E061h MOCOUTRM[7:0] Value after reset: Symbol Bit name Description b7 to b0 MOCOUTRM[7:0] MOCO User Trimming 1 0 0 0 0 0 0 0: -128 1 0 0 0 0 0 0 1: -127 1 0 0 0 0 0 1 0: -126 …...
Page 165 S3A3 User’s Manual 9. Clock Generation Circuit 9.2.25 Trace Clock Control Register (TRCKCR) Address(es): SYSTEM.TRCKCR 4001 E03Fh TRCKE — — — TRCK[3:0] Value after reset: Symbol Bit name Description b3 to b0 TRCK[3:0] Trace Clock operation frequency 0 0 0 0: /1 select 0 0 0 1: /2 (value after reset) 0 0 1 0: /4.
Page 166 S3A3 User’s Manual 9. Clock Generation Circuit 9.3.1 Connecting a Crystal Resonator Figure 9.4 shows an example of connecting a crystal resonator. A damping resistor (Rd) can be added, if required. Because the resistor values vary according to the resonator and the oscillation drive capability, use values recommended by the resonator manufacturer.
Page 167 S3A3 User’s Manual 9. Clock Generation Circuit XCIN XCOUT Figure 9.6 Connection example of 32.768-kHz crystal resonator Oscillation Stop Detection Function 9.5.1 Oscillation Stop Detection and Operation after Detection The oscillation stop detection function is used to detect the main clock oscillator stop. When oscillation stop is detected, the system clock switches as follows: ...
Page 168 S3A3 User’s Manual 9. Clock Generation Circuit system clock is PLL) operation is specified in the MOCO oscillation frequency and the division ratio set in the System Clock Select bits (SCKDIVCR.ICK[2:0]). Example of returning when CKSEL[2:0] = 011b (selecting the main clock oscillator) after an oscillation stop is detected.
Page 169 S3A3 User’s Manual 9. Clock Generation Circuit OSTDCR.OSTDIE bit to 1 again. A longer PCLKB wait time might be required, depending on the number of cycles required to read a given I/O register. The oscillation stop detection interrupt is a non-maskable interrupt. Because non-maskable interrupts are disabled in the initial state after a reset release, enable the non-maskable interrupts through software before using the oscillation stop detection interrupts.
Page 170 S3A3 User’s Manual 9. Clock Generation Circuit The ICLK frequency is specified by the ICK[2:0] bits in SCKDIVCR, the CKSEL[2:0] bits in SCKSCR, the PLLMUL[4:0] and PLODIV[1:0] bits in PLLCCR2, and the HOCOFRQ1[2:0] bits in OFS1. 9.7.2 Peripheral Module Clock (PCLKA, PCLKB, PCLKC, PCLKD) The peripheral module clocks, PCLKA, PCLKB, PCLKC, and PCLKD, are the operating clocks for the peripheral modules.
Page 171 S3A3 User’s Manual 9. Clock Generation Circuit oscillator. 9.7.7 CAC Clock (CACCLK) The CAC clock, CACCLK, is the operating clock for the CAC. CACCLK is generated by the following:  Main clock oscillator  Sub-clock oscillator  High-speed clock oscillator ...
Page 172 S3A3 User’s Manual 9. Clock Generation Circuit JTAGTCK is generated by the external clock for JTAG (TCK). Usage Notes 9.8.1 Notes on Clock Generation Circuit The frequencies of the system clock (ICLK), peripheral module clock (PCLKA to PCLKD), flash interface clock (FCLK), and the external bus clock (BCLK) supplied to each module change according to the settings of SCKDIVCR.
Page 173 S3A3 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) Clock Frequency Accuracy Measurement Circuit (CAC) 10.1 Overview The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock to be used as a measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range.
Page 174 S3A3 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) DFS[1:0] CACREFE DFS[1:0] CACREF pin Digital filter RSCS[2:0] RCDS[1:0] EDGES[1:0] 1/32 Reference 1/128 Edge detection signal circuit generation 1/1024 clock select 1/8192 Valid edge signal circuit FMCS[2:0] TCSS[1:0] Frequency measurement clock Main clock CFME...
Page 175 S3A3 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.2 CAC Control Register 1 (CACR1) Address(es): CAC.CACR1 4004 4601h CACRE EDGES[1:0] TCSS[1:0] FMCS[2:0] Value after reset: Symbol Bit name Description CACREFE CACREF Pin Input Enable 0: Disable 1: Enable. b3 to b1 FMCS[2:0] Measurement Target Clock Select...
Page 176 S3A3 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.3 CAC Control Register 2 (CACR2) Address(es): CAC.CACR2 4004 4602h DFS[1:0] RCDS[1:0] RSCS[2:0] Value after reset: Symbol Bit name Description Reference Signal Select 0: CACREF pin input 1: Internal clock (internally generated signal). b3 to b1 RSCS[2:0] Measurement Reference Clock...
Page 177 S3A3 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.4 CAC Interrupt Control Register (CAICR) Address(es): CAC.CAICR 4004 4603h OVFFC MENDF FERRF OVFIE MENDI FERRI — — Value after reset: Symbol Bit name Description FERRIE Frequency Error Interrupt Request 0: Disable frequency error interrupt request Enable 1: Enable frequency error interrupt request.
Page 178 S3A3 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.5 CAC Status Register (CASTR) Address(es): CAC.CASTR 4004 4604h — — — — — OVFF MENDF FERRF Value after reset: Symbol Bit name Description FERRF Frequency Error Flag 0: Clock frequency is within the allowable range 1: Clock frequency has deviated beyond the allowable range (frequency error).
Page 179 S3A3 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.6 CAC Upper-Limit Value Setting Register (CAULVR) Address(es): CAC.CAULVR 4004 4606h Value after reset: CAULVR is a 16-bit read/write register that specifies the upper value of the allowable range. When the counter value rises above the value specified in this register, a frequency error is detected.
Page 180 S3A3 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) CACREF pin or internal clock CFME bit in CACR0 0 is written to 1 is written to Counter value CFME bit. CFME bit. FFFFh Counter is After 1 is written to CFME bit, counting cleared by writing starts at the first valid edge.
Page 181 S3A3 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) selectable. The counter value transferred in CACNTBR might be in error by up to 1 cycle of the sampling clock because of the difference between the phases of the digital filter and the signal input to the CACREF pin. When a frequency dividing clock is selected as a count source clock, the counter value error is obtained using the following formula: Counter value error = (1 cycle of the count source clock) / (1 cycle of the sampling clock) 10.4...
Page 182 S3A3 User’s Manual 11. Low Power Modes Low Power Modes 11.1 Overview The MCU provides several functions for reducing power consumption, such as setting clock dividers, controlling EBCLK output, stopping modules, selecting power control mode in normal mode, and transitioning to low power modes. Table 11.1 lists the specifications of the low power mode functions.
Page 183 S3A3 User’s Manual 11. Low Power Modes Table 11.2 Operating conditions of each low power mode (2 of 2) Parameter Sleep mode Software Standby mode Snooze mode* Flash memory Operating Stop (Retained) Stop (Retained) DMA Controller (DMAC) Selectable Stop (Retained) Operation prohibited Data Transfer Controller (DTC) Selectable...
Page 184 S3A3 User’s Manual 11. Low Power Modes Table 11.3 Interrupt sources to transition to Normal mode from Snooze mode and Software Standby mode Interrupt source Name Software Standby mode Snooze mode VBATT VBATT_LVD Port PORT_IRQn (n = 0 to 15) LVD_LVD1 LVD_LVD2 IWDT...
Page 185 S3A3 User’s Manual 11. Low Power Modes SBYCR.SSBY = 0 Reset state Sleep mode WFI instruction RES pin = High SNZCR.SNZE = 1 All interrupts Snooze mode Interrupt shown in Table 11.3 Snooze end condition Snooze requests Normal mode shown in Table 11.8 shown in Table 11.6...
Page 186 S3A3 User’s Manual 11. Low Power Modes When the SSBY bit is set to 1, the MCU enters Software Standby mode after execution of a WFI instruction. When the MCU returns to Normal mode from Software Standby mode due to an interrupt, the SSBY bit remains 1. The SSBY bit can be cleared by writing 0 to it.
Page 187 S3A3 User’s Manual 11. Low Power Modes Symbol Bit name Description MSTPB2 Controller Area Network Target module: CAN0 Module Stop* 0: Cancel the module-stop state 1: Enter the module-stop state. b5 to b3 — Reserved These bits are read as 1. The write value should be 1. MSTPB6 Quad Serial Peripheral Target Module: QSPI...
Page 188 S3A3 User’s Manual 11. Low Power Modes 11.2.4 Module Stop Control Register C (MSTPCRC) Address(es): MSTP.MSTPCRC 4004 7004h MSTPC — — — — — — — — — — — — — — — Value after reset: MSTPC MSTPC MSTPC MSTPC MSTPC MSTPC...
Page 189 S3A3 User’s Manual 11. Low Power Modes 11.2.5 Module Stop Control Register D (MSTPCRD) Address(es): MSTP.MSTPCRD 4004 7008h MSTPD MSTPD MSTPD MSTPD MSTPD — — — — — — — — — — — Value after reset: MSTPD MSTPD MSTPD MSTPD MSTPD —...
Page 190 S3A3 User’s Manual 11. Low Power Modes 11.2.6 Operating Power Control Register (OPCCR) Address(es): SYSTEM.OPCCR 4001 E0A0h OPCM — — — — — OPCM[1:0] Value after reset: Symbol Bit name Description b1, b0 OPCM[1:0] Operating Power Control b1 b0 0 0: High-speed mode Mode Select 0 1: Middle-speed mode 1 0: Low-voltage mode*...
Page 191 S3A3 User’s Manual 11. Low Power Modes Symbol Bit name Description b7 to b5 — Reserved These bits are read as 0. The write value should be 0. The SOPCCR register is used to reduce power consumption in Normal mode, Sleep mode, and Snooze mode. Setting this register initiates the entry to and exit from Subosc-speed mode.
Page 192 S3A3 User’s Manual 11. Low Power Modes RXDREQEN (RXD0 Snooze Request Enable) The RXDREQEN bit specifies whether to detect a falling edge of the RXD0 pin in Software Standby mode. This bit is only available when SCI0 operates in asynchronous mode. To detect a falling edge of the RXD0 pin, set this bit before entering Software Standby mode.
Page 193 S3A3 User’s Manual 11. Low Power Modes section 18, Data Transfer Controller (DTC). DTCNZRED (Not Last DTC Transmission Completion Snooze End Enable) The DTCNZRED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by completion of each DTC transmission, that is, CRA or CRB registers in the DTC is not 0. For details of the condition of the trigger, see section 18, Data Transfer Controller (DTC).
Page 194 S3A3 User’s Manual 11. Low Power Modes Symbol Bit name Description SNZREQEN6 Snooze Request Enable 6 Enable IRQ6 pin snooze request: 0: Disable the snooze request 1: Enable the snooze request. SNZREQEN7 Snooze Request Enable 7 Enable IRQ7 pin snooze request: 0: Disable the snooze request 1: Enable the snooze request.
Page 195 S3A3 User’s Manual 11. Low Power Modes 14, Interrupt Controller Unit (ICU), the MCU enters Normal mode when the trigger is generated while the associated bit of the SNZREQCR register is 1. The setting of the WUPEN register always has a higher priority than the SNZREQCR register settings.
Page 196 S3A3 User’s Manual 11. Low Power Modes Symbol Bit name Description b7 to b2 — Reserved These bits are read as 0. The write value should be 0. PSMC[1:0] bits (Power Save Memory Control) The SRAM retention area in Software Standby mode is selected with the PSMC[1:0] bits. Supply current can be reduced by setting these bits to 01b (48-KB SRAM in Software Standby mode).
Page 197 S3A3 User’s Manual 11. Low Power Modes 11.5 Function for Lower Operating Power Consumption By selecting an appropriate operating power consumption control mode according to the operating frequency and operating voltage, power consumption can be reduced in Normal mode, Sleep mode, and Snooze mode. 11.5.1 Setting Operating Power Control Mode Make sure that the operating condition such as the voltage range and the frequency range is always within the specified...
Page 198 S3A3 User’s Manual 11. Low Power Modes 4. Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed). 5. Set the SOPCCR.SOPCM bit to 1 (Subosc-speed mode). 6. Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed). 7. Perform the following steps when the flash cache is cacheable in Subosc-speed mode. a.
Page 199 S3A3 User’s Manual 11. Low Power Modes range is 2.4 to 5.5 V during flash read. However, for ICLK and FCLK, the maximum operating frequency during flash read is 16 MHz when the operating voltage is 2.4 V or larger and smaller than 2.7 V. During flash programming and erasure, the operating frequency range is 1 to 48 MHz and the operating voltage range is 2.7 to 5.5 V.
Page 200 S3A3 User’s Manual 11. Low Power Modes The maximum operating frequency during flash read is 4 MHz for ICLK and FCLK. The operating voltage range is 1.6 to 5.5 V during flash read. During flash programming and erasure, the operating frequency range is 1 to 4 MHz and the operating voltage range is 1.8 to 5.5 V.
Page 201 S3A3 User’s Manual 11. Low Power Modes except P/E is prohibited ICLK, FCLK ICLK, FCLK [MHz] [MHz] Figure 11.6 Operating voltages and frequencies in Subosc-speed mode 11.6 Sleep Mode 11.6.1 Transition to Sleep Mode When a WFI instruction is executed while SBYCR.SSBY bit is 0, the MCU enters Sleep mode. In this mode, the CPU stops operating but the contents of its internal registers are retained.
Page 202 S3A3 User’s Manual 11. Low Power Modes The operations are as follows: 1. Canceling by an interrupt When an available interrupt request is generated, Sleep mode is canceled and the MCU starts the interrupt handling. 2. Canceling by RES pin reset When RES pin is driven low, the MCU enters the reset state.
Page 203 S3A3 User’s Manual 11. Low Power Modes 11.7.2 Canceling Software Standby Mode Software Standby mode is canceled by:  An available interrupt shown in Table 11.3  RES pin reset  A power-on reset  A voltage monitor reset  A reset caused by an IWDT underflow. On exiting Software Standby mode, the oscillators that operate before the transition to the mode restart.
Page 204 S3A3 User’s Manual 11. Low Power Modes Oscillator ICLK IRQn pin IRQMD[1:0] SBYCR.SSBY IRQ exception handling IRQ exception handling Software Standby mode IRQMD[1:0] = 10b SBYCR.SSBY = 1 Oscillation WFI instruction settling time Figure 11.7 Example of Software Standby mode application R01UM0006EU0110 Rev.1.10 Page 204 of 1618 Jul 3, 2018...
Page 205 S3A3 User’s Manual 11. Low Power Modes 11.8 Snooze Mode 11.8.1 Transition to Snooze Mode Figure 11.8 shows snooze mode entry configuration. When the snooze control circuit receives a Snooze request in Software Standby mode, the MCU transitions to Snooze mode. In this mode, some peripheral modules operate without waking up the CPU.
Page 206 S3A3 User’s Manual 11. Low Power Modes Trigger Interrupt instruction detection request High Standby cancel signal Snooze end signal Software Normal Standby Low power mode mode mode Snooze mode Normal mode Oscillation Oscillator Oscillates stopped Oscillates for system clock Wait for oscillation accuracy stabilization Note 1.
Page 207 S3A3 User’s Manual 11. Low Power Modes Table 11.8 Snooze end conditions Snooze end request Operating module when a snooze end request occurs AGT1 underflow Other than AGT1 underflow The MCU transitions to Software Standby mode The MCU transitions to Software Standby mode after all of the modules listed to the left of this after all of the modules complete operation ADC140...
Page 208 S3A3 User’s Manual 11. Low Power Modes 11.8.4 Snooze Operation Example Figure 11.11 shows an example setting for using ELC in Snooze mode. Start Snooze mode setting Setting for ELC in Snooze mode MSTPCRC.MSTPC14 = 0 Cancel ELC module-stop state Snooze entry (SYSTEM_SNZREQ) ELSRx.ELS = 01Dh signal is linked to modules...
Page 209 S3A3 User’s Manual 11. Low Power Modes The MCU is capable of data transmission/reception in SCI0 asynchronous mode without CPU intervention. Table 11.9 Table 11.10 show the maximum transfer rate of the SCI0 in Snooze mode. When using the SCI0 in Snooze mode, use one of the following operating modes: ...
Page 210 S3A3 User’s Manual 11. Low Power Modes Figure 11.12 shows an example setting for using the SCI0 in Snooze mode entry. Start Snooze mode setting Setting for SCI0 in Snooze mode MSTPCRB.MSTPB31 = 0 Cancel SCI0 module-stop state Set SCI0 Set as asynchronous UART receive mode SCKSCR.CKSEL = 0h The clock source must be HOCO...
Page 211 S3A3 User’s Manual 11. Low Power Modes 11.9 Usage Notes 11.9.1 Register Access (1) Do not write to registers listed in this section in any of the following conditions: [Registers]  All registers with a peripheral name of SYSTEM. [Conditions] ...
Page 212 S3A3 User’s Manual 11. Low Power Modes  SCKSCR, OPCCR. [Condition]  SOPCCR.SOPCM = 1 (Subosc-speed mode). (4) Do not write to registers listed in this section by DTC or DMAC: [Registers]  MSTPCRA, MSTPCRB, MSTPCRC, MSTPCRD. (5) Do not write to registers listed in this section in Snooze mode. They must be set before entering Software Standby mode: [Registers] ...
Page 213 S3A3 User’s Manual 11. Low Power Modes 11.9.6 Timing of WFI Instruction It is possible for the WFI instruction to be executed before I/O register and CS area writes are complete, in which case operation might not proceed as intended. This can happen if the WFI is placed immediately after a write to an I/O register and CS area.
Page 214 S3A3 User’s Manual 11. Low Power Modes  ADC140 window A/B compare mismatch (ADC140_WCMPUM)  Data operation circuit interrupt (DOC_DOPCI). 11.9.14 Module-Stop Function for ADC140 When entering Software Standby mode, it is recommended that you set the ADC140 module-stop state to reduce power consumption.
Page 215 S3A3 User’s Manual 12. Battery Backup Function Battery Backup Function 12.1 Overview The MCU provides a battery backup function that maintains partial battery powering in the event of a power loss. Switching between VCC and VBATT, the battery-powered area includes RTC, SOSC, LOCO, Wakeup Control/Backup Memory, VBATT_R Low Voltage Detection, and VBATT Low Voltage Detection.
Page 216 S3A3 User’s Manual 12. Battery Backup Function periodic signal, or VBATWIOn (n = 0 to 2) input signal is asserted when VBATT_R is powered by the VBATT pin. Note: The toggle triggered by the wakeup control function does not generate an interrupt at the ICU or a reset to the reset module.
Page 217 S3A3 User’s Manual 12. Battery Backup Function Switch control Internal reference voltage DETBATT VBATT_R VBATT Voltage regulator for backup power Internal reference Internal reference area voltage voltage DETBATLVD VBATPOR VBATT_POR VBATT reset detect flag Interrupt VBATT backup (VBATT_LVD) register VBATT battery low Non-maskable detect flag interrupt...
Page 218 S3A3 User’s Manual 12. Battery Backup Function 12.2 Register Descriptions 12.2.1 VBATT Control Register 1 (VBTCR1) Address(es): SYSTEM.VBTCR1 4001 E41Fh BPWS — — — — — — — WSTP Value after reset: Symbol Bit name Description BPWSWSTP Battery Power Supply Switch Stop 0: Battery power supply switch enable 1: Battery power supply switch stop.
Page 219 S3A3 User’s Manual 12. Battery Backup Function 12.2.2 VBATT Control Register 2 (VBTCR2) Address(es): SYSTEM.VBTCR2 4001 E4B0h VBTLVDLVL[1:0 VBTLV — — — — — Value after reset: Symbol Bit name Description b3 to b0 — Reserved These bits are read as 0. The write value should be 0. VBTLVDEN VBATT Pin Low Voltage Detect 0: VBATT pin low voltage detection disable...
Page 220 S3A3 User’s Manual 12. Battery Backup Function VBTRDF flag (VBATT_R Reset Detect Flag) The VBTRDF flag indicates that a VBATT_R (selected voltage of VCC or VBATT) power-on reset occurs. [Setting condition]  When a VBATT_R voltage power-on reset occurs. [Clearing condition] ...
Page 221 S3A3 User’s Manual 12. Battery Backup Function 12.2.5 VBATT Pin Low Voltage Detect Interrupt Control Register (VBTLVDICR) Address(es): SYSTEM.VBTLVDICR 4001 E4B4h VBTLV VBTLV — — — — — — DISEL Value after reset: Symbol Bit name Description VBTLVDIE VBATT Pin Low Voltage Detect Interrupt 0: VBATT pin low voltage detection interrupt disable Enable 1: VBATT pin low voltage detection interrupt enable.
Page 222 S3A3 User’s Manual 12. Battery Backup Function Set the VWEN bit to 1 only after setting of the following registers is complete. Set VWEN to 0 first before modifying these registers:  VBTWCHnOTSR  VBTICTLR  VBTOCTLR  VBTWTER  VBTWEGR (n = 0 to 2). 12.2.8 VBATT Wakeup I/O 0 Output Trigger Select Register (VBTWCH0OTSR)
Page 223 S3A3 User’s Manual 12. Battery Backup Function CH1VCH0TE VBATWIO1 Output VBATWIO0 0: VBATT wakeup I/O 1 output trigger by the VBATWIO0 Trigger Enable pin is disabled 1: VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is enabled. — Reserved This bit is read as 0.
Page 224 S3A3 User’s Manual 12. Battery Backup Function The VBTWCH2OTSR register is initialized by the VBATT_POR signal. 12.2.11 VBATT Input Control Register (VBTICTLR) Address(es): SYSTEM.VBTICTLR 4001 E4BBh VCH2I VCH1I VCH0I — — — — — Value after reset: Symbol Bit name Description VCH0INEN VBATT Wakeup I/O 0 Input Enable...
Page 225 S3A3 User’s Manual 12. Battery Backup Function VCHnOEN bit (VBATT Wakeup I/O n Output Enable Bit) (n = 0 to 2) The VCHnOEN bit defines the VBATT output enable. Note 1. Only one of these I/O pins can be set as output pin. Therefore, two out of the three bits must set to 0. Note 2.
Page 226 S3A3 User’s Manual 12. Battery Backup Function 12.2.14 VBATT Wakeup Trigger Source Edge Register (VBTWEGR) Address(es): SYSTEM.VBTWEGR 4001 E4BEh VCH2E VCH1E VCH0E — — — — — Value after reset: Symbol Bit name Description VCH0EG VBATWIO0 Wakeup Trigger Source Edge 0: Wakeup trigger is generated at a falling edge Select 1: Wakeup trigger is generated at a rising edge.
Page 227 S3A3 User’s Manual 12. Battery Backup Function The VBTWFR register indicates the triggering factor of the VBATT wakeup control function. This register is protected by the VWEN bit (VBTWCTLR register). VBTWFR is valid 5 PCLKB cycles after writing 1 to VWEN bit enable. Similarly, disabling VBTWFR takes 5 PCLKB cycles after writing 0 to VWEN bit.
Page 228 S3A3 User’s Manual 12. Battery Backup Function To change the system clock from other than SOSC/LOCO to SOSC/LOCO: 1. Change the SCKSCR.CKSEL[2:0] bits. 2. Change the BKRACR.BKRACS[2:0] bits to 000b. To change the system clock from SOSC/LOCO to other than SOSC/LOCO: 1.
Page 229 S3A3 User’s Manual 12. Battery Backup Function Table 12.2 Operating states in VBATT mode (2 of 2) Operating state VBATT mode Flash memory Stopped (retained) Realtime Clock (RTC) Selectable when the selecting clock operates as the count source AGTn (n = 0, 1) Stopped (undefined) Low Voltage Detection (LVD) Stopped...
Page 230 S3A3 User’s Manual 12. Battery Backup Function this bit. Note: You can use the battery backup function after the voltage monitor 0 reset is enabled (OFS1.LVDAS bit is 0). Voltage monitor 0 level should be higher than the VDETBATT level (OFS1.VDSEL1[2:0] bits are 000b, 001b, or 010b).
Page 231 S3A3 User’s Manual 12. Battery Backup Function 1. Make sure that the VBTSR.VBTRVLD bit is 1. 2. Set the VBTLVDICR.VBTLVDIE bit to 0 to disable voltage detect interrupt. 3. Set the VBTCMPCR.VBTCMPE bit to 0 for VBATT pin voltage detect circuit output to disable. 4.
Page 232 S3A3 User’s Manual 12. Battery Backup Function In this example, set the VBTWCH0OTSR.CH0VRTCTE and VBTWCH0OTSR.CH0VCH2TE bits to 1. 8. Set the VBTWCTLR.VWEN bit to 1 to activate the VBATT wakeup control function, then clear the VBTCR1.BPWSWSTP bit to 0 to enable the battery power supply switch. After setting the VBTWCTLR.VWEN bit to 1, the VBATT wakeup control function is enabled.
Page 233 S3A3 User’s Manual 12. Battery Backup Function VBATT Battery Power supply Power P402 VBATWIO0 (output) Wakeup control signal management Power supply stop I/O port powered by VCC pin control signal RTC_PRD Calendar count VBATT RTCIC2 Time capture wakeup control External time capture event P404 VBATWIO2 (input) Time capture pin...
Page 234 S3A3 User’s Manual 12. Battery Backup Function Vdet0 VBATTH DETBATT VBATT VBATPOR P402/VBATWIO0 Clear by I/O port powered by VCC pin software Wakeup (pulled up externally) Set by trigger software RTC periodic wakeup signal (RTC_PRD) Clear by software VBTWFR.VRTCIF Internal reset signal (active-low) LVD0 Note 1.
Page 235 S3A3 User’s Manual 13. Register Write Protection Register Write Protection 13.1 Overview The register write protection function protects important registers from being overwritten because of software errors. The registers to be protected are set with the Protect Register (PRCR). Table 13.1 lists the association between the PRCR bits and the registers to be protected.
Page 236 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Interrupt Controller Unit (ICU) 14.1 Overview The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC, DTC, and DMAC modules. The ICU also controls non-maskable interrupts. Table 14.1 lists the ICU specifications.
Page 237 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Interrupt Controller CPU Stack pointer monitor MPU Bus Master error MPU Bus Slave error SRAM ECC error SRAM Parity error IWDT underflow/refresh error Clock WDT underflow/refresh error Oscillation stop detection interrupt Clock restoration request Generation Voltage monitor 2 interrupt Circuit...
Page 238 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) 14.2.1 IRQ Control Register i (IRQCRi) (i = 0 to 15) Address(es): ICU.IRQCR0 4000 6000h, ICU.IRQCR1 4000 6001h, ICU.IRQCR2 4000 6002h, ICU.IRQCR3 4000 6003h, ICU.IRQCR4 4000 6004h, ICU.IRQCR5 4000 6005h, ICU.IRQCR6 4000 6006h, ICU.IRQCR7 4000 6007h,...
Page 239 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) specified in IRQCRi.FCLKSEL[1:0]. When the sampled level matches three times, the output level from the digital filter changes. For the digital filter details, see section 14.4.3, Digital Filter. 14.2.2 Non-Maskable Interrupt Status Register (NMISR) Address(es): ICU.NMISR 4000 6140h...
Page 240 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) WDTST flag (WDT Underflow/Refresh Error Status Flag) This flag indicates a WDT underflow/refresh error interrupt request. It is read-only and cleared by the NMICLR.WDTCLR bit. [Setting condition]  When a WDT underflow/refresh error interrupt occurs. [Clearing condition] ...
Page 241 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) RPEST flag (SRAM Parity Error Interrupt Status Flag) This flag indicates an SRAM parity error interrupt request. [Setting condition]  When an interrupt occurs in response to an SRAM parity error. [Clearing condition] ...
Page 242 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) 14.2.3 Non-Maskable Interrupt Enable Register (NMIER) Address(es): ICU.NMIER 4000 6120h SPEEN BUSME BUSSE RECCE VBATT LVD2E LVD1E WDTE IWDTE — — — RPEEN NMIEN OSTEN — Value after reset: Symbol Bit name Description IWDTEN IWDT Underflow/Refresh Error Interrupt...
Page 243 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) OSTEN (Oscillation Stop Detection Interrupt Enable) The OSTEN bit enables main oscillation stop detection interrupt as an NMI trigger. NMIEN (NMI Pin Interrupt Enable) The NMIEN bit enables NMI pin interrupt as an NMI trigger. RPEEN (SRAM Parity Error Interrupt Enable)
Page 244 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Symbol Bit name Description SPECLR CPU Stack Pointer Monitor Interrupt 0: No effect. R/(W) Clear 1: Clear the NMISR.SPEST flag. b15 to b13 — Reserved These bits are read as 0. The write value should be 0. Note 1.
Page 245 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Symbol Bit name Description b3 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W b5, b4 NFCLKSEL[1:0] NMI Digital Filter Sampling Clock b5 b4 0 0: PCLKB Select 0 1: PCLKB/8...
Page 246 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Symbol Bit name Description DTCE DTC Activation Enable 0: DTC activation is disabled 1: DTC activation is enabled. b31 to b25 — Reserved These bits are read as 0. The write value should be 0. Note: This register requires halfword or word access.
Page 247 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) 14.2.7 DMAC Event Link Setting Register n (DELSRn) Address(es): ICU.DELSR0 4000 6280h, ICU.DELSR1 4000 6284h, ICU.DELSR2 4000 6288h, ICU.DELSR3 4000 628Ch — — — — — — — — — — — —...
Page 248 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) 14.2.8 SYS Event Link Setting Register (SELSR0) Address(es): ICU.SELSR0 4000 6200h — — — — — — — — SELS[7:0] Value after reset: Symbol Bit name Description b7 to b0 SELS[7:0] SYS Event Link Select 00000000: Disable event output to the associated low-power mode module 00000001 to 11011001: Event signal number to be linked.
Page 249 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Symbol Bit name Description RTCALMWUPEN RTC Alarm Interrupt 0: Disable Software standby returns by RTC alarm Software Standby Returns interrupt Enable 1: Enable Software standby returns by RTC alarm interrupt. RTCPRDWUPEN RTC Period Interrupt 0: Disable Software standby returns by RTC period Software Standby Returns interrupt...
Page 250 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) USBFSWUPEN (USBFS Interrupt Software Standby Returns Enable) The USBFSWUPEN bit enables the use of USBFS interrupt to cancel Software Standby mode. AGT1UDWUPEN (AGT1 Underflow Interrupt Software Standby Returns Enable) The AGT1UDWUPEN bit enables the use of AGT1 underflow interrupt to cancel Software Standby mode. AGT1CAWUPEN (AGT1 Compare Match A Interrupt Software Standby Returns Enable)
Page 251 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.3 Interrupt vector table (2 of 2) Exception number IRQ number Vector offset Source Description 05Ch ICU.IELSR7 Event selected in the ICU.IELSR7 register 060h ICU.IELSR8 Event selected in the ICU.IELSR8 register 064h ICU.IELSR9 Event selected in the ICU.IELSR9 register...
Page 252 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.4 Event table (1 of 6) IELSRn DELSRn Canceling Event Interrupt request Connect to Invoke Canceling Software number source Name NVIC Invoke DTC DMAC Snooze Standby 001h Port PORT_IRQ0   ...
Page 253 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.4 Event table (2 of 6) IELSRn DELSRn Canceling Event Interrupt request Connect to Invoke Canceling Software number source Name NVIC Invoke DTC DMAC Snooze Standby 029h ADC140 ADC140_ADI   ...
Page 254 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.4 Event table (3 of 6) IELSRn DELSRn Canceling Event Interrupt request Connect to Invoke Canceling Software number source Name NVIC Invoke DTC DMAC Snooze Standby 053h I/O port IOPORT_GROUP1  * ...
Page 255 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.4 Event table (4 of 6) IELSRn DELSRn Canceling Event Interrupt request Connect to Invoke Canceling Software number source Name NVIC Invoke DTC DMAC Snooze Standby 07Bh GPT164 GPT4_CCMPA   ...
Page 256 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.4 Event table (5 of 6) IELSRn DELSRn Canceling Event Interrupt request Connect to Invoke Canceling Software number source Name NVIC Invoke DTC DMAC Snooze Standby 0A3h GPT169 GPT9_CCMPA   ...
Page 257 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.4 Event table (6 of 6) IELSRn DELSRn Canceling Event Interrupt request Connect to Invoke Canceling Software number source Name NVIC Invoke DTC DMAC Snooze Standby 0CBh SPI0 SPI0_SPRI   ...
Page 258 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) CPU : NVIC IELSRn Set by S/W interrupt Select of event factor Event factor pending Interrupt source Reset Reset Enable register Automatically cleared by Clear by S/W the interrupt completion Figure 14.2 Interrupt path of the ICU and CPU (NVIC) Use the following procedures for detecting interrupts: ...
Page 259 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) If you select the CPU or DTC in one IELSRn register, setting the same interrupt factor in any other IELSRn register is prohibited. Similarly, if you select the DMAC in one DELSRn register, setting the same interrupt factor in any other DELSRn register is prohibited.
Page 260 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Interrupt source IELSRn Interrupt request Event No.17 to 20 (011h to 014h) DELSRn DMAC activation DMAC request DMAC DMAC activation request activation control DMAC response DMAC interrupt Figure 14.3 DMAC request trigger and interrupt path 14.4.3 Digital Filter A digital filter function is provided for the external interrupt request pins (IRQi, i = 0 to 15) and the NMI pin interrupt.
Page 261 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) Sampling clock for digital filter IRQCRi.FLTEN bit Pulses removed The level matches three times IRQi pin The level matches three times IRQi_d (internal F/F) Digital filter enabled Disabled Enabled Operation example with IRQCRi.IRQMD[1:0] = 11b (low) Note 1.
Page 262 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU)  MPU bus slave error interrupt  CPU stack pointer monitor interrupt. Non-maskable interrupts can only be used with the CPU, not to activate the DTC or DMAC. Non-maskable interrupts take precedence over all other interrupts. The non-maskable interrupt states can be verified in the Non-Maskable Interrupt Status Register (NMISR).
Page 263 S3A3 User’s Manual 14. Interrupt Controller Unit (ICU) a. Set the event that you want to trigger a return to Normal mode from Snooze mode in SELSR0.SEL and set the value 017h (ICU_SNZCANCEL) in IELSRn.IELS. b. Set the event that you want to trigger a return to Normal mode from Snooze mode in IELSRn.IELS. 2.
Page 264 S3A3 User’s Manual 15. Buses Buses 15.1 Overview Table 15.1 lists the bus specifications, Figure 15.1 shows the bus configuration, and Table 15.2 lists the addresses assigned for each bus. Table 15.1 Bus specifications Bus type Description  Connected to the CPU Main bus ICode bus (CPU) ...
Page 265 S3A3 User’s Manual 15. Buses Table 15.2 Addresses assigned for each bus Address Area 0000 0000h to 01FF FFFFh Memory bus 1, 3 Code flash memory 2000 0000h to 2001 7FFFh Memory bus 4 SRAM0 4000 0000h to 4001 FFFFh Internal peripheral bus 1 Peripheral I/O registers 4004 0000h to 4005 FFFFh...
Page 266 S3A3 User’s Manual 15. Buses 15.2.3 External Bus Table 15.3 lists the external bus specifications. The external bus controller arbitrates requests for bus access on the external address space from the CPU system bus and the DMA bus. The priority order can be set using the external bus priority control bits (BUSSCNT.ARBMET).
Page 267 S3A3 User’s Manual 15. Buses Table 15.4 External pin configurations (2 of 2) Pin name Description WR0/WR Output WR0 signal is a strobe signal that indicates (when low) a write to an external address space is in progress in byte strobe mode, and D07 to D00 are valid, active-low. WR signal is a strobe signal that indicates a write to an external address space is in progress in single write strobe mode, active-low.
Page 268 S3A3 User’s Manual 15. Buses 15.2.6 Restriction on Endianness ® Memory space must be little-endian to execute code on the Cortex -M4 core. 15.3 Register Descriptions 15.3.1 CSn Control Register (CSnCR) (n = 0 to 3) Address(es): BUS.CS0CR 4000 3802h EMOD —...
Page 269 S3A3 User’s Manual 15. Buses 15.3.2 CSn Recovery Cycle Register (CSnREC) (n = 0 to 3) Address(es): BUS.CS0REC 4000 380Ah, BUS.CS1REC 4000 381Ah, BUS.CS2REC 4000 382Ah, BUS.CS3REC 4000 383Ah — — — — WRCV[3:0] — — — — RRCV[3:0] Value after reset: Symbol Bit name Description...
Page 270 S3A3 User’s Manual 15. Buses  After a read access to the external bus, a read access is made to the external bus in a different area  After a read access to the external bus, a write access is made to the external bus in the same area ...
Page 271 S3A3 User’s Manual 15. Buses 15.3.3 CS Recovery Cycle Insertion Enable Register (CSRECEN) Address(es): BUS.CSRECEN 4000 3880h RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN Value after reset: Symbol Bit name Description RCVEN0 Separate Bus Recovery Cycle Insertion 0: Disabled...
Page 272 S3A3 User’s Manual 15. Buses Table 15.5 Access type association with RCVENi/RCVENMj bits Associated bits Access type External address space Insertion of recovery cycles (Separate/Multiplexed) Read access after read Same area Recovery cycles specified in the RRCV[3:0] RCVEN0/RCVENM0 access bits for the precedence access area are inserted Different area Recovery cycles specified in the RRCV[3:0]...
Page 273 S3A3 User’s Manual 15. Buses WRMOD (Write Access Mode Select) The WRMOD bit selects a write access operating mode. Writing 0 selects byte strobe mode, in which data writes are controlled by the WRn signals (n = 0 and 1) associated with the respective byte positions. Writing 1 selects single write strobe mode, in which data writes are controlled by the BCn (n = 0 and 1) and the WR signals associated with the respective byte positions.
Page 274 S3A3 User’s Manual 15. Buses 15.3.5 CSn Wait Control Register 1 (CSnWCR1) (n = 0 to 3) Address(es): BUS.CS0WCR1 4000 3004h, BUS.CS1WCR1 4000 3014h, BUS.CS2WCR1 4000 3024h, BUS.CS3WCR1 4000 3034h — — — CSRWAIT[4:0] — — — CSWWAIT[4:0] Value after reset: —...
Page 275 S3A3 User’s Manual 15. Buses Do not attempt to write the CSnWCR1 register while the external bus is being accessed. Set each of these bits to satisfy the restrictions described in section 15.5.7 (1) Constraints on using separate bus interface or section 15.5.7 (2) Constraints on using address/data multiplexed bus...
Page 276 S3A3 User’s Manual 15. Buses 15.3.6 CSn Wait Control Register 2 (CSnWCR2) (n = 0 to 3) Address(es): BUS.CS0WCR2 4000 3008h, BUS.CS1WCR2 4000 3018h, BUS.CS2WCR2 4000 3028h, BUS.CS3WCR2 4000 3038h — CSON[2:0] — WDON[2:0] — WRON[2:0] — RDON[2:0] Value after reset: —...
Page 277 S3A3 User’s Manual 15. Buses Symbol Bit name Description b22 to b20 WRON[2:0] WR Assert Wait Select 0 0 0: No wait is inserted 0 0 1: Wait with a length of 1 clock cycle is inserted 0 1 0: Wait with a length of 2 clock cycles are inserted 0 1 1: Wait with a length of 3 clock cycles are inserted 1 0 0: Wait with a length of 4 clock cycles are inserted 1 0 1: Wait with a length of 5 clock cycles are inserted...
Page 278 S3A3 User’s Manual 15. Buses CSnWCR1.CSWWAIT[4:0] value. RDON[2:0] bits (RD Assert Wait Select) The RDON[2:0] bits specify the number of wait cycles to be inserted before the RD signal is asserted. Note: For normal read access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤ CSnWCR1.CSRWAIT[4:0] value.
Page 279 S3A3 User’s Manual 15. Buses 15.3.7 Master Bus Control Register (BUSMCNT<master>) Address(es): BUS.BUSMCNTM4I 4000 4000h, BUS.BUSMCNTM4D 4000 4004h, BUS.BUSMCNTSYS 4000 4008h, BUS.BUSMCNTDMA 4000 400Ch IERES — — — — — — — — — — — — — — — Value after reset: Symbol Bit name...
Page 280 S3A3 User’s Manual 15. Buses Symbol Bit name Description b5, b4 ARBMET[1:0] Arbitration Method Specify the priority between groups: b5 b4 0 0: Fixed priority 0 1: Round-robin 1 0: Setting prohibited 1 1: Setting prohibited. b15 to b6 — Reserved These bits are read as 0.
Page 281 S3A3 User’s Manual 15. Buses Note: This register is only cleared by resets other than MPU related resets. For more information, see section 6, Resets section 16, Memory Protection Unit (MPU). Table 15.7 lists the registers associated with each bus type. BERAD[31:0] bits (Bus Error...
Page 282 S3A3 User’s Manual 15. Buses For more information on bus errors, see section 15.6, Bus Error Monitoring Section, and section 16, Memory Protection Unit (MPU). 15.4 Endianness and Data Alignment The external bus has a data alignment function to control which byte of the data bus (D15 to D08, or D07 to D00) is used when accessing the external address space (the CS area).
Page 283 S3A3 User’s Manual 15. Buses WR1/BC1 WR0/BC0 Access Number of Data Bus Unit of Data Size Address Access Bus Cycle Address Data First 8 bits 4n+1 First 8 bits 8 bits 4n+2 First 8 bits 4n+2 4n+3 First 8 bits 4n+2 First 16 bits...
Page 284 S3A3 User’s Manual 15. Buses WR1/BC1 WR0/BC0 Access Number of Unit of Data Bus Data Size Address Access Bus Cycle Data Address First 8 bits 4n+1 First 8 bits 4n+1 8 bits 4n+2 First 8 bits 4n+2 4n+3 First 8 bits 4n+3 First 8 bits...
Page 285 S3A3 User’s Manual 15. Buses 15.5 Operation of CS Area Controller 15.5.1 Separate Bus This section describes the periods shown in the timing diagrams. The CS area controller (CSC) operates in sync with the external bus clock, BCLK. Operation cycles, such as wait cycles, specified in the CSC register, are counted on BCLK. In the following description, the frequencies of BCLK and EBCLK pin output are the same, unless otherwise noted.
Page 286 S3A3 User’s Manual 15. Buses For page access, this is inserted within the clock cycle period where the strobe signal is valid and subsequent page accesses, or within the clock cycle period for the CS extension (see section (c), Tn1 to Tnm (clock cycles of CS extension)).
Page 287 S3A3 User’s Manual 15. Buses Next bus access can be started Tend External bus clock (BCLK) Write-access CS extension cycle (CSWOFF) Normal write cycle wait (CSWWAIT) Address (A23 to A00) CS assert wait (CSON) Chip select (CSn) Byte control (BCm) WR assert wait (WRON) Data write (WR)
Page 288 S3A3 User’s Manual 15. Buses cycles)) are also inserted in the second and subsequent external bus accesses. See Figure 15.32. The values in the wait control registers shown in the figures are example settings. In your application, set the register bits according to the specifications of connected devices.
Page 289 S3A3 User’s Manual 15. Buses Tend Tend External bus clock (BCLK) CSWWAIT: 2 Normal write cycle wait (CSWWAIT): 2 Address (A23 to A00) Write-access CS extension cycle (CSWOFF): 1 CSWOFF: 1 Chip select (CSn) Byte control (BCm) WR assert wait (WRON): 1 WRON: 1 Data write (WR)
Page 290 S3A3 User’s Manual 15. Buses Tend Tend EBCLK pin output External bus clock (BCLK) Address (A23 to A00) Write-access CS extension cycle Normal write cycle wait Normal read cycle wait Read-access CS extension (CSWOFF): 1 (CSRWAIT): 2 (CSWWAIT): 2 cycle (CSROFF): 2 Chip select (CSn) Byte control...
Page 291 S3A3 User’s Manual 15. Buses Tend Tend EBCLK pin output External bus clock (BCLK) Address (A23 to A00) Write-access CS extension Normal write cycle wait (CSWWAIT): 3 CSWWAIT: 3 cycle (CSWOFF): 1 CSWOFF : 1 Chip select (CSn) CS assert wait (CSON): 1 CSON: 1 Byte control (BCm)
Page 292 S3A3 User’s Manual 15. Buses Tend Tend EBCLK pin output External bus clock (BCLK) Address (A23 to A00) Write-access CS extension cycle Normal write cycle wait (CSWOFF): 1 (CSWWAIT): 3 CSWWAIT: 3 CSWOFF: 1 Chip select (CSn) CS assert wait (CSON): 1 CSON: 1 Byte control (BCm)
Page 293 S3A3 User’s Manual 15. Buses Next bus access can be started Tend Tpw1 Tpwn Tend External bus clock (BCLK) Read-access CS extension cycle Normal read cycle wait (CSRWAIT) Page read cycle wait (CSPRWAIT) (CSROFF) Address (A23 to A00) CS assert wait (CSON) Chip select (CSn) Byte control...
Page 294 S3A3 User’s Manual 15. Buses Figure 15.19 Figure 15.20 show examples of operations for access to a 16-bit bus space in 32 bits. The values of the wait control registers shown in the figures are example settings. In your application, set the registers according to the specifications of connected devices.
Page 295 S3A3 User’s Manual 15. Buses CSWWAIT: 4 CSPWWAIT: 4 Tend Tdw1 Tpw1 Tend External bus clock (BCLK) Address (A23 to A00) CSWOFF: 1 Chip select (CSn) Byte control (BC1, BC0) WRON: 1 WRON: 1 Data write (WR) WDON: 1 Data bus (D15 to D00) WDOFF: 1 WDON: 1...
Page 296 S3A3 User’s Manual 15. Buses CSRWAIT: 5 CSRWAIT: 3 Tend Tpw1 Tpw2 Tpw3 Tend EBCLK pin output External bus clock (BCLK) Address (A23 to A00) CSROFF: 1 Chip select (CSn) Byte control (BC1, BC0) RDON: 1 RDON: 1 Data read (RD) Data bus (D15 to D00)
Page 297 S3A3 User’s Manual 15. Buses CSPWWAIT: 4 CSWWAIT: 4 Tend Tdw1 Tpw1 Tpw2 Tpw3 Tpw4 Tend EBCLK pin output External bus clock (BCLK) Address (A23 to A00) CSWOFF: 1 Chip select (CSn) Byte control (BC1, BC0) WRON: 1 WRON: 1 Data write (WR) WDON: 1...
Page 298 S3A3 User’s Manual 15. Buses Figure 15.23 Figure 15.25 show examples of operations with the address/data multiplexed I/O interface Address cycle Data cycle Tend External bus clock (BCLK) Address Address cycle wait (AWAIT) Address/data bus 1 cycle fixed Address latch (ALE) RD assert wait (RDON) Data read...
Page 299 S3A3 User’s Manual 15. Buses Address cycle Data cycle Tend External bus clock (BCLK) Write data output wait (WDON) Address Data output extension cycle (WDOFF) Address cycle wait (AWAIT) Address/data bus 1 cycle fixed Address latch (ALE) WR assert wait (WRON) Data write (WRm) Write-access CS extension cycle (CSWOFF)
Page 300 S3A3 User’s Manual 15. Buses Address cycle Data cycle Address cycle Data cycle Twn Tend Tn1 Twn Tend Tn1 EBCLK output External bus clock (BCLK) Address Write data output wait (WDON): 4 Data output extension cycle Address cycle wait (AWAIT): 1 Address cycle wait (AWAIT): 1 (WDOFF): 1 Address/data...
Page 301 S3A3 User’s Manual 15. Buses … Twn (Tend) Tend Tpw1 … Tpwn (Tend) Tend External bus clock (BCLK) Address (A23 to A00) Chip select/ byte control (CSn/BC) Data read (RD) Read cycle wait (CSRWAIT) Page read cycle wait (CSPRWAIT) Data bus (D15 to D00) External wait (WAIT)
Page 302 S3A3 User’s Manual 15. Buses (Tend) (Tend) Tend Tdw1 … Tend Tpw1 … Tpwn Tdw1 External bus clock (BCLK) Address (A23 to A00) Chip select (CSn) Data read (RD) WR assert wait (WRON) WR assert wait (WRON) Data write (WR) Page write cycle wait (CSPWWAIT) Write cycle wait (CSWWAIT) Data bus...
Page 303 S3A3 User’s Manual 15. Buses Address Address Data cycle Data cycle cycle cycle Tw4 (Tend) Tend (Tend) Tend External bus clock (BCLK) Address Address/data bus Address latch (ALE) Chip select/ byte control (CSn/BCm) Data read (RD) Normal read cycle wait (CSRWAIT) Normal read cycle wait (CSRWAIT) External wait (WAIT)
Page 304 S3A3 User’s Manual 15. Buses access over the external bus starts immediately after the end of the recovery cycles. When two or more external bus access cycles are required for a single transfer request from a bus master, and the recovery cycle insertion condition is satisfied, recovery cycles are also inserted between these bus access cycles.
Page 305 S3A3 User’s Manual 15. Buses CS1 read recovery CS0 write recovery CS0 write recovery (CS1REC.RRCV[3:0]): 1 (CS0REC.WRCV[3:0]): 2 (CS0REC.WRCV[3:0]): 2 CS1 read (1) CS0 write (1) Write (2) Read (2) Tw1 Tw2 Tend Tw1 Tw2 Tend Tend Tw1 Tend External bus clock (BCLK) Address A0(1)
Page 306 S3A3 User’s Manual 15. Buses CS0 write recovery CS0 read recovery CS1 read CS0 write (CS0.WRCV) : 4 CS0 read (CS0.RRCV) : 4 EBCLK pin output Tend Tend Tend External bus clock (BCLK) Address (A23 to A00) Chip select 0 (CS0) Chip select 1 (CS1)
Page 307 S3A3 User’s Manual 15. Buses CS0 write recovery CS1 read recovery (CS0REC.WRCV[3:0]): 1 (CS1REC.RRCV[3:0]): 1 CS0 write (1) CS0 write (2) CS1 read (1) CS1 read (2) Tw1 Tw2 Tend Tw1 Tw2 Tend Tr1 Tw1 Tw2 Tw3 Tend Tr1 Tw1 Tw2 Tw3 Tend Tr1 External bus clock (BCLK) Address...
Page 308 S3A3 User’s Manual 15. Buses (CSnMOD.PRENB = 1 or CSnMOD.PWENB = 1), the first page access or access that does not fall within the scope of a page access is a normal access operation. Because of this, constraints on normal access must be satisfied. Table 15.10 Constraints on normal access and page access Constraints on normal access...
Page 309 S3A3 User’s Manual 15. Buses  Illegal address access  Bus master MPU error  Bus slave MPU error  Timeout. Table 15.12 lists the address ranges where access leads to illegal address access errors. However, the reserved area in the slave does not trigger an illegal address access error.
Page 310 S3A3 User’s Manual 15. Buses 0200 0000h, the bus module can detect the error. Note 1. The bus module does not detect whether the MMF switched the address. Therefore if the MMF is enabled and the CPU accesses 0200 0000h, no error occurs (depends on the switched address). If the MMF is disabled and the CPU accesses 0200 0000h, the bus module can detect the error.
Page 311 S3A3 User’s Manual 16. Memory Protection Unit (MPU) Memory Protection Unit (MPU) 16.1 Overview The MCU has four Memory Protection Units (MPUs) and a CPU stack pointer monitor function. Table 16.1 lists the supported MPU specifications, and Table 16.2 shows the behavior on detection of each MPU error. Table 16.1 MPU specifications Classification...
Page 312 S3A3 User’s Manual 16. Memory Protection Unit (MPU) Table 16.3 CPU stack pointer monitor specifications (2 of 2) Parameter Description Number of regions 2 regions:  Main Stack Pointer (MSP)  Process Stack Pointer (PSP). Address specification for individual regions Specifying start and end addresses for individual regions Stack pointer monitor enable or disable setting for Enabling or disabling stack pointer monitor for individual regions...
Page 313 S3A3 User’s Manual 16. Memory Protection Unit (MPU) CPU processor register set Process Stack Main Stack R13 (SP) Pointer (PSP) Pointer (MSP) R14 (LR) R15 (PC) xPSR CPU stack pointer monitor Main stack pointer monitor ENABLE Start address address Reset Compare Non-maskable (within)
Page 314 S3A3 User’s Manual 16. Memory Protection Unit (MPU) Start Write Main Stack Pointer (MSP) register Write Process Stack Pointer (PSP) register Write MSPMPUSA and MSPMPUEA registers Write PSPMPUSA and PSPMPUEA registers Write MSPMPUCTL and PSPMPUCTL registers Write MSPMPUOAD and PSPMPUOAD registers Write MSPMPUPT and PSPMPUPT register Figure 16.2 Register setting flow...
Page 315 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 16.2.3.1 Main Stack Pointer (MSP) Monitor Start Address Register (MSPMPUSA) Address(es): SPMON.MSPMPUSA 4000 0D08h MSPMPUSA[31:16] Value after reset: MSPMPUSA[15:0] Value after reset: x: Undefined Symbol Bit name Description b31 to b0 MSPMPUSA[31:0] Region Start Address Address where the region starts, for use in region determination.
Page 316 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 16.2.3.3 Process Stack Pointer (PSP) Monitor Start Address Register (PSPMPUSA) Address(es): SPMON.PSPMPUSA 4000 0D18h PSPMPUSA[31:16] Value after reset: PSPMPUSA[15:0] Value after reset: x: Undefined Symbol Bit name Description b31 to b0 PSPMPUSA[31:0] Region Start Address Address where the region starts, for use in region determination.
Page 317 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 16.2.3.5 Stack Pointer Monitor Operation After Detection Register (MSPMPUOAD, PSPMPUOAD) Address(es): SPMON.MSPMPUOAD 4000 0D00h, SPMON.PSPMPUOAD 4000 0D10h KEY[7:0] — — — — — — — Value after reset: Symbol Bit name Description Operation after Detection 0: Non-maskable interrupt 1: Reset.
Page 318 S3A3 User’s Manual 16. Memory Protection Unit (MPU)  MSPMPUEA  MSPMPUOAD. When the PSPMPUCTL.ENABLE bit is set to 1, the following registers are available:  PSPMPUSA  PSPMPUEA  PSPMPUOAD. ERROR (Stack Pointer Monitor Error Flag) The ERROR bit indicates the status of the stack pointer monitor. Each stack point monitor has an independent ERROR bit.
Page 319 S3A3 User’s Manual 16. Memory Protection Unit (MPU) When writing to the PROTECT bit, simultaneously write A5h to the KEY[7:0] bits, using halfword access. KEY[7:0] bits (Key Code) The KEY[7:0] bits enable or disable writes to the PROTECT bit. When writing to the PROTECT bit, write A5h to KEY[7:0] simultaneously.
Page 320 S3A3 User’s Manual 16. Memory Protection Unit (MPU) DMAC/DTC ICode bus DCode bus System bus Bus Master MPU Group A Bus Master MPU DMA bus External Code flash Data flash Internal SRAM0 memory peripheral bus cont. memory Figure 16.3 MPU bus master block diagram Figure 16.4 shows the MPU bus master group A.
Page 321 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 16.4.1.1 Group A Region n Start Address Register (MMPUSAn) (n = 0 to 15) Address(es): MMPU.MMPUSA0 4000 0204h, MMPU.MMPUSA1 4000 0214h, MMPU.MMPUSA2 4000 0224h, MMPU.MMPUSA3 4000 0234h, MMPU.MMPUSA4 4000 0244h, MMPU.MMPUSA5 4000 0254h, MMPU.MMPUSA6 4000 0264h,...
Page 322 S3A3 User’s Manual 16. Memory Protection Unit (MPU) Symbol Bit name Description Read Protection 0: Read access permitted 1: Read access protected. Write Protection 0: Write access permitted 1: Write access protected. b15 to b3 — Reserved These bits are read as 0. The write value should be 0. R/W The ENABLE, RP, and WP bits are individually configurable for each group A region n.
Page 323 S3A3 User’s Manual 16. Memory Protection Unit (MPU) Table 16.6 Function of master control circuit Output of group A Output of group A Output of group A MMPUCTLA.ENABLE region 0 unit region 1 unit region 2 to 15 unit Function of group A Don’t care Don’t care Protected region...
Page 324 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 16.4.1.5 Group A Protection of Register (MMPUPTA) Address(es): MMPU.MMPUPTA 4000 0102h PROTE KEY[7:0] — — — — — — — Value after reset: Symbol Bit name Description PROTECT Protection of register 0: All bus master MPU group A register writes are permitted 1: All bus master MPU group A register writes are protected.
Page 325 S3A3 User’s Manual 16. Memory Protection Unit (MPU) MMPUCTLA. MMPUCTLA. Setting of all regions ENABLE bit = 0 ENABLE bit = 1 Setting of Protected region regions Region 0 R/W Region 1 read only Clearing of MMPUACAn. Region 2 write only All memory is All memory is ENABLE bit...
Page 326 S3A3 User’s Manual 16. Memory Protection Unit (MPU) Start Write MMPUCTLA.OAD bit All memory is protected region Set MMPUCTLA.ENABLE bit Write MMPUSAn and MMPUEAn registers Write MMPUACAn register Region selected in the MMPUACAn register is added Set MMPUPTA.PROTECT bit The register is protected Figure 16.7 Register setting flow after reset Figure 16.8...
Page 327 S3A3 User’s Manual 16. Memory Protection Unit (MPU) SYSTEM.RSTSR1.BUSMRF. For details, see section 6, Resets. 16.5 Bus Slave MPU The bus slave MPU monitors access to the bus slave functions, such as flash or SRAM. The bus slave function can be accessed from two bus masters, the CPU, and the bus master MPU group A.
Page 328 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 16.5.1 Register Descriptions Note: Bus access must be stopped before writing to MPU registers. 16.5.1.1 Access Control Register for Memory Bus 3 (SMPUMBIU) Address(es): SMPU.SMPUMBIU 4000 0C10h WPGR RPGRP — — — —...
Page 329 S3A3 User’s Manual 16. Memory Protection Unit (MPU) RPGRPA (Master Group A Read protection) The RPGRPA bit enables or disables memory protection for master group A reads on internal peripheral Bus 9. WPGRPA (Master Group A Write protection) The WPGRPA bit enables or disables memory protection for master group A writes on internal peripheral bus 9. 16.5.1.3 Access Control Register for Memory Bus 4 (SMPUSRAM0)
Page 330 S3A3 User’s Manual 16. Memory Protection Unit (MPU) Symbol Bit name Description RPGRPA Master Group A Read 0: Memory protection for master group A read disabled protection 1: Memory protection for master group A read enabled. WPGRPA Master Group A Write 0: Memory protection for master group A write disabled protection 1: Memory protection for master group A write enabled.
Page 331 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 16.5.1.6 Access Control Register for Internal Peripheral Bus 7 (SMPUP6BIU) Address(es): SMPU.SMPUP6BIU 4000 0C28h WPGR RPGRP WPCP — — — — — — — — — — — — RPCPU Value after reset: Symbol Bit name Description...
Page 332 S3A3 User’s Manual 16. Memory Protection Unit (MPU) RPCPU (CPU Read protection) The RPCPU bit enables or disables memory protection for CPU reads in CS area. WPCPU (CPU Write protection) The WPCPU bit enables or disables memory protection for CPU writes in CS area. RPGRPA (Master Group A Read protection)
Page 333 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 16.5.1.9 Slave MPU Control Register (SMPUCTL) Address(es): SMPU.SMPUCTL 4000 0C00h PROTE KEY[7:0] — — — — — — Value after reset: Symbol Bit name Description Operation after 0: Non-maskable interrupt detection 1: Reset. PROTECT Protection of register 0: All bus slave register writes are permitted...
Page 334 S3A3 User’s Manual 16. Memory Protection Unit (MPU) or RPGRPA) bit in the access control registers (SMPUMBIU, SMPUFBIU, SMPUSRAM0, SMPUP0BIU, SMPUP2BIU, SMPUP6BIU, SMPUEXBIU, and SMPUEXBIU2). 16.5.2.2 Protecting the registers Registers related to the bus slave MPU can be protected with the PROTECT bit in the SMPUCTL register. 16.5.2.3 Memory protection error If access to a protected region is detected, the bus slave MPU generates a memory protection error.
Page 335 S3A3 User’s Manual 16. Memory Protection Unit (MPU) Monitor of program counter PC region 0 Program counter PC region 1 Monitor of DCode bus Region 0 Mask of access Bus of CPU Region 1 of CPU Monitor of system bus Region 1 Mask of access Region 2...
Page 336 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 00FF FFFFh, not including the reserved areas) or SRAM (1FF0 0000h to 200F FFFFh, not including the reserved areas). The secure program is executed in the memory space defined by the SECMPUPCSn and SECMPUPCEn registers and can access the secure data specified in the SECMPUSm and SECMPUEm registers (m = 0 to 3).
Page 337 S3A3 User’s Manual 16. Memory Protection Unit (MPU) The SECMPUS0 and SECMPUE0 registers specify the secure program and the flash data (0000 0000h to 00FF FFFFh, not including the reserved areas). The memory space defined in the SECMPUS0 and SECMPUE0 registers can only be accessed from the secure program set up in the SECMPUPCSn and SECMPUPCEn registers.
Page 338 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 16.6.1.6 Security MPU Region 1 End Address Register (SECMPUE1) Address(es): SECMPUE1 0000 0424h SECMPUE1[31:16] Value after reset: The value set by user SECMPUE1[15:0] Value after reset: The value set by user Symbol Bit name Description b31 to b0...
Page 339 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 16.6.1.8 Security MPU Region 2 End Address Register (SECMPUE2) Address(es): SECMPUE2 0000 042Ch — — — — — — — — — SECMPUE2[22:16] Value after reset: The value set by user SECMPUE2[15:0] Value after reset: The value set by user Symbol...
Page 340 S3A3 User’s Manual 16. Memory Protection Unit (MPU) 16.6.1.10 Security MPU Region 3 End Address Register (SECMPUE3) Address(es): SECMPUE3 0000 0434h — — — — — — — — — SECMPUE3[22:16] The value set by user Value after reset: SECMPUE3[15:0] The value set by user Value after reset: Symbol...
Page 341 S3A3 User’s Manual 16. Memory Protection Unit (MPU) Note: To enable or disable the security MPU, see section 16.6.2, Memory Protection. DIS0 (Region 0 Disable) The DIS0 bit enables or disables the security MPU region 0. If security MPU region 0 is enabled, the code flash region within the limits set up by the SECMPUS0 and SECMPUE0 is secure data.
Page 342 S3A3 User’s Manual 16. Memory Protection Unit (MPU) Security MPU setting Memory Memory Non-secure data Secure function Region 3 Secure data Non-secure data Non-secure Secure function Region 2 Secure data program Non-secure data SRAM Region 1 Secure data PC region 1 Secure program Code flash Non-secure...
Page 343 S3A3 User’s Manual 17. DMA Controller (DMAC) DMA Controller (DMAC) 17.1 Overview The MCU includes a 4-channel DMA Controller (DMAC) that can transfer data without intervention from the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address.
Page 344 S3A3 User’s Manual 17. DMA Controller (DMAC) DMAC DMAC registers DMAC channels Activation control (CH0 to CH3) DMSAR DMDAR DMCRA DMA start DMCRB request transfer DMOFR request DMTMD arbitration DMAMD DMSTS DMCNT Interrupt DMCSL DMAC controller response DMAST DMIST Interrupt request for ICU (DMACm_INT) Register control...
Page 345 S3A3 User’s Manual 17. DMA Controller (DMAC) 17.2 Register Descriptions 17.2.1 DMA Source Address Register (DMSAR) Address(es): DMAC0.DMSAR 4000 5000h, DMAC1.DMSAR 4000 5040h, DMAC2.DMSAR 4000 5080h, DMAC3.DMSAR 4000 50C0h Value after reset: Value after reset: Description Setting range b31 to b0 Specifies the transfer source start address 0000 0000h to FFFF FFFFh (4 GB) Set DMSAR while DMAC activation is disabled (the DMST bit in DMAST = 0) or DMA transfer is disabled (the DTE...
Page 346 S3A3 User’s Manual 17. DMA Controller (DMAC) 17.2.3 DMA Transfer Count Register (DMCRA) Address(es): DMAC0.DMCRA 4000 5008h, DMAC1.DMCRA 4000 5048h, DMAC2.DMCRA 4000 5088h, DMAC3.DMCRA 4000 50C8h  Normal transfer mode DMCRAH — — — — — — Value after reset: DMCRAL Value after reset: ...
Page 347 S3A3 User’s Manual 17. DMA Controller (DMAC) Setting bits [15:10] in DMCRAL is invalid. Write 0 to these bits. The value in DMCRAL is decremented by one each time data is transferred until it reaches 000h, at which time the value in DMCRAH is loaded into DMCRAL. 17.2.4 DMA Block Transfer Count Register (DMCRB)
Page 348 S3A3 User’s Manual 17. DMA Controller (DMAC) DTS[1:0] bits (Repeat Area Select) The DTS[1:0] bits select either the source or destination as the repeat area in repeat transfer mode and the block area in block transfer mode. In normal transfer mode, these bit settings are invalid. 17.2.6 DMA Interrupt Setting Register (DMINT)
Page 349 S3A3 User’s Manual 17. DMA Controller (DMAC) ESIE (Transfer Escape End Interrupt Enable) The ESIE bit enables the transfer escape end interrupt requests (repeat size end interrupt request and extended repeat area overflow interrupt request) that occur during DMA transfer. The interrupt occurs when this bit is 1 and the ESIF flag in DMSTS is set to 1.
Page 350 S3A3 User’s Manual 17. DMA Controller (DMAC) decremented by 1, 2, and 4, respectively  When offset addition is selected, the offset specified in the DMACm.DMOFR register is added to the address. SARA[4:0] bits (Source Address Extended Repeat Area) The SARA[4:0] bits specify the extended repeat area on the source address. The extended repeat area function is realized through an update of the specified lower address bits with the remaining upper address bits fixed.
Page 351 S3A3 User’s Manual 17. DMA Controller (DMAC) Table 17.2 SARA[4:0] or DARA[4:0] settings and corresponding repeat areas (2 of 2) SARA[4:0] or DARA[4:0] Extended repeat area 10111b 8 MB specified as extended repeat area by the lower 23 bits of the address 11000b 16 MB specified as extended repeat area by the lower 24 bits of the address 11001b...
Page 352 S3A3 User’s Manual 17. DMA Controller (DMAC)  When 0 is written to this bit  When the specified total volume of data transfer is complete  When DMA transfer is stopped by a repeat size end interrupt  When DMA transfer is stopped by an extended repeat area overflow interrupt. 17.2.10 DMA Software Start Register (DMREQ)
Page 353 S3A3 User’s Manual 17. DMA Controller (DMAC) 17.2.11 DMA Status Register (DMSTS) Address(es): DMAC0.DMSTS 4000 501Eh, DMAC1.DMSTS 4000 505Eh, DMAC2.DMSTS 4000 509Eh, DMAC3.DMSTS 4000 50DEh — — DTIF — — — ESIF Value after reset: Symbol Bit name Description ESIF Transfer Escape End Interrupt 0: No interrupt occurred R/W*...
Page 354 S3A3 User’s Manual 17. DMA Controller (DMAC) flag (DMA Active Flag) The ACT flag indicates whether the DMAC is in the idle or active state. [Setting condition]  When the DMAC starts a data transfer. [Clearing condition]  When the data transfer in response to one transfer request completes. 17.2.12 DMAC Module Activation Register (DMAST)
Page 355 S3A3 User’s Manual 17. DMA Controller (DMAC) Table 17.3 Register update operation in normal transfer mode (2 of 2) Register Function Update operation after completion of a transfer for one transfer request DMACm.DMCRAL Transfer count Decremented by one or not updated (in free running mode) DMACm.DMCRAH Not updated (not used in normal transfer mode) DMACm.DMCRB...
Page 356 S3A3 User’s Manual 17. DMA Controller (DMAC) Table 17.4 Register update operation in repeat transfer mode Update operation after completion of a transfer for one transfer request When DMACm.DMCRAL is 1 Register Function When DMACm.DMCRAL is not 1 (transfer of the last repeat size data unit) ...
Page 357 S3A3 User’s Manual 17. DMA Controller (DMAC) mode, when all data in a single block is transferred, you can stop DMA transfer and request a repeat size end interrupt. To resume DMA transfer, write 1 to the DTE bit in DMACm.DMCNT during repeat size end interrupt handling. A transfer end interrupt request can be generated after completion of the specified number of block transfers.
Page 358 S3A3 User’s Manual 17. DMA Controller (DMAC) occurs in the extended repeat area on the transfer source while the SARIE bit in DMACm.DMINT is set to 1, the ESIF flag in DMACm.DMSTS is set to 1 and the DTE bit in DMACm.DMCNT is set to 0 to stop DMA transfer. At this point, if the ESIE bit in DMACm.DMINT is set to 1, an interrupt by an extended repeat area overflow is requested.
Page 359 S3A3 User’s Manual 17. DMA Controller (DMAC) Example: 8 bytes are specified as an extended repeat area by the lower 3 bits of DMACm.DMSAR (SARA[4:0] bits in DMACm.DMAMD = 00011b), block transfer mode with block size 5 is set (DMACm.DMCRA = 00050005h), and transfer source address is not specified as a block area. Data size is 8 bits (SZ[1:0] bits in DMACm.DMTMD = 00b).
Page 360 S3A3 User’s Manual 17. DMA Controller (DMAC) Transfer Address B1 Data 1 Address A1 Data 1 Address B2 = address B1 + 4 Data 2 Data 3 Address B3 = address B2 + 4 Offset value Data 4 Address B4 = address B3 + 4 Data 5 Address B5 = address B4 + 4 Data 2...
Page 361 S3A3 User’s Manual 17. DMA Controller (DMAC) First Data 1 Data 5 Data 9 Data 13 Data 1 Data 2 Data 3 Data 4 cycle Transfer Data 2 Data 6 Data 10 Data 14 Data 5 Data 6 Data 7 Data 8 Second cycle Data 3...
Page 362 S3A3 User’s Manual 17. DMA Controller (DMAC) Start Set the address, repeat size, and number of repeat operations Set repeat transfer mode Enable repeat size end interrupts Write 1 to the DTE bit in DMAC0.DMCNT Receive transfer request Transfer data Decrement repeat size and number of repeat operations Number of repeat operations = 0? Repeat size = 0?
Page 363 S3A3 User’s Manual 17. DMA Controller (DMAC) 17.3.4 Activation Sources Software, the interrupt requests from the peripheral modules, and external interrupt requests can all be specified as DMAC activation sources. Set the DCTG[1:0] bits in DMACm.DMTMD to select the activation source. (1) DMAC activation through software To start DMA transfer through software: 1.
Page 364 S3A3 User’s Manual 17. DMA Controller (DMAC) System clock Peripheral module or external pin interrupts DMAC activation request DMAC access Data transfer Data transfer Figure 17.10 DMAC operation timing example 1 with DMA activation by interrupt from peripheral module/ external interrupt input pin, in normal transfer mode or repeat transfer mode System clock Peripheral function interrupts or...
Page 365 S3A3 User’s Manual 17. DMA Controller (DMAC) Cr = Read destination access cycle. Cw = Data write destination access cycle. Note 1. This is the case when the block size is 2 or more. When the block size is 1, normal transfer cycle applies. Cr and Cw depend on the access destination.
Page 366 S3A3 User’s Manual 17. DMA Controller (DMAC) Initial settings To use peripheral function Disable the peripheral function as the DMACm Disable the control register for the peripheral function interrupts as DMA activation request source sources Disable the IRQ pin as the DMACm request To use external pin interrupts as source DMA activation sources...
Page 367 S3A3 User’s Manual 17. DMA Controller (DMAC) 17.3.8 Starting DMA Transfer To enable a DMA transfer of channel m, set the DTE bit in DMACm.DMCNT to 1 (DMA transfer enabled) and set the DMST bit in DMAST to 1 (DMAC start enabled). New activation requests are not accepted during the transfer of another DMAC channel or DTC.
Page 368 S3A3 User’s Manual 17. DMA Controller (DMAC) is requested. When this bit and the ESIE bit in DMACm.DMINT are 1, a transfer escape end interrupt is requested. This flag is set to 1 when the bus cycle of the DMA transfer that caused the interrupt request is complete and the ACT flag in DMACm.DMSTS is set to 0, indicating the DMA transfer end.
Page 369 S3A3 User’s Manual 17. DMA Controller (DMAC) If this interrupt is requested during a read cycle, the subsequent write cycle is performed. In block transfer mode, if the interrupt is requested during a 1-block transfer, the remaining data in the block is transferred before transfer stops. Before sending an interrupt request from the DMAC to the CPU or the DTC, the interrupt control register must be set.
Page 370 S3A3 User’s Manual 17. DMA Controller (DMAC) Different procedures are used for canceling an interrupt to restart a DMA transfer in the following cases:  When terminating a DMA transfer  When continuing a DMA transfer. (1) When terminating a DMA transfer Write 0 to the DTIF flag in DMACm.DMSTS to clear a transfer end interrupt, and to the ESIF flag in DMACm.DMSTS to clear a repeat size interrupt or an extended repeat area overflow interrupt.
Page 371 S3A3 User’s Manual 17. DMA Controller (DMAC) (1) Module-stop function Writing 1 to the MSTPA22 bit in MSTPCRA enables the module-stop function of the DMAC. If a DMA transfer is in progress when 1 is written to the MSTPA22 bit, the transition to the module-stop state continues after DMA transfer ends.
Page 372 S3A3 User’s Manual 17. DMA Controller (DMAC) the DMA transfer, write the event number to the ICU.DELSRn.DELS[7:0] bit with the settings shown in section 17.3.7, Activating DMAC. R01UM0006EU0110 Rev.1.10 Page 372 of 1618 Jul 3, 2018...
Page 373 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Data Transfer Controller (DTC) 18.1 Overview The MCU includes a Data Transfer Controller (DTC) that performs data transfers when activated by an interrupt request. Table 18.1 lists the DTC specifications and Figure 18.1 shows a block diagram.
Page 374 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Non-maskable interrupt request NVIC Interrupt request Activation request DMAC DMAC response Interrupt controller Register Vector number control Activation Activation request control DTC response Bus interface DTCCR Snooze control response DTCVBR signals control DTCST DTC_ DTCEND...
Page 375 S3A3 User’s Manual 18. Data Transfer Controller (DTC) 18.2.1 DTC Mode Register A (MRA) Address(es): (inaccessible directly from the CPU. See section 18.3.1) MD[1:0] SZ[1:0] SM[1:0] — — Value after reset: x: Undefined Symbol Bit name Description b1, b0 — Reserved These bits are read as undefined.
Page 376 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Symbol Bit name Description b3, b2 DM[1:0] Transfer Destination Address — b3 b2 0 0: Address in the DAR register is fixed Addressing Mode (write-back to DAR is skipped) 0 1: Address in the DAR register is fixed (write-back to DAR is skipped) 1 0: DAR value is incremented after data transfer: +1 when MRA.SZ[1:0] bits = 00b...
Page 377 S3A3 User’s Manual 18. Data Transfer Controller (DTC) access the SRAM area (transfer information (n) start address + 04h) and the DTC automatically transfers the transfer information to and from the SAR register. See section 18.3.1, Allocating Transfer Information and DTC Vector Table.
Page 378 S3A3 User’s Manual 18. Data Transfer Controller (DTC) register. See section 18.3.1, Allocating Transfer Information and DTC Vector Table. (1) Normal transfer mode (MRA.MD[1:0] bits = 00b) In normal transfer mode, CRA functions as a 16-bit transfer counter. The transfer count is 1, 65,535, and 65,536 when the set value is 0001h, FFFFh, and 0000h, respectively.
Page 379 S3A3 User’s Manual 18. Data Transfer Controller (DTC) When the transfer counter (CRA register) becomes 0 during the previous normal transfer and when the transfer counter (CRB register) becomes 0 during the previous block transfer, the transfer information is read regardless of the RRS bit value.
Page 380 S3A3 User’s Manual 18. Data Transfer Controller (DTC) 18.2.10 DTC Status Register (DTCSTS) Address(es): DTC.DTCSTS 4000 540Eh — — — — — — — VECN[7:0] Value after reset: Symbol Bit name Description b7 to b0 VECN[7:0] DTC-Activating Vector These bits indicate the vector number for the activation source Number Monitoring when a DTC transfer is in progress.
Page 381 S3A3 User’s Manual 18. Data Transfer Controller (DTC) 18.3.1 Allocating Transfer Information and DTC Vector Table The DTC reads the start address of the transfer information associated with each activation source from the vector table and reads the transfer information starting at that address. The vector table must be located so that the lower 10 bits of the base address (start address) are 0.
Page 382 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Allocation of transfer information Lower address Start address Reserved (0) Transfer information per transfer (4 words (16 bytes)) Chain transfer Reserved (0) Transfer information for the second transfer in chain transfer mode (4 words (16 bytes)) 4 bytes Figure 18.3...
Page 383 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Setting the MRB.CHNE bit to 1 allows multiple transfers or chain transfer on a single activation source. It also enables a chain transfer when the specified data transfer is complete. Figure 18.4 shows the operation flow of the DTC.
Page 384 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Table 18.3 Chain transfer conditions First transfer Second transfer* CHNE CHNS DISEL Transfer CHNE CHNS DISEL Transfer counter* counter* DTC transfer — Other than (1 → 0) — — — — Ends after the first transfer —...
Page 385 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Table 18.4 Transfer information write-back skip conditions and applicable registers MRA.SM[1:0] bits MRB.DM[1:0] bits SAR register DAR register Skip Skip Skip Write-back Write-back Skip Write-back Write-back 18.4.3 Normal Transfer Mode The normal transfer mode allows a 1-byte (8 bit), 1-halfword (16 bit), 1-word (32 bit) data transfer on a single activation source.
Page 386 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area Transfer 6 times Data 1 Data 1 (transfer 1 data per each event) Data 2 Data 2 Data 3 Data 3 Data 4 Data 4 Data 5 Data 5 Data 6...
Page 387 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area (set to repeat area) Transfer 8 times Data 1 Data 1 (transfer 1 data per each event) Data 2 Data 2 Data 3 Data 3 Data 4 Data 4 Data 1...
Page 388 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area (set to block area) First block Transfer Block area nth block Figure 18.7 Memory map of block transfer mode 18.4.6 Chain Transfer Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single activation source. If MRB.CHNE is set to 1 and CHNS to 0, an interrupt request to the CPU is not generated on completion of the specified number of rounds of transfer or by setting the MRB.DISEL bit to 1.
Page 389 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Writing 1 to the MRB.CHNE and CHNS bits enables chain transfer to be performed only after completion of the specified data transfer. In repeat transfer mode, chain transfer is performed after completion of the specified data transfer. For details on chain transfer conditions, see Table 18.3, Chain transfer conditions.
Page 390 S3A3 User’s Manual 18. Data Transfer Controller (DTC) System clock ICU.IELSRn.IR DTC activation request DTC access Data Data Vector read Transfer Transfer Transfer Transfer transfer transfer information read information information information write read write Figure 18.11 Example 3 of DTC operation timing for chain transfer System clock ICU.IELSRn.IR DTC activation request...
Page 391 S3A3 User’s Manual 18. Data Transfer Controller (DTC) 18.4.8 Execution Cycles of DTC Table 18.8 lists the execution cycles of single data transfer of the DTC. For the order of the execution states, see section 18.4.7, Operation Timing. Table 18.8 Execution cycles of DTC Data transfer Transfer...
Page 392 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Start Set the ICU.IELSRn.IELS[7:0] bit to 0 to disable the interrupt in the NVIC and provide the following settings: [1] Set the DTCCR.RRS bit to 0 to reset the transfer Set the DTCCR.RRS bit to 0 information read skip flag.
Page 393 S3A3 User’s Manual 18. Data Transfer Controller (DTC) address of the SRAM area for data storage in the DAR register, and 128 (0080h) in the CRA register. The CRB register can be set to any value. (2) DTC vector table settings The start address of the transfer information for the RXI interrupt is set in the vector table for the DTC.
Page 394 S3A3 User’s Manual 18. Data Transfer Controller (DTC) 3. In the MRB register, select the destination address as fixed (MRB.DM[1:0] bits = 00b) and set up chain transfer (MRB.CHNE bit = 1 and MRB.CHNS bit = 0). 4. Set the SAR register to the first address of the data table. 5.
Page 395 S3A3 User’s Manual 18. Data Transfer Controller (DTC) the handling routine. 18.6.3 Chain Transfer when Counter = 0 The second data transfer is performed only when the transfer counter is set to 0 in the first data transfer, and the first data transfer information is repeatedly changed in the second transfer.
Page 396 S3A3 User’s Manual 18. Data Transfer Controller (DTC) Input circuit Transfer information allocated in the on-chip memory space Input buffer First data transfer Transfer information Chain transfer (counter = 0) Second data transfer Transfer information Upper 8 bits of DAR Figure 18.14 Chain transfer when counter = 0 18.7...
Page 397 S3A3 User’s Manual 18. Data Transfer Controller (DTC) (1) Module-stop function Writing 1 to the MSTPCRA.MSTPA22 bit enables the module-stop function of the DTC. If the DTC transfer is in progress at the time, 1 is written to the MSTPCRA.MSTPA22 bit. The transition to the module-stop state proceeds after DTC transfer ends.
Page 398 S3A3 User’s Manual 19. Event Link Controller (ELC) Event Link Controller (ELC) 19.1 Overview The Event Link Controller (ELC) uses the event requests generated by various peripheral modules as source signals to connect them to different modules, allowing direct link between the modules without CPU intervention. Table 19.1 lists the ELC specifications and Figure 19.1...
Page 399 S3A3 User’s Manual 19. Event Link Controller (ELC) 19.2 Register Descriptions 19.2.1 Event Link Controller Register (ELCR) Address(es): ELC.ELCR 4004 1000h ELCON — — — — — — — Value after reset: Symbol Bit name Description b6 to b0 — Reserved These bits are read as 0.
Page 400 S3A3 User’s Manual 19. Event Link Controller (ELC) 19.2.3 Event Link Setting Register n (ELSRn) (n = 0 to 9, 12, 14 to 18) Address(es): ELC.ELSR0 4004 1010h, ELC.ELSR1 4004 1014h, ELC.ELSR2 4004 1018h, ELC.ELSR3 4004 101Ch, ELC.ELSR4 4004 1020h, ELC.ELSR5 4004 1024h, ELC.ELSR6 4004...
Page 401 S3A3 User’s Manual 19. Event Link Controller (ELC) Table 19.3 Association between event signal names set in ELSRn.ELS bits and signal numbers (1 of 5) Event number Interrupt request source Name Description 001h Port PORT_IRQ0* External pin interrupt 0 002h PORT_IRQ1* External pin interrupt 1 003h...
Page 402 S3A3 User’s Manual 19. Event Link Controller (ELC) Table 19.3 Association between event signal names set in ELSRn.ELS bits and signal numbers (2 of 5) Event number Interrupt request source Name Description 03Ah IIC1 IIC1_RXI Receive data full 03Bh IIC1_TXI Transmit data empty 03Ch IIC1_TEI...
Page 403 S3A3 User’s Manual 19. Event Link Controller (ELC) Table 19.3 Association between event signal names set in ELSRn.ELS bits and signal numbers (3 of 5) Event number Interrupt request source Name Description 073h GPT323 GPT3_CCMPA Compare match A 074h GPT3_CCMPB Compare match B 075h GPT3_CMPC...
Page 404 S3A3 User’s Manual 19. Event Link Controller (ELC) Table 19.3 Association between event signal names set in ELSRn.ELS bits and signal numbers (4 of 5) Event number Interrupt request source Name Description 09Bh GPT168 GPT8_CCMPA Compare match A 09Ch GPT8_CCMPB Compare match B 09Dh GPT8_CMPC...
Page 405 S3A3 User’s Manual 19. Event Link Controller (ELC) Table 19.3 Association between event signal names set in ELSRn.ELS bits and signal numbers (5 of 5) Event number Interrupt request source Name Description 0C6h SCI9 SCI9_RXI* Receive data full 0C7h SCI9_TXI* Transmit data empty 0C8h SCI9_TEI...
Page 406 S3A3 User’s Manual 19. Event Link Controller (ELC) 19.3.3 Example of Procedure for Linking Events To link events: 1. Set the operation of the module for which an event is to be linked. 2. Set the appropriate ELSRn register for the module to be linked. 3.
Page 407 S3A3 User’s Manual 19. Event Link Controller (ELC) Table 19.5 ELC delay time Clock domain Clock frequency ELC delay time clock_A = clock_B clock_A = clock_B 0 cycle clock_A  clock_B clock_A = clock_B 1 cycle to 2 cycles clock_A > clock_B 1 cycle to 2 cycles of B clock_A <...
Page 408 S3A3 User’s Manual 20. I/O Ports I/O Ports 20.1 Overview The I/O port pins operate as general I/O port pins, I/O pins for peripheral modules, interrupt input pins, analog I/O, port group function for ELC, or bus control pins. All pins operate as input pins immediately after a reset, and pin functions are switched by register settings.
Page 409 S3A3 User’s Manual 20. I/O Ports Table 20.1 I/O port specifications (2 of 2) Package Package Package Package 144 pins, Number Number Number Number Port 145 pins of pins 121 pins of pins 100 pins of pins 64 pins of pins PORT2 P200 to P200 to P206,...
Page 410 S3A3 User’s Manual 20. I/O Ports 20.2 Register Descriptions 20.2.1 Port Control Register 1 (PCNTR1/PODR/PDR) Address(es): PORT0.PCNTR1 4004 0000h, PORT1.PCNTR1 4004 0020h, PORT2.PCNTR1 4004 0040h, PORT3.PCNTR1 4004 0060h, PORT4.PCNTR1 4004 0080h, PORT5.PCNTR1 4004 00A0h, PORT6.PCNTR1 4004 00C0h, PORT7.PCNTR1 4004 00E0h, PORT8.PCNTR1 4004 0100h, PORT9.PCNTR1 4004...
Page 411 S3A3 User’s Manual 20. I/O Ports 20.2.2 Port Control Register 2 (PCNTR2/EIDR/PIDR) Address(es): PORT0.PCNTR2 4004 0004h, PORT1.PCNTR2 4004 0024h, PORT2.PCNTR2 4004 0044h, PORT3.PCNTR2 4004 0064h, PORT4.PCNTR2 4004 0084h, PORT5.PCNTR2 4004 00A4h, PORT6.PCNTR2 4004 00C4h, PORT7.PCNTR2 4004 00E4h, PORT8.PCNTR2 4004 0104h, PORT9.PCNTR2 4004 0124h, PORT1.EIDR 4004...
Page 412 S3A3 User’s Manual 20. I/O Ports 20.2.3 Port Control Register 3 (PCNTR3/PORR/POSR) Address(es): PORT0.PCNTR3 4004 0008h, PORT1.PCNTR3 4004 0028h, PORT2.PCNTR3 4004 0048h, PORT3.PCNTR3 4004 0068h, PORT4.PCNTR3 4004 0088h, PORT5.PCNTR3 4004 00A8h, PORT6.PCNTR3 4004 00C8h, PORT7.PCNTR3 4004 00E8h, PORT8.PCNTR3 4004 0108h, PORT9.PCNTR3 4004 0128h, PORT0.PORR 4004...
Page 413 S3A3 User’s Manual 20. I/O Ports 20.2.4 Port Control Register 4 (PCNTR4/EORR/EOSR) Address(es): PORT1.PCNTR4 4004 002Ch, PORT2.PCNTR4 4004 004Ch, PORT3.PCNTR4 4004 006Ch, PORT4.PCNTR4 4004 008Ch, PORT1.EORR 4004 002Ch, PORT2.EORR 4004 004Ch, PORT3.EORR 4004 006Ch, PORT4.EORR 4004 008Ch, PORT1.EOSR 4004 002Eh, PORT2.EOSR 4004 004Eh, PORT3.EOSR 4004...
Page 414 S3A3 User’s Manual 20. I/O Ports 20.2.5 Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY) (m = 0 to 9; n = 00 to 15) Address(es): PFS.P000PFS 4004 0800h PFS.P015PFS 4004 083Ch, PFS.P100PFS 4004 0840h PFS.P115PFS 4004 087Ch, PFS.P200PFS 4004 0880h PFS.P206PFS 4004 0898h, PFS.P212PFS 4004 08B0h...
Page 415 S3A3 User’s Manual 20. I/O Ports Symbol Bit name Description b13, b12 EOF/EOR Event on Falling/Event on b13 b12 0 0: Don’t care Rising 0 1: Detect rising edge 1 0: Detect falling edge 1 1: Detect both edges. ISEL IRQ Input Enable 0: Not used as an IRQn input pin 1: Used as an IRQn input pin.
Page 416 S3A3 User’s Manual 20. I/O Ports The PSEL[4:0] bits assign the peripheral function. For details of the peripheral settings for each product, see section 20.6, Peripheral Select Settings for each Product. 20.2.6 Write-Protect Register (PWPR) Address(es): PMISC.PWPR 4004 0D03h B0WI PFSWE —...
Page 417 S3A3 User’s Manual 20. I/O Ports Each pin is associated with a Pin Function Select Register (PmnPFS), which includes the associated PODR, PIDR, and PDR bits. In addition, the PmnPFS register includes the following:  PCR: Pull-up resistor control bit that turns the input pull-up MOS on or off ...
Page 418 S3A3 User’s Manual 20. I/O Ports EOSR PODR EORR ELC_PORT1, 2, 3, or 4 Figure 20.3 Event ports output data 20.3.3.2 Behavior when an event pulse is output to the ELC To output the event pulse from the external pins to the ELC, set the EOR/EOF bits in the PmnPFS register. For details, section 20.2.5, Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY) (m = 0 to 9;...
Page 419 S3A3 User’s Manual 20. I/O Ports 20.4 Handling of Unused Pins Table 20.3 shows how to handle unused pins. Table 20.3 Handling of unused pins Pin name Description P201/MD Use as a mode pin Connect to VCC through a resistor (pulling up) USB_DP, USB_DM When both P914PFS.PMR and P915PFS.PMR bits are set to 1, keep these pins open.
Page 420 S3A3 User’s Manual 20. I/O Ports 20.5.3 Port Output Data Register (PODR) Summary This register outputs data as follows: 1. Output 0 if PCNTR4.EORRn is set to 1 when an ELC_PORT1, 2, 3, or 4 signal occurs. 2. Output 1 if the PCNTR4.EOSRn is set to 1 when an ELC_PORT1, 2, 3, or 4 signal occurs. 3.
Page 421 S3A3 User’s Manual 20. I/O Ports 20.5.7 Pull-up/Pull-down Setting for P914 and P915 using USBFS/GPIO Function When P914 and P915 are used as GPIO pins, their operation is affected by the pull-up/pull-down function of the USBFS registers. Therefore, before using the GPIO function, disable the pull-up and pull-down control of the USBFS registers using the SYSCFG.DMRPU, SYSCFG.DPRPU, and SYSCFG.DRPD bits.
Page 422 S3A3 User’s Manual 20. I/O Ports Table 20.6 Register settings for I/O pin functions (PORT1) (1) PSEL[4:0] bit settings Function P100 P101 P102 P103 P104 P105 P106 P107 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00001b AGTIO0 AGTEE0 AGTO0 ― ― ―...
Page 423 S3A3 User’s Manual 20. I/O Ports Table 20.7 Register settings for I/O pin functions (PORT1) (2) PSEL[4:0] bit settings Function P108 P109 P110 P111 P112 P113 P114 P115 00000b (value Hi-Z/JTAG/SWD TMS/ TDO/ Hi-Z after reset) SWDIO TRACESWO 00001b ― ―...
Page 424 S3A3 User’s Manual 20. I/O Ports Table 20.8 Register settings for I/O pin functions (PORT2) (1) PSEL[4:0] bit settings Function P200 P201 P202 P203 P204 P205 P206 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00001b ― ― ― ― AGTIO1 AGTO1 ―...
Page 425 S3A3 User’s Manual 20. I/O Ports Table 20.9 Register settings for I/O pin functions (PORT2) (2) PSEL[4:0] bit settings Function P212 P213 P214 P215 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00001b AGTEE1 ― ― ― 00010b GTETRGB GTETRGA ― ― 00011b GTIOC0B GTIOC0A...
Page 426 S3A3 User’s Manual 20. I/O Ports Table 20.10 Register settings for I/O pin functions (PORT3) PSEL[4:0] bit settings Function P300 P301 P302 P303 P304 P305 P306 P307 00000b (value Hi-Z/JTAG/SWD TCK/ Hi-Z after reset) SWCLK 00001b ― AGTIO0 ― ― ―...
Page 427 S3A3 User’s Manual 20. I/O Ports —: Setting prohibited Table 20.11 Register settings for I/O pin functions (PORT4) (1) PSEL[4:0] bit settings Function P400 P401 P402 P403 P404 P405 P406 P407 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00001b AGTIO1 ― AGTIO0* AGTIO0* ―...
Page 428 S3A3 User’s Manual 20. I/O Ports Table 20.12 Register settings for I/O pin functions (PORT4) (2) PSEL[4:0] bit settings Function P408 P409 P410 P411 P412 P413 P414 P415 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00001b ― ― AGTOB1 AGTOA1 ― ―...
Page 429 S3A3 User’s Manual 20. I/O Ports Table 20.13 Register settings for I/O pin functions (PORT5) PSEL[4:0] bit settings Function P500 P501 P502 P503 P504 P505 P506 P507 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00001b AGTOA0 AGTOB0 ― ― ― ― ―...
Page 430 S3A3 User’s Manual 20. I/O Ports  : Available —: Setting prohibited Table 20.14 Register settings for I/O pin functions (PORT6) PSEL[4:0] bit settings Function P600 P601 P602 P603 P604 P605 P606 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00011b GTIOC6B GTIOC6A GTIOC7B GTIOC7A...
Page 431 S3A3 User’s Manual 20. I/O Ports Table 20.15 Register settings for I/O pin functions (PORT7) PSEL[4:0] bit settings Function P700 P701 P702 P703 P704 P705 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00001b ― ― ― ― AGTO0 AGTIO0 00011b GTIOC5A GTIOC5B GTIOC6A GTIOC6B...
Page 432 S3A3 User’s Manual 20. I/O Ports Table 20.16 Register settings for I/O pin functions (PORT8) PSEL[4:0] bit settings Function P800 P801 P802 P803 P804 P805 P806 P807 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00011b ― ― ― ― GTIOC9B GTIOC9A ―...
Page 433 S3A3 User’s Manual 20. I/O Ports Table 20.17 Register settings for I/O pin functions (PORT9) PSEL[4:0] bit settings Function P900 P901 P902 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00001b ― AGTIO1 AGTO1 00100b TXD4/ SCK4 CTS4_RTS4/ MOSI4/ SDA4 01011b ― ―...
Page 434 S3A3 User’s Manual 21. Key Interrupt Function (KINT) Key Interrupt Function (KINT) 21.1 Overview A key interrupt (KEY_INTKR) can be generated by setting the Key Return Mode register (KRM) and inputting a rising or falling edge to the key interrupt input pins, KR00 to KR07. Table 21.1 shows the assignment for key interrupt detection, Table 21.2...
Page 435 S3A3 User’s Manual 21. Key Interrupt Function (KINT) Filter KR00 KRF0 KREG KRM0 KRMD Filter KR01 KRF1 KREG KRM1 KRMD Filter KR02 KRF2 KREG KRM2 KRMD Filter KR03 KRF3 KREG KRM3 KRMD KEY_INTKR Filter KR04 KRF4 KEY_INTKR mask signal KREG KRM4 KRMD Filter...
Page 436 S3A3 User’s Manual 21. Key Interrupt Function (KINT) 21.2 Register Descriptions 21.2.1 Key Return Control Register (KRCTL) Address(es): KINT.KRCTL 4008 0000h KRMD — — — — — — KREG Value after reset: Symbol Bit name Description KREG Selection of Detection Edge 0: Falling edge (KR00 to KR07) 1: Rising edge.
Page 437 S3A3 User’s Manual 21. Key Interrupt Function (KINT) Note: The on-chip pull-up resistors can be applied by setting the associated key interrupt input pin in the pull-up resistor. For details, section 20, I/O Ports. Key interrupts can be assigned in the PmnPFS.PSEL bits. For more information, see section 20, I/O Ports.
Page 438 S3A3 User’s Manual 21. Key Interrupt Function (KINT) the key interrupt (KEY_INTKR) is generated. If the KRMD bit is set to 1, clear the KEY_INTKR signal by clearing the associated bit in the KRF register. Figure 21.4 shows, only one interrupt is generated each time a falling edge is input to one channel, that is, when KREG = 0, regardless of whether the KRFn bit is cleared before or after a rising edge is input.
Page 439 S3A3 User’s Manual 21. Key Interrupt Function (KINT) KR00 KR01 KR05 KRF0 Cleared by software Delay time KRF1 Cleared by software Delay time KRF5 Cleared by software Delay time KEY_INTKR Key interrupt Key interrupt Key interrupt When KRMD = 1 and KREG = 0 Figure 21.5 Operation of KEY_INTKR signal when key interrupts are input to multiple channels 21.4...
Page 440 S3A3 User’s Manual 22. Port Output Enable for GPT (POEG) Port Output Enable for GPT (POEG) 22.1 Overview The Port Output Enable (POEG) can place the General PWM Timer (GPT) output pins in the output-disable state in one of the following ways: ...
Page 441 S3A3 User’s Manual 22. Port Output Enable for GPT (POEG) Group B POEG Group A IOCF IOCE Ch 0 POEG_GROUP0 POEG_GROUP1 Group A Ch 0 GTINTAD.GRPABH, GTINTAD.GRPABL Group B Ch 9 Ch 1 Ch 9 OPSCR. GTOUUP Comparator detect GRP[1:0], GTOULO OPSCR.
Page 442 S3A3 User’s Manual 22. Port Output Enable for GPT (POEG) Symbol Bit name Description IOCF Output-disable Request 0: No output-disable request from the GPT disable request R(/W)* Detection Flag from GPT occurred 1: Output-disable request from the GPT disable request occurred. OSTPF Oscillation Stop Detection 0: No output-disable request from oscillation stop detection...
Page 443 S3A3 User’s Manual 22. Port Output Enable for GPT (POEG) 22.3.1 Pin Input Level Detection Operation If the input conditions set by POEGGn.PIDE, POEGGn.NFCS[1:0], POEGGn.NFEN, and POEGGn.INV occur on the GTETRGA and GTETRGB pins, the GPT output pins are output-disabled. 22.3.1.1 Digital filter Figure 22.2...
Page 444 S3A3 User’s Manual 22. Port Output Enable for GPT (POEG) flags in GPT are set to 0. Writing 0 to the POEGGn.OSTPF flag is ignored (the flag is not cleared) if the OSTDSR.OSTDF flag in the clock generation circuit is not set to 0. In addition, when the flag set and release occur at the same time, the flag set takes precedence.
Page 445 S3A3 User’s Manual 22. Port Output Enable for GPT (POEG)  Down-count  Input capture. For the POEGG.INV polarity setting signal, when the same level is input three times continuously with the sampling clock selected in the POEGGn.NFCS[1:0] and POEGGn.NFEN bits, that value is output. Set the control registers the same as for the input level detection operation described in section 22.3.1, Pin Input Level Detection Operation.
Page 446 S3A3 User’s Manual 23. General PWM Timer (GPT) General PWM Timer (GPT) 23.1 Overview The General PWM Timer (GPT) is a 32-bit timer with four GPT32 channels, and a 16-bit timer with six GPT16 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms can be generated for controlling brushless DC motors.
Page 447 S3A3 User’s Manual 23. General PWM Timer (GPT) Table 23.2 GPT functions Parameter GPT32, GPT16 Count clock PCLKD PCLKD/4 PCLKD/16 PCLKD/64 PCLKD/256 PCLKD/1024 Output compare/input capture registers (GTCCR) GTCCRA GTCCRB Compare/buffer registers GTCCRC GTCCRD GTCCRE GTCCRF Cycle setting register GTPR Cycle setting buffer registers GTPBR I/O pins...
Page 448 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320 Control registers Interrupt request signals GPT321 GPT0_CCMPA GTWP GTICASR GTDTCR GPT322 GPT0_CCMPB GTSTR GTICBSR GTDVU Clock source GPT323 GPT0_CMPC GTSTP GTCR PCLKD GPT0_CMPD GPT164 GTCLR GTUDDTYC PCLKD/4 Cycle setting/ GPT0_CMPE GTSSR GTIOR GPT165 PCLKD/16...
Page 449 S3A3 User’s Manual 23. General PWM Timer (GPT) Table 23.3 lists the I/O pins used in the GPT. Table 23.3 GPT I/O pins Channel Pin name Function Shared GTETRGA Input External trigger input pin A (after noise filtering) GTETRGB Input External trigger input pin B (after noise filtering) GPT320 GTIOC0A...
Page 450 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.2 Register Descriptions Table 23.4 lists the registers in the GPT. Table 23.4 GPT registers Module Register Access symbol Register name symbol Reset value Address size GPT32m* General PWM Timer Write Protection Register GTWP 00000000h 4007 8000h + 0100h ×...
Page 451 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.2.1 General PWM Timer Write-Protection Register (GTWP) Address(es): GPT32m.GTWP 4007 8000h + 0100h × m (m = 0 to 3), GPT16m.GTWP 4007 8000h + 0100h × m (m = 4 to 9) —...
Page 452 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.2.3 General PWM Timer Software Stop Register (GTSTP) Address(es): GPT32m.GTSTP 4007 8008h + 0100h × m (m = 0 to 3), GPT16m.GTSTP 4007 8008h + 0100h × m (m = 4 to 9) —...
Page 453 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.2.5 General PWM Timer Start Source Select Register (GTSSR) Address(es): GPT32m.GTSSR 4007 8010h + 0100h × m (m = 0 to 3), GPT16m.GTSSR 4007 8010h + 0100h × m (m = 4 to 9) SSELC SSELC SSELC...
Page 454 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description SSCBFAL GTIOCB Pin Falling Input during 0: Counter start disabled on the falling edge of GTIOCB GTIOCA Value Low Source input when GTIOCA input is 0 Counter Start Enable 1: Counter start enabled on the falling edge of GTIOCB input when GTIOCA input is 0.
Page 455 S3A3 User’s Manual 23. General PWM Timer (GPT) SSCAFBH (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable) The SSCAFBH bit enables or disables the GTCNT counter start on the falling edge of GTIOCA pin input, when GTIOCB input is 1.
Page 456 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description PSGTRGBF GTETRGB Pin Falling Input Source 0: Counter stop disabled on the falling edge of GTETRGB Counter Stop Enable input 1: Counter stop enabled on the falling edge of GTETRGB input.
Page 457 S3A3 User’s Manual 23. General PWM Timer (GPT) PSGTRGAR (GTETRGA Pin Rising Input Source Counter Stop Enable) The PSGTRGAR bit enables or disables the GTCNT counter stop on the rising edge of GTETRGA pin input. PSGTRGAF (GTETRGA Pin Falling Input Source Counter Stop Enable) The PSGTRGAF bit enables or disables the GTCNT counter stop on the falling edge of GTETRGA pin input.
Page 458 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.2.7 General PWM Timer Clear Source Select Register (GTCSR) Address(es): GPT32m.GTCSR 4007 8018h + 0100h × m (m = 0 to 3), GPT16m.GTCSR 4007 8018h + 0100h × m (m = 4 to 9) CSELC CSELC CSELC...
Page 459 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description CSCBFAL GTIOCB Pin Falling Input during 0: Counter clear disabled on the falling edge of GTIOCB GTIOCA Value Low Source input when GTIOCA input is 0 Counter Clear Enable 1: Counter clear enabled on the falling edge of GTIOCB input when GTIOCA input is 0.
Page 460 S3A3 User’s Manual 23. General PWM Timer (GPT) CSCAFBH (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable) The CSCAFBH bit enables or disables GTCNT counter clear on the falling edge of GTIOCA pin input, when GTIOCB input is 1.
Page 461 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description USGTRGBF GTETRGB Pin Falling Input Source 0: Counter count up disabled on the falling edge of Counter Count Up Enable GTETRGB input 1: Counter count up enabled on the falling edge of GTETRGB input.
Page 462 S3A3 User’s Manual 23. General PWM Timer (GPT) USGTRGAR (GTETRGA Pin Rising Input Source Counter Count Up Enable) The USGTRGAR bit enables or disables the GTCNT counter count up on the rising edge of GTETRGA pin input. USGTRGAF (GTETRGA Pin Falling Input Source Counter Count Up Enable) The USGTRGAF bit enables or disables the GTCNT counter count up on the falling edge of GTETRGA pin input.
Page 463 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.2.9 General PWM Timer Down Count Source Select Register (GTDNSR) Address(es): GPT32m.GTDNSR 4007 8020h + 0100h × m (m = 0 to 3), GPT16m.GTDNSR 4007 8020h + 0100h × m (m = 4 to 9) DSELC DSELC DSELC...
Page 464 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description DSCBFAL GTIOCB Pin Falling Input during 0: Counter count down disabled on the falling edge of GTIOCA Value Low Source GTIOCB input when GTIOCA input is 0 Counter Count Down Enable 1: Counter count down enabled on the falling edge of GTIOCB input when GTIOCA input is 0.
Page 465 S3A3 User’s Manual 23. General PWM Timer (GPT) GTIOCB input is 0. DSCAFBH (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable) The DSCAFBH bit enables or disables the GTCNT counter count down on the falling edge of GTIOCA pin input, when GTIOCB input is 1.
Page 466 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description ASGTRGBR GTETRGB Pin Rising Input Source 0: GTCCRA input capture disabled on the rising edge of GTCCRA Input Capture Enable GTETRGB input 1: GTCCRA input capture enabled on the rising edge of GTETRGB input.
Page 467 S3A3 User’s Manual 23. General PWM Timer (GPT) The GTICASR sets the source of input capture for GTCCRA. ASGTRGAR (GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable) The ASGTRGAR bit enables or disables input capture for GTCCRA on the rising edge of GTETRGA pin input. ASGTRGAF (GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable)
Page 468 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.2.11 General PWM Timer Input Capture Source Select Register B(GTICBSR) Address(es): GPT32m.GTICBSR 4007 8028h + 0100h × m (m = 0 to 3), GPT16m.GTICBSR 4007 8028h + 0100h × m (m = 4 to 9) BSELC BSELC BSELC...
Page 469 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description BSCBFAL GTIOCB Pin Falling Input during 0: GTCCRB input capture disabled on the falling edge of GTIOCA Value Low Source GTIOCB input when GTIOCA input is 0 GTCCRB Input Capture Enable 1: GTCCRB input capture enabled on the falling edge of GTIOCB input when GTIOCA input is 0.
Page 470 S3A3 User’s Manual 23. General PWM Timer (GPT) BSCAFBH (GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable) The BSCAFBH bit enables or disables input capture for GTCCRB on the falling edge of GTIOCA pin input, when GTIOCB input is 1.
Page 471 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description b18 to b16 MD[2:0] Mode Select 0 0 0: Saw-wave PWM mode (single buffer or double buffer possible) 0 0 1: Saw-wave one-shot pulse mode (fixed buffer operation) 0 1 0: Setting prohibited 0 1 1: Setting prohibited 1 0 0: Triangle-wave PWM mode 1 (32-bit transfer at...
Page 472 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.2.13 General PWM Timer Count Direction and Duty Setting Register (GTUDDTYC) Address(es): GPT32m.GTUDDTYC 4007 8030h + 0100h × m (m = 0 to 3), GPT16m.GTUDDTYC 4007 8030h + 0100h × m (m = 4 to 9) OBDTY OBDTY OADTY...
Page 473 S3A3 User’s Manual 23. General PWM Timer (GPT) becomes GTPR value). When the UD value changes from 0 to 1 with the UDF bit being 0 and while counting stops, the counter starts down-counting and the count direction changes at an underflow (the timing synchronous with count clock after GTCNT value becomes 0).
Page 474 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.2.14 General PWM Timer I/O Control Register (GTIOR) Address(es): GPT32m.GTIOR 4007 8034h + 0100h × m (m = 0 to 3), GPT16m.GTIOR 4007 8034h + 0100h × m (m = 4 to 9) OBHLD OBDFL NFCSB[1:0] NFBEN...
Page 475 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description b31, b30 NFCSB[1:0] Noise Filter B Sampling Clock b31 b30 0 0: PCLKD/1 Select 0 1: PCLKD/4 1 0: PCLKD/16 1 1: PCLKD/64. The GTIOR sets the functions of the GTIOCA and GTIOCB pins. GTIOA[4:0] bits (GTIOCA Pin Function...
Page 476 S3A3 User’s Manual 23. General PWM Timer (GPT)  The value specified in bit [4] of the GTIOB[4:0] bits is output when counting starts  The value specified in the OBDFLT bit is output when counting stops  If the OBDFLT bit is modified while counting stops, the new value is immediately reflected in the output. When the OBHLD bit is set to 1: ...
Page 477 S3A3 User’s Manual 23. General PWM Timer (GPT) Table 23.5 Settings of GTIOA[4:0] and GTIOB[4:0] bits (2 of 2) GTIOA/GTIOB[4:0] bits Function b3, b2* b1, b0* Initial output is high Output retained at Output retained at GTCCRA/GTCCRB compare match cycle end Low output at GTCCRA/GTCCRB compare match High output at GTCCRA/GTCCRB compare match Output toggled at GTCCRA/GTCCRB compare match...
Page 478 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description GRPABH Same Time Output Level High Disable 0: Same time output level high disable request Request Enable disabled 1: Same time output level high disable request enabled. GRPABL Same Time Output Level Low Disable 0: Same time output level low disable request Request Enable...
Page 479 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description TCFF Input Compare Match Flag F 0: No compare match of GTCCRF is generated R/(W)* 1: A compare match of GTCCRF is generated. TCFPO Overflow Flag 0: No overflow (crest) occurred R/(W)* 1: An overflow (crest) occurred.
Page 480 S3A3 User’s Manual 23. General PWM Timer (GPT)  GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)  GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)  GTBER.CCRA[1:0] = 01b, 10b, 11b (GTCCRC performs buffer operation). TCFD flag (Input Compare Match Flag TCFD is the status flag for the compare match of GTCCRD.
Page 481 S3A3 User’s Manual 23. General PWM Timer (GPT)  In counting by hardware sources, an overflow (GTCNT changes from GTPR to 0 in up-counting) has occurred. [Clearing condition]  0 is written to this flag. TCFPU flag (Underflow Flag) The TCFPU flag indicates when an underflow or a trough has occurred. [Setting conditions] ...
Page 482 S3A3 User’s Manual 23. General PWM Timer (GPT)  The GTIOCA and GTIOCB pins output 1 at the same time when both OAE and OBE bits are set to 1  Either the OAE bit or the OBE bit is set to 0. The compare-target signals to generate the OABHF/OABLF flag are the compare match outputs (PWM outputs) signals before they are masked by the output disable function.
Page 483 S3A3 User’s Manual 23. General PWM Timer (GPT) CCRA[1:0] bits (GTCCRA Buffer Operation) The CCRA[1:0] bits set buffer operation using GTCCRA, GTCCRC, and GTCCRD combined. When buffer operation is restricted by the operating mode set in GTCR, the GTCR setting is given priority. CCRB[1:0] bits (GTCCRB Buffer...
Page 484 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.2.19 General PWM Timer Compare Capture Register n (GTCCRn) (n = A to F) Address(es): GPT32m.GTCCRA 4007 804Ch + 0100h × m (m = 0 to 3), GPT16m.GTCCRA 4007 804Ch + 0100h × m (m = 4 to 9), GPT32m.GTCCRB 4007 8050h + 0100h ×...
Page 485 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.2.21 General PWM Timer Cycle Setting Buffer Register (GTPBR) Address(es): GPT32m.GTPBR 4007 8068h + 0100h × m (m = 0 to 3), GPT16m.GTPBR 4007 8068h + 0100h × m (m = 4 to 9) Value after reset: Value after reset: Note 1.
Page 486 S3A3 User’s Manual 23. General PWM Timer (GPT) Lower limit value: 0. 23.2.23 General PWM Timer Dead Time Value Register U (GTDVU) Address(es): GPT32m.GTDVU 4007 808Ch + 0100h x m (m = 0 to 3), GPT16m.GTDVU 4007 808Ch + 0100h x m (m = 4 to 9) Value after reset: Value after reset: Note 1.
Page 487 S3A3 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description External Feedback Signal Enable This bit selects the input phase from software settings and external input: 0: Select the external input 1: Select the soft setting (OPSCR.UF, VF, WF). Positive-Phase Output (P) Control 0: Level signal output 1: PWM signal output (PWM of GPT320).
Page 488 S3A3 User’s Manual 23. General PWM Timer (GPT) (GTOUUP pin, GTOVUP pin, GTOWUP pin). (Negative-Phase Output (N) Control) The N bit selects one of the level signal output (PWM of GPT320) or PWM signal output for the negative-phase output (GTOULO pin, GTOVLO pin, GTOWLO pin). (Invert-Phase Output Control) The INV bit selects one of the positive logic (active-high) output or negative logic (active-low) output for the output...
Page 489 S3A3 User’s Manual 23. General PWM Timer (GPT)  Writing to GTCR register  Writing 1 to the bit in GTSTR associated with the GPT channel number when the GTSSR.CSTRT bit is set to 1  Writing 1 to the bit in GTSTP associated with the GPT channel number when the GTPSR.CSTOP bit is set to 1 ...
Page 490 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.3, 000b (saw-wave PWM mode) is set.) Set count direction Select the count direction with the GTUDDTYC register. Figure 23.3, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Page 491 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.5, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction with the GTUDDTYC register. Figure 23.5, after 10b is set in GTUDDTYC[1:0], 00b is set in GTUDDTYC[1:0] (down-counting).
Page 492 S3A3 User’s Manual 23. General PWM Timer (GPT) PCLKD GTETRGA N + 1 GTCNT Figure 23.7 Example of periodic count operation in up-counting using hardware sources Figure 23.8 shows an example for setting periodic count operation in down-counting by the count clock. Set count source Select the counting-up source with the GTUPSR register.
Page 493 S3A3 User’s Manual 23. General PWM Timer (GPT) PCLKD GTETRGA N + 1 GTCNT Figure 23.9 Example of event count operation in down-counting using hardware sources Figure 23.10 shows an example for setting a periodic count operation in down-counting using a hardware resource. Set count source Select the counting-down source with the GTDNSR register.
Page 494 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.3.1.2 Waveform output by compare match Compare match means that the GTCNT counter value matches the value of GTCCRA or GTCCRB. When a compare match occurs, the compare match flag is generated synchronously with the count clock including the event count. At the same time the GPT can output low, high, or toggled output from the associated GTIOCA or GTIOCB output pin.
Page 495 S3A3 User’s Manual 23. General PWM Timer (GPT) Figure 23.12 shows an example for setting low output and high output operation. Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.11, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 496 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRB register GPT320.GTCCRA register 0000 0000h Time GTIOC0A pin output GTIOC0B pin output [Setting examples] GPT320.GTIOR.GTIOA[4:0] bits: Initial output is high, output toggled at compare match, output retained at cycle end GPT320.GTIOR.GTIOB[4:0] bits: Initial output is low, output toggled at compare match, output retained at cycle end Figure 23.13 Example of toggled output operation (1)
Page 497 S3A3 User’s Manual 23. General PWM Timer (GPT) Figure 23.15 shows an example setting for toggled output operation. Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.13 Figure 23.14, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 498 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register E400h C154h 9682h 1100h 0000 0000h Time GTIOC0A pin input GTIOC0B pin input GPT320.GTCCRA register 9682h E400h 1100h C154h GPT320.GTCCRB register [Setting examples] GTICASR setting input capture at both edges GTICBSR setting input capture at the rising edge Figure 23.16 Example of input capture operation...
Page 499 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.16, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register. Figure 23.16, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Page 500 S3A3 User’s Manual 23. General PWM Timer (GPT) GTCNT counter value cccc bbbb aaaa 0000 0000h Time Register write Register write Register write Register write GTPBR register bbbb cccc Buffer transfer Buffer transfer Buffer transfer at overflow at overflow at overflow GTPR register aaaa bbbb...
Page 501 S3A3 User’s Manual 23. General PWM Timer (GPT) GTCNT counter value cccc bbbb aaaa 0000 0000h Time GTPBR register aaaa bbbb cccc Buffer transfer at trough Buffer transfer at trough Buffer transfer at trough GTPR register aaaa bbbb cccc Figure 23.20 Example of GTPR buffer operation with triangle waves R01UM0006EU0110 Rev.1.10 Page 501 of 1618...
Page 502 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.18 Figure 23.19 000b (saw-wave PWM mode) is set, and in Figure 23.20 100b (triangle-wave PWM mode 1) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 503 S3A3 User’s Manual 23. General PWM Timer (GPT)  Buffer transfer by overflow or underflow Buffer transfer is performed at an overflow (during up-counting) or an underflow (during down-counting) in saw- wave mode or in event count operation. In triangle-wave mode, buffer transfer is performed at a trough (triangle- wave PWM mode 1) or a crest and trough (triangle-wave PWM mode 2).
Page 504 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register cccc bbbb aaaa 0000 0000h Time Register write Register write Register write GPT320.GTCCRD register cccc Buffer transfer at Buffer transfer at trough trough bbbb cccc GPT320.GTCCRC register Buffer transfer at Buffer transfer at trough...
Page 505 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.22, 000b (saw-wave PWM mode) is set, in Figure 23.23, 100b (triangle-wave PWM mode 1) is set, and in Figure 23.24, 101b (triangle-wave PWM mode 2) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 506 S3A3 User’s Manual 23. General PWM Timer (GPT) Figure 23.26 Figure 23.27 show examples of GTCCRA and GTCCRB buffer operation and Figure 23.28 shows an example for setting the GTCCRA and GTCCRB buffer operation. GPT320.GTCNT counter value GPT320.GTPR register cccc bbbb aaaa 0000 0000h...
Page 507 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0] and count clear source with GTCSR. Figure 23.26, MD[2:0] = 000b (saw-wave PWM mode) and GTCSR = 0000 0F00h, and in Figure 23.27, MD[2:0] = 000b (saw-wave PWM mode) and GTCSR = 0000 F000h. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 508 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register ffff eeee dddd cccc bbbb aaaa 0000 0000h Time Register write Register write Register write Register write GPT320.GTCCRC register cccc eeee Buffer transfer Buffer transfer Buffer transfer at overflow at overflow at overflow...
Page 509 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. In Figure 23.29, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register. Figure 23.29, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Page 510 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.3.3.2 Saw-wave one-shot pulse mode The saw-wave one-shot pulse mode is a mode in which the cycle is set in GTPR. The GTCNT counter performs saw- wave (half-wave) operation and a PWM waveform is output to the GTIOCA or GTIOCB pin at a compare match of GTCCRA or GTCCRB with buffer operation fixed.
Page 511 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register hhhh gggg ffff eeee dddd cccc bbbb aaaa 0000 0000h Time Register write Register write Register write GPT320.GTCCRD register eeee Buffer transfer Buffer transfer at overflow at overflow Temporary register A gggg eeee...
Page 512 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.31, 001b (saw-wave one-shot pulse mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register. Figure 23.31, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Page 513 S3A3 User’s Manual 23. General PWM Timer (GPT) low output, high output, or toggle output separately for a compare match and for the cycle end based on the GTIOR setting. By setting GTDTCR and GTDVU, a compare match value for a negative-phase waveform with dead time can automatically be set to GTCCRB.
Page 514 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.33, 100b (triangle-wave PWM mode 1) is set. Select count clock Select the count clock with GTCR.TPCS[2:0]. Set cycle Set the cycle in GTPR. Set initial value for counter Set the initial value in the GTCNT counter.
Page 515 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.3.3.4 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) Similar to triangle-wave PWM mode 1, in triangle-wave PWM mode 2 the cycle is set in GTPR. The GTCNT counter performs triangle-wave (full-wave) operation, and a PWM waveform is output to the GTIOCA or GTIOCB pin when a GTCCRA or GTCCRB compare match occurs.
Page 516 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.35, 101b (triangle-wave PWM mode 2) is set. Select count clock Select the count clock with GTCR.TPCS[2:0]. Set cycle Set the cycle in GTPR. Set initial value for counter Set the initial value in the GTCNT counter.
Page 517 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.3.3.5 Triangle-wave PWM mode 3 (64-bit transfer at trough) The triangle-wave PWM mode 3 is a mode in which the cycle is set in GTPR. The GTCNT counter performs triangle- wave (full-wave) operation and a PWM waveform is output to the GTIOCA or GTIOCB pin at a compare match of GTCCRA or GTCCRB with buffer operation fixed.
Page 518 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register hhhh gggg ffff eeee dddd cccc bbbb aaaa 0000 0000h Time Register write Register write GPT320.GTCCRD register hhhh Buffer transfer at trough Temporary register A ffff hhhh Register write Register write GPT320.GTCCRC register...
Page 519 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.37, 110b (triangle-wave PWM mode 3) is set. Select count clock Select the count clock with GTCR.TPCS[2:0]. Set cycle Set the cycle in GTPR. Set initial value for counter Set the initial value in the GTCNT counter.
Page 520 S3A3 User’s Manual 23. General PWM Timer (GPT) Figure 23.39 Figure 23.42 show examples of automatic dead time setting function operation. Figure 23.43 Figure 23.44 show the setting examples. GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRA register 0000 0000h Time Buffer transfer Buffer transfer Buffer transfer Buffer transfer...
Page 521 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRA register Time 0000 0000h Buffer transfer at trough Buffer transfer at trough GPT320.GTCCRA register GPT320.GTCCRB register GTCCRA - GTDVU GTCCRA - GTDVU (Automatic setting) GTIOC0A pin output GTDVU GTDVU GTDVU...
Page 522 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. In Figure 23.39 Figure 23.40, 001b (saw-wave one-shot pulse mode) is set. In Figure 23.42, 110b (triangle-wave PWM mode 3) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 523 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. In Figure 23.41, 100b (triangle-wave PWM mode 1) is set. In Figure 23.42, 101b (triangle-wave PWM mode 2) is set. Select count clock Select the count clock with GTCR.TPCS[2:0].
Page 524 S3A3 User’s Manual 23. General PWM Timer (GPT) and GTUDDTYC.UDF bit is 0, the GTUDDTYC.UD bit value is not reflected to the count operation. If the GTUDDTYC.UDF bit is set to 1 while the count operation is stopped, the GTUDDTYC.UD bit value at that time is reflected at the start of counting.
Page 525 S3A3 User’s Manual 23. General PWM Timer (GPT)  Output interrupt  Perform buffer operation. When the control is changed from 0% or 100% duty setting to compare match, the output value of GTIOCA pin at cycle end is determined by GTIOR.GTIOA[3:2] and GTUDDTYC.OADTYR. The output value of GTIOCB pin at cycle end is decided by GTIOR.GTIOB[3:2] and GTUDDTYC.OBDTYR.
Page 526 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register bbbb aaaa 0000 0000h Time Register write Register write Register write GTUDDTYC.OADTY GTIOC0A pin output GTIOC0B pin output 100% [Setting examples] GPT320.GTIOR.GTIOA[4:0] bits: 00011b Initial low output, output toggled at compare match, output retained at cycle end GPT320.GTUDDTYC.OADTYR bit: 0b Applied the value of duty 0% or 100% output to GTIOA[3:2] bits function after 0% or 100% duty setting is released...
Page 527 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.47, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register. Figure 23.47, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Page 528 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.49, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register. Figure 23.49, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Page 529 S3A3 User’s Manual 23. General PWM Timer (GPT) Count started on the rising Count stopped on the falling edge of GTETRGA edge of GTETRGA GTCNT counter value GTPR register Count started on the rising edge of GTETRGA 0000 0000h Time GTETRGA pin input Figure 23.51 Example of count start/stop operation by a hardware source started on the rising edge of...
Page 530 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.51, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register. Figure 23.51, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Page 531 S3A3 User’s Manual 23. General PWM Timer (GPT) GTCNT counter value Count stopped/cleared at ELC event input Clear by software (by writing 1 to corresponding channel number bit of GTCLR register) Count started at Count started at ELC event input ELC event input 0000 0000h Time...
Page 532 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.53 Figure 23.54, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register. Figure 23.53, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Page 533 S3A3 User’s Manual 23. General PWM Timer (GPT) GTCNT counter value Counter cleared Clear by software (by at overflow writing 1 to corresponding channel number bit of GTPR register GTCLR register) Counter cleared by hardware source 0000 0000h Time Hardware source counter clear signal GPTn_OVF (n = 0 to 9) interrupt request...
Page 534 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register 0000 0000h Time GPT321.GTCNT counter value GPT321.GTPR register 0000 0000h Time GPT322.GTCNT counter value GPT322.GTPR register 0000 0000h Time GPT323.GTCNT counter value GPT323.GTPR register Time 0000 0000h Write 0000 000Fh in Write 0000 000Fh in Write 0000 000Fh in...
Page 535 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register Set initial value cccc bbbb aaaa 0000 0000h Time GPT321.GTCNT counter value GPT321.GTPR register cccc Set initial value bbbb aaaa Time 0000 0000h GPT322.GTCNT counter value GPT322.GTPR register cccc bbbb Set initial value...
Page 536 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register 0000 0000h Time GPT321.GTCNT counter value GPT321.GTPR register 0000 0000h Time GPT322.GTCNT counter value GPT322.GTPR register 0000 0000h Time GPT323.GTCNT counter value GPT323.GTPR register Time 0000 0000h Count operation of channel Count operation of channel 0/1/2/3 started by...
Page 537 S3A3 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.59, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register. Figure 23.59, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Page 538 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRB register GPT320.GTCCRA register GPT321.GTCNT counter GPT321.GTPR register GPT321.GTCCRB register GPT321.GTCCRA register GPT322.GTCNT counter GPT322.GTPR register GPT322.GTCCRB register GPT322.GTCCRA register GPT323.GTCNT counter GPT323.GTPR register GPT323.GTCCRB register GPT323.GTCCRA register GTIOC0A pin output GTIOC0B pin output GTIOC1A pin output...
Page 539 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRA register = GPT320.GTCCRB register GPT321.GTCNT counter GPT321.GTPR register GPT321.GTCCRA register = GPT321.GTCCRB register GPT322.GTCNT counter GPT322.GTPR register GPT322.GTCCRA register = GPT322.GTCCRB register GTIOC0A pin output GTIOC0B pin output GTIOC1A pin output GTIOC1B pin output GTIOC2B pin output...
Page 540 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRD register GPT320.GTCCRC register GPT321.GTCNT counter GPT321.GTPR register GPT321.GTCCRD register GPT321.GTCCRC register GPT322.GTCNT counter GPT322.GTPR register GPT322.GTCCRD register GPT322.GTCCRC register GTIOC0A pin output GTIOC0B pin output GPT320.GTDVU GPT320.GTDVU GTIOC1A pin output GTIOC1B pin output GPT321.GTDVU...
Page 541 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRA register GPT320.GTCCRB register GPT321.GTCNT counter GPT321.GTPR register GPT321.GTCCRA register GPT321.GTCCRB register GPT322.GTCNT counter GPT322.GTPR register GPT322.GTCCRA register GPT322.GTCCRB register GTIOC0A pin output GTIOC0B pin output GTIOC1A pin output GTIOC1B pin output GTIOC2A pin output GTIOC2B pin output...
Page 542 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320. GTPR register GPT320.GTCCRA register GPT321.GTCNT counter GPT321. GTPR register GPT321.GTCCRA register GPT322.GTCNT counter GPT322. GTPR register GPT322.GTCCRA register GPT320.GTDVU GPT320.GTDVU GTIOC0A pin output GTIOC0B pin output GPT321.GTDVU GTIOC1A pin output GPT321.GTDVU GTIOC1B pin output GPT322.GTDVU...
Page 543 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320. GTPR register GPT320.GTCCRC register GPT320.GTCCRD register GPT321.GTCNT counter GPT321. GTPR register GPT321.GTCCRC register GPT321.GTCCRD register GPT322.GTCNT counter GPT322. GTPR register GPT322.GTCCRC register GPT322.GTCCRD register GPT320.GTDVU GPT320.GTDVU GTIOC0A pin output GTIOC0B pin output GPT321.GTDVU GTIOC1A pin output...
Page 544 S3A3 User’s Manual 23. General PWM Timer (GPT) GTIOCA pin input GTIOCB pin input GTCNT counter Up-counting Down-counting Time Figure 23.67 Example of phase counting mode 1 Table 23.7 Conditions of up-counting/down-counting in phase counting mode 1 GTIOCA pin input GTIOCB pin input Operation Register setting...
Page 545 S3A3 User’s Manual 23. General PWM Timer (GPT) Table 23.8 Conditions of up-counting/down-counting in phase counting mode 2 (A) GTIOCA pin input GTIOCB pin input Operation Register setting High Don’t care GTUPSR = 0000 0800h GTDNSR = 0000 0400h High Up-counting High Don’t care...
Page 546 S3A3 User’s Manual 23. General PWM Timer (GPT) GTIOCA pin input GTIOCB pin input GTCNT counter Up-counting Down-counting Time Figure 23.70 Example of phase counting mode 2 (C) Table 23.10 Conditions of up-counting/down-counting in phase counting mode 2 (C) GTIOCA pin input GTIOCB pin input Operation Register setting...
Page 547 S3A3 User’s Manual 23. General PWM Timer (GPT) Table 23.11 Conditions of up-counting/down-counting in phase counting mode 3 (A) GTIOCA pin input GTIOCB pin input Operation Register setting High Don’t care GTUPSR = 0000 0800h GTDNSR = 0000 8000h High Up-counting High Down-counting...
Page 548 S3A3 User’s Manual 23. General PWM Timer (GPT) GTIOCA pin input GTIOCB pin input GTCNT counter Up-counting Down-counting Time Figure 23.73 Example of phase counting mode 3 (C) Table 23.13 Conditions of up-counting/down-counting in phase counting mode 3 (C) GTIOCA pin input GTIOCB pin input Operation Register setting...
Page 549 S3A3 User’s Manual 23. General PWM Timer (GPT) Table 23.14 Conditions of up-counting/down-counting in phase counting mode 4 GTIOCA pin input GTIOCB pin input Operation Register setting High Up-counting GTUPSR = 0000 6000h GTDNSR = 0000 9000h Don’t care High High Down-counting High...
Page 550 S3A3 User’s Manual 23. General PWM Timer (GPT) GTIOCA pin input GTIOCB pin input GTCNT Up-counting Time Figure 23.76 Example of phase counting mode 5 (B) Table 23.16 Conditions of up-counting/down-counting in phase counting mode 5 (B) GTIOCA pin input GTIOCB pin input Operation Register setting...
Page 551 S3A3 User’s Manual 23. General PWM Timer (GPT) Soft setting (UF/VF/WF) OPSCR. Hall sensor UF/VF/WF input edge sample GPT_UVWEDGE PCLKD (every PCLKD) sample Input phase (Input U-phase) PWM edge (Input V-phase) sample Synchronize (Input W-phase) From Hall element noise filter PCLKD GTIU OPS internal node name...
Page 552 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320 PWM Input sel after “U-phase” GTIU Input sel after “V-phase” GTIV Input sel after “W-phase” GTIW Output “U-phase (Up)” GTOUUP Output “U-phase (Lo)” GTOULO Output “V-phase (Up)” GTOVUP Output “V-phase (Lo)” GTOVLO Output “W-phase (Up)”...
Page 553 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320 PWM "U-phase" after input selection GTIU "V-phase" after input selection GTIV "W-phase" after input selection GTIW Output enable OPSCR.EN Auto clear Setting by software Output Disabled Source Select 00b (Group A output disable request) OPSCR.GRP Group output disable OPSCR.GODF...
Page 554 S3A3 User’s Manual 23. General PWM Timer (GPT) Table 23.17 Input selection processing method OPSCR register Selection of input phase sampling method Synchronization input/output selection FB bit ALIGN bit (U/V/W-phase) process (GPT_OPS internal node name) External Input at PWM Falling Edge Sampling Input Phase (PCLKD synchronization + falling edge sample) Input U-Phase (gtu_sync)
Page 555 S3A3 User’s Manual 23. General PWM Timer (GPT) Table 23.19 Output selection control method (positive phase) Enable-phase output Positive-phase output Invert-phase output Output port name (positive phase = up) control (P) control control (output selection internal node allocation) GTOUUP GTOVUP OPSCR.EN bit OPSCR.P bit OPSCR.INV bit...
Page 556 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.3.11.5 Output selection control (group output disable function) When OPSCR.GODF is 1 and the signal value selected by the OPSCR.GRP[1:0] bit is high (output disable request), the GPT_OPS output pins are changed to Hi-Z asynchronously and the OPSCR.EN bit is set to 0 by the output disable request signal synchronized with PCLKD.
Page 557 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.3.11.7 GPT_OPS start operation setting flow GPT320 operation mode setting GPT320.GTIOCA set the PWM output operation mode of the saw-wave or triangle-wave. For details, see section 23.3.3, PWM Output Operating Mode. Counting of GPT320 Start the count operation of GPT320 and output a PWM waveform.
Page 558 S3A3 User’s Manual 23. General PWM Timer (GPT) Table 23.21 Interrupt sources (1 of 2) DMAC/DTC Channel Name Interrupt source Interrupt flag activation GPT0_CCMPA GPT320.GTCCRA input capture/compare match TCFA Possible GPT0_CCMPB GPT320.GTCCRB input capture/compare match TCFB Possible GPT0_CMPC GPT320.GTCCRC compare match TCFC Possible GPT0_CMPD...
Page 559 S3A3 User’s Manual 23. General PWM Timer (GPT) Table 23.21 Interrupt sources (2 of 2) DMAC/DTC Channel Name Interrupt source Interrupt flag activation GPT5_CCMPA GPT165.GTCCRA input capture/compare match TCFA Possible GPT5_CCMPB GPT165.GTCCRB input capture/compare match TCFB Possible GPT5_CMPC GPT165.GTCCRC compare match TCFC Possible GPT5_CMPD...
Page 560 S3A3 User’s Manual 23. General PWM Timer (GPT)  When the GTCCRA register functions as an input capture register, the input-capture signal causes transfer of the GTCNT counter value to the GTCCRA register. (2) GPTn_CCMPB interrupt (n = 0 to 9) An interrupt request is generated under the following conditions: ...
Page 561 S3A3 User’s Manual 23. General PWM Timer (GPT) (7) GPTn_OVF interrupt (n = 0 to 9) An interrupt request is generated under the following conditions:  In saw-wave mode, interrupt requests are enabled at overflows (when the GTCNT counter value changes from GTPR to 0 during up-counting) ...
Page 562 S3A3 User’s Manual 23. General PWM Timer (GPT) 23.5.2 Event Signal Inputs from ELC The GPT can perform the following operations in response to a maximum of eight events from the ELC:  Start counting, stop counting, clear counting  Up-counting, down-counting ...
Page 563 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register 0000 0000h Time Register write timing is too late Register write Register write for buffer transfer timing bbbb cccc dddd eeee GPT320.GTCCRF register Buffer transfer at trough Buffer transfer at crest Buffer transfer at crest aaaa...
Page 564 S3A3 User’s Manual 23. General PWM Timer (GPT) end of cycle, GTIOR.OADF[1:0] should be set to 00b (for GTIOCA pin) or GTIOR.OBDF[1:0] should be set to 00b (for GTIOCB pin). Figure 23.84 shows an example of the GTIOC pin output disable control operation. GPT320.GTCNT counter value GPT320.GTPR register cccc...
Page 565 S3A3 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRA register GPT320.GTCCRB register 0000 0000h Time Hi-Z GTIOC0A pin output Hi-Z GTIOC0B pin output Reset is released. Count operation starts. GTIOR.OAE and OBE bits are set. Reset GPT initialization settings Count operation...
Page 566 S3A3 User’s Manual 23. General PWM Timer (GPT) GTCCRA > GTPR, no compare match occurs. Similarly, GTCCRB should be set within the range of 0 < GTCCRB < GTPR. If GTCCRB = 0 or GTCCRB = GTPR is set, a compare match occurs within the cycle only when GTCCRB = 0 or GTCCRB = GTPR is satisfied. When GTCCRB >...
Page 567 S3A3 User’s Manual 23. General PWM Timer (GPT) If up-counting and down-counting by hardware sources occur at the same time, the GTCNT counter value does not change. When there is a conflict between updating the GTCNT register and reading by the CPU, pre-update data is read. (2) GTCR.CST bit When there is a conflict between starting/stopping by hardware sources set in the GTSSR/GTPSR registers and writing by the CPU (writing to GTCR/GTSTR/GTSTP registers), writing by CPU has priority over starting/stopping by...
Page 568 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Asynchronous General Purpose Timer (AGT) 24.1 Overview The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting external events. This 16-bit timer consists of a reload register and a down counter.
Page 569 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Data bus 16-bit 16-bit 16-bit reload reload reload register register register TCMEA or TCMEB = 1 TCK[2:0] AGT underflows TCK[2:0] = 000b CKS[2:0] AGT underflows or PCLKB AGTCMA AGTCMB = 100b AGTLCLK AGT is rewritten = 001b...
Page 570 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.2 Register Descriptions 24.2.1 AGT Counter Register (AGT) Address(es): AGT0.AGT 4008 4000h, AGT1.AGT 4008 4100h Value after reset: Description Setting Range *1, *2 b15 to b0 16-bit counter and reload register 0000h to FFFFh Note 1.
Page 571 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.2.3 AGT Compare Match B Register (AGTCMB) Address(es): AGT0.AGTCMB 4008 4004h, AGT1.AGTCMB 4008 4104h Value after reset: Description Setting range b15 to b0 16-bit compare match B data is stored 0000h to FFFFh Note 1.
Page 572 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) TCSTF flag (AGT count status flag) [Setting condition]  When 1 is written to the TSTART bit (the TCSTF flag is set to 1 in synchronization with the count source). [Clearing conditions] ...
Page 573 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.2.5 AGT Mode Register 1 (AGTMR1) Address(es): AGT0.AGTMR1 4008 4009h, AGT1.AGTMR1 4008 4109h TEDGP — TCK[2:0] TMOD[2:0] Value after reset: Symbol Bit name Description b2 to b0 TMOD[2:0] Operating mode 0 0 0: Timer mode 0 0 1: Pulse output mode 0 1 0: Event counter mode 0 1 1: Pulse width measurement mode...
Page 574 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.2.6 AGT Mode Register 2 (AGTMR2) Address(es): AGT0.AGTMR2 4008 400Ah, AGT1.AGTMR2 4008 410Ah — — — — CKS[2:0] Value after reset: Symbol Bit name Description b2 to b0 CKS[2:0] AGTLCLK/AGTSCLK 0 0 0: 1/1 count source clock 0 0 1: 1/2 frequency division ratio...
Page 575 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Symbol Bit name Description — Reserved This bit is read as 0. The write value should be 0. AGTOn output enable 0: AGTOn output disabled 1: AGTOn output enabled. — Reserved This bit is read as 0.
Page 576 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.2.9 AGT Compare Match Function Select Register (AGTCMSR) Address(es): AGT0.AGTCMSR 4008 400Eh, AGT1.AGTCMSR 4008 410Eh TOPOL TOPOL — TOEB TCMEB — TOEA TCMEA Value after reset: Symbol Bit name Description TCMEA Compare match A 0: Compare match A register disabled register enable...
Page 577 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) The AGTIOSEL register sets the AGTIOn pin when using the AGTIOn in Software Standby mode. The AGTIOSEL register can be set with an 8-bit memory manipulation instruction. SEL[1:0] bits (AGTIOn Pin Select) The SEL[1:0] bits select the AGTIOn pin function.
Page 578 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Write 1 to TSTART bit in AGTCR register with software Write 5678h to AGT register with software Write 1234h to AGT register with software Register write clock Count source TSTART bit in AGTCR register TCMEB bit in AGTCMSR register...
Page 579 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Write 1 to TSTART bit in AGTCR register with software Write 1234h to AGT register with software Write 5678h to AGT register with software Register write clock Count source TSTART bit in AGTCR register TCMEB bit in AGTCMSR register...
Page 580 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Write 1 to TSTART bit in AGTCR register with software Write 1234h to AGTCMA register with software Write 2345h to AGTCMA register with software Register write clock Count source TSTART bit in AGTCR register AGT counter 5678h...
Page 581 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Count source Previous value Reload register New value (1010h) (0300h) Counter reloading occurs AGT counter 02FAh 02F9h 02F8h 02F7h 1010h 100Fh 100Eh ••••• ••••• 0000h 1010h 100Fh 100Eh 100Dh 100Ch 100Bh TUNDF bit in AGTCR register Set to 0 with...
Page 582 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Write 1 to TSTART bit in AGTCR register with software Write 0002h to Write 0004h to AGT register with AGT register with software software Count source TSTART bit in AGTCR register AGT register FFFFh 0002h...
Page 583 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Event counter mode is entered TMOD[2:0] bits in 010b AGTMR1 register Event is counted at rising edge AGTIOC register TSTART bit in AGTCR register Event input is started Event input is complete AGTIOn pin event input AGT counter...
Page 584 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) ends, the counter is stopped, the TEDGF bit in the AGTCR register is set to 1 (active edge received), and an interrupt request is generated. The measurement of pulse width data is performed by reading the count value while the counter is stopped.
Page 585 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Count source TSTART bit in AGTCR register Measurement pulse input Counter is reloaded AGT counter 0300h •••• 02FFh 02FEh 0300h 02FFh 02FEh 02FDh02FCh 02FBh 02FAh 02F9h 02F8h 02F7h 0300h 02FFh •••• 0001h 0000h 0300h 02FFh 02FEh Content of read-out buffer 0300h...
Page 586 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) n = AGT register content m = Compare Match A register setting value p = Compare Match B register setting value FFFFh Count starts Underflow Underflow Matched Matched Matched Matched Time 0000h TSTART bit in AGTCR register...
Page 587 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.3.9 Output Settings for each Mode Table 24.5 Table 24.8 list the states of pins AGTOn, AGTIOn, AGTOAn, and AGTOBn in each mode. Table 24.5 AGTOn pin setting AGTIOC register Operating mode TOE bit TEDGSEL bit AGTOn pin output...
Page 588 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Table 24.8 AGTOBn pin setting (2 of 2) AGTCMSR register Operating mode TOEB bit TOPOLB bit AGTOBn pin output Event counter mode Inverted output Normal output 0 or 1 Output disabled (not used) Pulse width measurement mode Prohibited...
Page 589 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Table 24.11 AGT interrupt sources DMAC/DTC Name Interrupt source activation  When the counter underflows AGTn_AGTI Possible  When measurement of the active width of the external input (AGTIOn) is complete in pulse width measurement mode ...
Page 590 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.4.3 When Changing Mode The registers associated with AGT operating mode (AGTMR1, AGTMR2, AGTIOC, AGTISR, AGTCMSR, and AGTIOC) can be changed only when the count is stopped with both the TSTART and TCSTF bits set to 0 (count stops). Do not change these registers during count operation.
Page 591 S3A3 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.4.8 Reset of I/O Register The I/O register of the AGT is not initialized by different types of resets. For details, see section 6, Resets. 24.4.9 When Selecting PCLKB, PCLKB/8, or PCLKB/2 as the Count Source When a reset is generated, the operation of the AGT cannot be guaranteed.
Page 592 S3A3 User’s Manual 25. Realtime Clock (RTC) Realtime Clock (RTC) 25.1 Overview The RTC has two counting modes, calendar count mode and binary count mode, that are used by switching register settings. For calendar count mode, the RTC has a 100 year calendar from 2000 to 2099 and automatically adjusts dates for leap years.
Page 593 S3A3 User’s Manual 25. Realtime Clock (RTC) Internal peripheral bus Realtime clock (RTC) Bus interface To each RCR2 RTCOUT function Time counter 1-Hz/64-Hz output Alarm function prescaler XCIN 128 Hz RSECAR/ RMINAR/ RSECCNT/ 32.768 kHz Sub-clock 128 Hz generation R64CNT BCNT0AR BCNT1AR BCNT0...
Page 594 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.2 Register Descriptions Write or read from the RTC registers as described in section 25.6.5, Notes on Writing to and Reading from Registers. If the value in an RTC register after a reset is given as x (undefined bits) in the list, it is not initialized by a reset. When RTC enters the reset state or a low power state during counting operations, for example while the RCR2.START bit is 1, the year, month, day of the week, date, hours, minutes, seconds, and 64-Hz counters continue to operate.
Page 595 S3A3 User’s Manual 25. Realtime Clock (RTC) Symbol Bit name Description — Reserved Set this bit to 0. It is read as the set value. The RSECCNT counter sets and counts the BCD-coded second value. It counts the carries generated once per second in the 64-Hz counter.
Page 596 S3A3 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.BCNT1 4004 4004h BCNT[15:8] Value after reset: x: Undefined BCNT1 is a read/write 32-bit binary counter b15 to b8 that performs count operation by a carry generated for each second of the 64-Hz counter.
Page 597 S3A3 User’s Manual 25. Realtime Clock (RTC) bit in RCR2. To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time. 25.2.5 Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3) (1) In calendar count mode: Address(es): RTC.RWKCNT 4004 4008h —...
Page 598 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.2.6 Day Counter (RDAYCNT) Address(es): RTC.RDAYCNT 4004 400Ah — — DATE10[1:0] DATE1[3:0] Value after reset: x: Undefined Symbol Bit name Description b3 to b0 DATE1[3:0] 1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place b5, b4 DATE10[1:0]...
Page 599 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.2.8 Year Counter (RYRCNT) Address(es): RTC.RYRCNT 4004 400Eh — — — — — — — — YR10[3:0] YR1[3:0] Value after reset: x: Undefined Symbol Bit name Description b3 to b0 YR1[3:0] 1-Year Count Counts from 0 to 9 once per year.
Page 600 S3A3 User’s Manual 25. Realtime Clock (RTC)  RYRAREN. When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RSECAR values from 00 through 59 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate correctly.
Page 601 S3A3 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.BCNT1AR 4004 4012h BCNTAR[15:8] Value after reset: x: Undefined BCNT1AR is a read/write alarm register associated with the 32-bit binary counter from b15 to b8. This register is set to 00h by an RTC software reset.
Page 602 S3A3 User’s Manual 25. Realtime Clock (RTC) RTC software reset. (2) In binary count mode: Address(es): RTC.BCNT2AR 4004 4014h BCNTAR[23:16] Value after reset: x: Undefined BCNT2AR is a read/write alarm register associated with the 32-bit binary counter b23 to b16. This register is cleared to 00h by an RTC software reset.
Page 603 S3A3 User’s Manual 25. Realtime Clock (RTC) correctly. This register is set to 00h by an RTC software reset. (2) In binary count mode: Address(es): RTC.BCNT3AR 4004 4016h BCNTAR[31:24] Value after reset: x: Undefined BCNT3AR is a read/write alarm register associated with the 32-bit binary counter b31 to b24. This register is set to 00h by an RTC software reset.
Page 604 S3A3 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.BCNT0AER 4004 4018h ENB[7:0] Value after reset: x: Undefined BCNT0AER is a read/write register to set the alarm enable associated with the 32-bit binary counter b7 to b0. The binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm register (BCNTAR[31:0]), and when all match, the IR flag associated with the RTC_ALM interrupt becomes 1.
Page 605 S3A3 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.BCNT1AER 4004 401Ah ENB[15:8] Value after reset: x: Undefined BCNT1AER is a read/write register for setting the alarm enable associated with the 32-bit binary counter b15 to b8. The binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm register (BCNTAR[31:0]), and when all match, the IR flag associated with the RTC_ALM interrupt becomes 1.
Page 606 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.2.16 Year Alarm Enable Register (RYRAREN)/Binary Counter 3 Alarm Enable Register (BCNT3AER) (1) In calendar count mode: Address(es): RTC.RYRAREN 4004 401Eh — — — — — — — Value after reset: x: Undefined Symbol Bit name Description...
Page 607 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.2.17 RTC Control Register 1 (RCR1) Address(es): RTC.RCR1 4004 4022h PES[3:0] RTCOS Value after reset: x: Undefined Symbol Bit name Description Alarm Interrupt Enable 0: An alarm interrupt request is disabled 1: An alarm interrupt request is enabled. Carry Interrupt Enable 0: A carry interrupt request is disabled 1: A carry interrupt request is enabled.
Page 608 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.2.18 RTC Control Register 2 (RCR2) (1) In calendar count mode: Address(es): RTC.RCR2 4004 4024h CNTM HR24 AADJP AADJE RTCOE ADJ30 RESET START Value after reset: x: Undefined Symbol Bit name Description START Start 0: Prescaler and time counter are stopped 1: Prescaler and time counter operate normally.
Page 609 S3A3 User’s Manual 25. Realtime Clock (RTC) ADJ30 (30-Second Adjustment) The ADJ30 bit is for 30-second adjustment. When 1 is written to the ADJ30 bit, the RSECCNT value of 30 seconds or less is rounded down to 00 second and the value of 30 seconds or more is rounded up to 1 minute.
Page 610 S3A3 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.RCR2 4004 4024h CNTM — AADJP AADJE RTCOE — RESET START Value after reset: x: Undefined Symbol Bit name Description START Start 0: The 32-bit binary counter, 64-Hz counter, and prescaler are stopped 1: The 32-bit binary counter, 64-Hz counter, and prescaler are in normal operation.
Page 611 S3A3 User’s Manual 25. Realtime Clock (RTC) AADJE (Automatic Adjustment Enable) The AADJE bit controls (enables or disables) automatic adjustment. Set the plus-minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the AADJE bit. The AADJE bit is cleared to 0 by an RTC software reset. AADJP (Automatic Adjustment Period Select)
Page 612 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.2.20 Frequency Register (RFRH/RFRL) Address(es): RTC.RFRH 4004 402Ah — — — — — — — — — — — — — — — RFC16 Value after reset: x: Undefined Symbol Bit name Description RFC16 Reserved Write 0 before writing to the RFRL register after a cold start.
Page 613 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.2.21 Time Error Adjustment Register (RADJ) Address(es): RTC.RADJ 4004 402Eh PMADJ[1:0] ADJ[5:0] Value after reset: x: Undefined Symbol Bit name Description b5 to b0 ADJ[5:0] Adjustment Value These bits specify the adjustment value from the prescaler b7, b6 PMADJ[1:0] Plus–Minus...
Page 614 S3A3 User’s Manual 25. Realtime Clock (RTC) Symbol Bit name Description b5, b4 TCNF[1:0] Time Capture Noise b5 b4 0 0: Noise filter is off Filter Control 0 1: Setting prohibited 1 0: Noise filter is on (count source) 1 1: Noise filter is on (count source by divided by 32). —...
Page 615 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.2.23 Second Capture Register y (RSECCPy) (y = 0 to 2)/BCNT0 Capture Register y (BCNT0CPy) (y = 0 to 2) (1) In calendar count mode: Address(es): RTC.RSECCP0 4004 4052h, RTC.RSECCP1 4004 4062h, RTC.RSECCP2 4004 4072h —...
Page 616 S3A3 User’s Manual 25. Realtime Clock (RTC) Symbol Bit name Description b6 to b4 MIN10[2:0] 10-Minute Capture Capture value for the tens place of minutes — Reserved This bit is read as 0 after an RTC software reset RMINCPy is a read-only register that captures the RMINCNT value when a time capture event is detected. The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RMINCP0, RMINCP1, and RMINCP2 registers, respectively.
Page 617 S3A3 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.BCNT2CP0 4004 4056h, RTC.BCNT2CP1 4004 4066h, RTC.BCNT2CP2 4004 4076h BCNTCPy[23:16] Value after reset: x: Undefined BCNT2CPy is a read-only register that captures the BCNT2 value when a time capture event is detected. The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the BCNT2CP0, BCNT2CP1, and BCNT2CP2 registers, respectively.
Page 618 S3A3 User’s Manual 25. Realtime Clock (RTC) capture event detection using the RTCCRy.TCCT[1:0] bits. 25.2.27 Month Capture Register y (RMONCPy) (y = 0 to 2) (1) In calendar count mode: Address(es): RTC.RMONCP0 4004 405Ch, RTC.RMONCP1 4004 406Ch, RTC.RMONCP2 4004 407Ch —...
Page 619 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.3.2 Clock and Count Mode Setting Procedure Figure 25.3 shows how to set the clock and the count mode. Select the count source RCR4.RCKSEL bit setting Supply 6 clocks of the clock selected by the Supply 6 clocks of the count source RCR4.RCKSEL bit Set the START bit to 0...
Page 620 S3A3 User’s Manual 25. Realtime Clock (RTC) Set the START bit to 0 Write 0 to the RCR2.START bit START = 0 Wait for the RCR2.START bit to become 0 Execute an RTC software reset Write 1 to the RCR2.RESET bit RESET = 0 Wait for the RCR2.RESET bit to become 0 Set the year, month, day of the week,...
Page 621 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.3.5 Reading 64-Hz Counter and Time Figure 25.6 shows how to read a 64-Hz counter and time. (a) To read the time without using interrupt Disable the NVIC carry interrupt request Write 1 to the Interrupt Clear-Enable Register corresponding to the RTC_CUP interrupt Enable the RTC carry interrupt request Write 1 to the RCR1.CIE bit...
Page 622 S3A3 User’s Manual 25. Realtime Clock (RTC) 25.3.6 Alarm Function Figure 25.7 shows how to use the alarm function. Write 1 to the Interrupt Clear-Enable Register Disable the NVIC alarm interrupt request corresponding to the RTC_ALM interrupt Set alarm enable at the same time as or after the Set alarm time alarm time setting Enable the RTC alarm interrupt request...
Page 623 S3A3 User’s Manual 25. Realtime Clock (RTC) The RCR1.AIE bit register is set to 1 Enable the alarm interrupt Write 0 to the Interrupt Clear-Enable Register Disable the alarm interrupt request of associated with the RTC_ALM interrupt the NVIC Disable the alarm interrupt request of Write 0 to the RCR1.AIE bit the RTC Wait for the RCR1.AIE bit to be cleared to 0...
Page 624 S3A3 User’s Manual 25. Realtime Clock (RTC) (2) Example 2: Sub-clock oscillator running at 32.766 kHz (a) Adjustment procedure When the sub-clock oscillator is running at 32.766 kHz, 1 second elapses every 32,766 clock cycles. The RTC is meant to run at 32,768 clock cycles, so the clock runs slow by 2 clock cycles every second. The time on the clock is slow by 20 clock cycles every 10 seconds, so adjustment can take the form of setting the clock forward by 20 cycles every 10 seconds.
Page 625 S3A3 User’s Manual 25. Realtime Clock (RTC) To change automatic adjustment to adjustment by software: 1. Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed). 2. Set the RCR2.AADJE bit to 0 (adjustment by software is enabled). 3. Proceed with the adjustment by setting the RADJ.PMADJ[1:0] bits for addition or subtraction and the RADJ.ADJ[5:0] bits to the value for use in time error adjustment at the desired time.
Page 626 S3A3 User’s Manual 25. Realtime Clock (RTC) Count source RTCICn (n = 0 to 2) Internal event-input signal Since the level has matched three Since the level has only matched times, it is conveyed to the internal twice, it is not conveyed to the circuits.
Page 627 S3A3 User’s Manual 25. Realtime Clock (RTC) Sequence for setting the alarm Wait until the alarm Alarm register settings time setting is in progress confirmed Alarm registers Clock counters Match while settings are being made Interrupt flag (the IELSRn.IR bit and the Interrupt Set-Pending Register corresponding to the RTC_ALM interrupt...
Page 628 S3A3 User’s Manual 25. Realtime Clock (RTC) The event generation period immediately after the event generation is selected, is not guaranteed. Note: If event linking from the RTC is used, only set the ELC after setting the RTC, for example, initialization and time settings.
Page 629 S3A3 User’s Manual 25. Realtime Clock (RTC) Set the RCR1.PES[3:0] bits and Set the period and enable interrupt requests write 1 to the RCR1.PIE bit The period is not guaranteed Confirm generation of the first periodic interrupt* The first interrupt is generated Interrupts The set period elapses generated...
Page 630 S3A3 User’s Manual 25. Realtime Clock (RTC) Alternatively, when the sub-clock oscillator is not used as the system clock or realtime clock, the counter can be stopped by writing 0 (sub-clock oscillator is selected) to the RCR4.RCKSEL bit and stopping the sub-clock oscillator. To stop the sub-clock oscillator, write 1 to the SOSCCR.SOSTP bit.
Page 631 S3A3 User’s Manual 26. Watchdog Timer (WDT) Watchdog Timer (WDT) 26.1 Overview The Watchdog Timer (WDT) is a 14-bit down-counter and can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow interrupt.
Page 632 S3A3 User’s Manual 26. Watchdog Timer (WDT) Interrupt request (WDT_NMIUNDF) Interrupt control circuit WDT output Reset control circuit Clock frequency divider PCLKB/4 PCLKB/64 PCLKB PCLKB/128 WDT control circuit 14-bit down-counter PCLKB/512 PCLKB/2048 PCLKB/8192 Option Function Select Register 0 (OFS0) Count stop control output in Sleep mode Clock control circuit Event signal output...
Page 633 S3A3 User’s Manual 26. Watchdog Timer (WDT) 26.2.2 WDT Control Register (WDTCR) Address(es): WDT.WDTCR 4004 4202h — — RPSS[1:0] — — RPES[1:0] CKS[3:0] — — TOPS[1:0] Value after reset: Symbol Bit name Description b1, b0 TOPS[1:0] Timeout Period Select b1 b0 0 0: 1,024 cycles (03FFh) 0 1: 4,096 cycles (0FFFh) 1 0: 8,192 cycles (1FFFh)
Page 634 S3A3 User’s Manual 26. Watchdog Timer (WDT) Table 26.2 Timeout period settings CKS[3:0] bits TOPS[1:0] bits Timeout period Clock division ratio (number of cycles) PCLKB clock cycles PCLKB/4 1024 4096 4096 16384 8192 32768 16384 65536 PCLKB/64 1024 65536 4096 262144 8192 524288...
Page 635 S3A3 User’s Manual 26. Watchdog Timer (WDT) Table 26.3 Relationship between timeout period and window start and end counter values Timeout period Window start and end counter value TOPS[1:0] bits Cycles Counter value 100% 1024 03FFh 03FFh 02FFh 01FFh 00FFh 4096 0FFFh 0FFFh...
Page 636 S3A3 User’s Manual 26. Watchdog Timer (WDT) CNTVAL[13:0] bits (Down-Counter Value) Read the CNTVAL[13:0] bits to confirm the value of the down-counter. The read value might differ from the actual count by a value of one count. UNDFF flag (Underflow Flag) Read the UNDFF flag to confirm whether an underflow occurred in the down-counter.
Page 637 S3A3 User’s Manual 26. Watchdog Timer (WDT) 26.2.5 WDT Count Stop Control Register (WDTCSTPR) Address(es): WDT.WDTCSTPR 4004 4208h SLCST — — — — — — — Value after reset: Symbol Bit name Description b6 to b0 — Reserved These bits are read as 0 and cannot be modified SLCSTP Sleep-Mode Count Stop Control 0: Count stop is disabled...
Page 638 S3A3 User’s Manual 26. Watchdog Timer (WDT) After the reset state is released, set the following to Sleep mode in the WDTCSTPR register:  Clock division ratio  Window start and end positions  Timeout period in the WDTCR register ...
Page 639 S3A3 User’s Manual 26. Watchdog Timer (WDT) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES pin Control register (WDTCR) (1) Initial value (2) Set value Writing to the Writing to the Writing to Writing to the Writing to the register is invalid *1 register is valid...
Page 640 S3A3 User’s Manual 26. Watchdog Timer (WDT) However, if the down-counter underflows because refreshing of the down-counter is not possible due to a runaway program or if a refresh error occurs due to refreshing outside the refresh-permitted period, the WDT outputs a reset signal or non-maskable interrupt request/interrupt request (WDT_NMIUNDF).
Page 641 S3A3 User’s Manual 26. Watchdog Timer (WDT) becomes 1 to protect WDTCR, WDTRCR and WDTCSTPR against subsequent write attempts. This protection is released by a reset source of the WDT. With other reset sources, the protection is not released. Figure 26.5 shows control waveforms produced in response to writing to the WDTCR.
Page 642 S3A3 User’s Manual 26. Watchdog Timer (WDT) Peripheral clock (PCLKB) Data written to WDTRR register WDTRR register Valid write signal (internal signal) WDTRR register Invalid Refresh synchronization signal Refresh signal (after synchronization Refresh request with count cycle) Counter value (n+1)h (n)h (n-1)h 0FFFh...
Page 643 S3A3 User’s Manual 26. Watchdog Timer (WDT) Peripheral clock (PCLKB) Refreshing (n)h (n-1)h Counter value (n+1)h (n-1)h 0FFFh Bits WDTSR.CNTVAL (n)h (n+1)h (n-1)h (n-1)h 0FFFh [13:0] WDTSR.CNTVAL [13:0] read signal (internal signal) WDTSR.CNTVAL xxxxh (n+1)h (n)h (n)h 0FFFh [13:0] read data Figure 26.7 Read process for WDT down-counter value when WDTCR.CKS[3:0] = 0100b, WDTCR.TOPS[1:0] = 26.3.7...
Page 644 S3A3 User’s Manual 27. Independent Watchdog Timer (IWDT) Independent Watchdog Timer (IWDT) 27.1 Overview The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt/ interrupt on a timer underflow.
Page 645 S3A3 User’s Manual 27. Independent Watchdog Timer (IWDT) Interrupt request (IWDT_NMIUNDF) Interrupt control circuit IWDT reset output Reset control circuit Clock frequency divider IWDTCLK IWDTCLK IWDTCLK/16 IWDTCLK/32 IWDT control circuit 14-bit counter IWDTCLK/64 IWDTCLK/128 IWDTCLK/256 Count stop control output Option Function Select Register 0 in Sleep, Snooze, or Software Standby (OFS0) mode...
Page 646 S3A3 User’s Manual 27. Independent Watchdog Timer (IWDT) 27.2.2 IWDT Status Register (IWDTSR) Address(es): IWDT.IWDTSR 4004 4404h REFEF UNDFF CNTVAL[13:0] Value after reset: Symbol Bit name Description b13 to b0 CNTVAL[13:0] Counter Value Value counted by the down-counter UNDFF Underflow Flag 0: Underflow not occurred R/(W)* 1: Underflow occurred.
Page 647 S3A3 User’s Manual 27. Independent Watchdog Timer (IWDT) 27.2.3 Option Function Select Register 0 (OFS0) For information on the Option Function Select Register 0 (OFS0), see section 7.2.1, Option Function Select Register 0 (OFS0). IWDTTOPS[1:0] bits (IWDT Timeout Period Selects) The IWDTTOPS[1:0] bits select the timeout period, that is, the period until the down-counter underflows from 128, 512, 1024, or 2048 cycles, taking the divided clock specified by the IWDTCKS[3:0] bits as 1 cycle.
Page 648 S3A3 User’s Manual 27. Independent Watchdog Timer (IWDT) value smaller than the window start position. If the window end position is greater than the window start position, only the window start position setting is enabled. IWDTRPSS[1:0] bits (IWDT Window Start Position Select) The IWDTRPSS[1:0] bits specify the window start position that indicates the refresh-permitted period.
Page 649 S3A3 User’s Manual 27. Independent Watchdog Timer (IWDT) 27.3 Operation 27.3.1 Auto Start Mode When the IWDT Start Mode Select bit (OFS0.IWDTSTRT) in the Option Function Select Register 0 is 0, auto start mode is selected, otherwise IWDT is disabled. Within the reset state, the setting values for the following in the Option Function Select Register 0 (OFS0) are set in the IWDT registers: ...
Page 650 S3A3 User’s Manual 27. Independent Watchdog Timer (IWDT) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES pin Refresh the counter Active: High Counting starts Counting starts Counting starts Counting starts Underflow Refresh error Refresh error Status flag Refresh error flag cleared...
Page 651 S3A3 User’s Manual 27. Independent Watchdog Timer (IWDT) After FFh is written to the IWDTRR register, refreshing the counter requires up to 4 cycles of the signal for counting (the IWDT-dedicated clock frequency division ratio select bits (OFS0.IWDTCKS[3:0]) determine how many cycles of the IWDT-dedicated clock (IWDTCLK) make up 1 cycle for counting).
Page 652 S3A3 User’s Manual 27. Independent Watchdog Timer (IWDT) 27.3.4 Reset Output When the IWDT Reset Interrupt Request Select bit (OFS0.IWDTRSTIRQS) in the Option Function Select Register 0 (OFS0) is set to 1, a reset signal is output when an underflow in the counter or a refresh error occurs. Counting down automatically starts after the reset output.
Page 653 S3A3 User’s Manual 27. Independent Watchdog Timer (IWDT) 27.5 Usage Notes 27.5.1 Refresh Operations While configuring the refresh time, consider variations in the range of errors given the accuracy of PCLKB and IWDTCLK. Set values that ensure refreshing is possible. 27.5.2 Clock Division Ratio Setting Satisfy the frequency of the peripheral module clock (PCLKB) ...
Page 654 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) USB 2.0 Full-Speed Module (USBFS) 28.1 Overview The MCU provides a USB 2.0 Full-Speed module (USBFS) that operates as a host or device controller compliant with the Universal Serial Bus (USB) specification revision 2.0. The host controller supports USB 2.0 full-speed and low- speed transfers, and the device controller supports USB 2.0 full-speed transfers.
Page 655 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.1 shows a block diagram of the USBFS. VCC_USB_LDO USB LDO VCC_USB Regulator Battery charging control controller LINK core Registers Registers USB device controller USB_DP Interrupt USB_DM controller FIFO buffer controller USB protocol engine...
Page 656 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2 Register Descriptions 28.2.1 System Configuration Control Register (SYSCFG) Address(es): USBFS.SYSCFG 4009 0000h DCFM DRPD DPRPU DMRP — — — — — SCKE — CNEN — — — USBE Value after reset: Symbol Bit name Description...
Page 657 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) DMRPU (D- Line Resistor Control* The DMRPU bit enables or disables pulling up the D- line in device controller mode. When the DMRPU bit is set to 1 in device controller mode, the USBFS pulls up the D- line to notify the USB host that it attached as a low-speed device.
Page 658 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description b15, b14 OVCMON[1:0] External USB_OVRCURA/ OVCMON[1] bit indicates the USB_OVRCURA pin status USB_OVRCURB Input Pin OVCMON[0] bit indicates the USB_OVRCURB pin status. Monitor Note 1. Depends on the status of the USB_OVRCURA/USB_OVRCURB and USB_ID pins. LNST[1:0] bits (USB Data Line Status...
Page 659 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description USBRST USB Bus Reset Output 0: USB bus reset signal not output 1: USB bus reset signal output. RWUPE Wakeup Detection Enable 0: Downstream port wakeup disabled 1: Downstream port wakeup enabled.
Page 660 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) USBRST bit is 1, until the bit is cleared to 0 by software. The USBRST bit must be 1 (USB bus reset period) for the time defined in the USB 2.0 specification. Writing 1 to this bit during communication (UACT bit = 1) or during resume processing (RESUME bit = 1) prevents the USBFS from starting USB bus reset processing until both the UACT and RESUME bits become 0.
Page 661 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Value after reset: Symbol Bit name Description b15 to b0 FIFOPORT[15:0]* FIFO Port Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. Note 1.
Page 662 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.6 Endian operation in 8-bit access CFIFOSEL.BIGEND bit D0FIFOSEL.BIGEND bit D1FIFOSEL.BIGEND bit Bits [15:8] Bits [7:0] Access prohibited N + 0 data Access prohibited N + 0 data Note 1. Writing to or reading from an access-prohibited area is not allowed.
Page 663 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Do not specify the same pipe number in the CURPIPE[3:0] bits in the CFIFOSEL, D0FIFOSEL, and D1FIFOSEL registers. When the CURPIPE[3:0] bits in the D0FIFOSEL and D1FIFOSEL registers are set to 0000b, no pipe is selected.
Page 664 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) D0FIFOSEL, D1FIFOSEL Address(es): USBFS.D0FIFOSEL 4009 0028h, USBFS.D1FIFOSEL 4009 002Ch BIGEN RCNT REW DCLRM DREQE — — — — — — CURPIPE[3:0] Value after reset: Symbol Bit name Description b3 to b0 CURPIPE FIFO Port Access Pipe 0 0 0 0: No pipe specification...
Page 665 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) (FIFO Port Access Bit Width) The MBW bit specifies the bit width for accessing the D0FIFO port or D1FIFO port. When the selected pipe is receiving, after a write to these bits starts a data read from the FIFO buffer, do not change the bits until all of the data is read.
Page 666 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description FRDY FIFO Port Ready 0: FIFO port access disabled 1: FIFO port access enabled. BCLR CPU Buffer Clear 0: Does not operate 1: FIFO buffer cleared in the CPU. BVAL Buffer Memory Valid Flag 0: Invalid...
Page 667 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS)  To transmit a short packet, set this flag to 1 after data is written  To transmit a zero-length packet, set this flag to 1 before data is written to the FIFO buffer. The USBFS then switches the FIFO buffer from the CPU to the SIE, enabling transmission.
Page 668 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.8 Interrupt Enable Register 1 (INTENB1) Address(es): USBFS.INTENB1 4009 0032h OVRC DTCHE ATTCH EOFER PDDET BCHGE — — — — — SIGNE SACKE — — — INTE0 Value after reset: Symbol Bit name Description PDDETINTE0...
Page 669 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.9 BRDY Interrupt Enable Register (BRDYENB) Address(es): USBFS.BRDYENB 4009 0036h PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B — — — — — — RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE...
Page 670 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description PIPE1NRDYE NRDY Interrupt Enable for Pipe 1 0: Interrupt output disabled 1: Interrupt output enabled. PIPE2NRDYE NRDY Interrupt Enable for Pipe 2 0: Interrupt output disabled 1: Interrupt output enabled. PIPE3NRDYE NRDY Interrupt Enable for Pipe 3 0: Interrupt output disabled...
Page 671 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description PIPE7BEMPE BEMP Interrupt Enable for Pipe 7 0: Interrupt output disabled 1: Interrupt output enabled. PIPE8BEMPE BEMP Interrupt Enable for Pipe 8 0: Interrupt output disabled 1: Interrupt output enabled. PIPE9BEMPE BEMP Interrupt Enable for Pipe 9 0: Interrupt output disabled...
Page 672 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.13 Interrupt Status Register 0 (INTSTS0) Address(es): USBFS.INTSTS0 4009 0040h VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS DVSQ[2:0] VALID CTSQ[2:0] Value after reset: 0/1* 0/1* Symbol Bit name Description b2 to b0 CTSQ[2:0] Control Transfer Stage...
Page 673 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) VALID (USB Request Reception) In host controller mode, the read value of the VALID bit is invalid. DVSQ[2:0] bits (Device State) The DVSQ[2:0] bits are initialized by a USB bus reset. In host controller mode, the read value is invalid. BRDY (Buffer Ready Interrupt Status)
Page 674 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) RESM (Resume Interrupt Status) In device controller mode, the USBFS sets the RESM bit to 1 when detecting the falling edge of the signal on the USB_DP pin in the suspended state (DVSQ[2:0] = 1xxb). Values read from the RESM bit in host controller mode are invalid.
Page 675 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) the PDDETINT interrupt is generated, eliminate transient elements by reading the PDDETSTS0 bit at least three times through software processing and check that the values read are the same. SACK (Setup Transaction Normal Response Interrupt Status) The SACK bit indicates the status of the setup transaction normal response interrupt in host controller mode.
Page 676 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) interrupt enable bit is set to 1 by software, the USBFS generates the interrupt. The USBFS detects bus detach events based on the USB 2.0 specification. After detecting the DTCH interrupt, the USBFS controls hardware as follows, regardless of the associated interrupt enable bit setting: ...
Page 677 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description PIPE6BRDY BRDY Interrupt Status for Pipe 6* 0: Interrupts are not generated 1: Interrupts are generated. PIPE7BRDY BRDY Interrupt Status for Pipe 7* 0: Interrupts are not generated 1: Interrupts are generated.
Page 678 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.17 BEMP Interrupt Status Register (BEMPSTS) Address(es): USBFS.BEMPSTS 4009 004Ah PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B — — — — — — Value after reset: Symbol Bit name Description PIPE0BEMP BEMP Interrupt Status for Pipe 0...
Page 679 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) FRNM[10:0] bits (Frame Number) The FRNM[10:0] bits indicate the latest frame number for the USBFS after issuing of an SOF packet every 1 ms or writing to the FRNM[10:0] bits at the SOF packet reception. CRCE (Receive Data Error)
Page 680 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) BREQUEST[7:0] bits (Request) The BREQUEST[7:0] bits store the bRequest value of the USB request.  In host controller mode: Set these bits to the value of the USB request data in setup transmission transactions. Do not change the value of the bits while the DCPCTR.SUREQ bit is 1.
Page 681 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) In device controller mode, the USBINDX stores the received wIndex value. In host controller mode, the USBINDX sets the wIndex value to be transmitted. USBINDX is initialized by a USB bus reset. WINDEX[15:0] bits (Index) The WINDEX[15:0] bits hold the value of a USB request.
Page 682 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.23 DCP Configuration Register (DCPCFG) Address(es): USBFS.DCPCFG 4009 005Ch SHTNA — — — — — — — — — — — — — — Value after reset: Symbol Bit name Description b3 to b0 —...
Page 683 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.24 DCP Maximum Packet Size Register (DCPMAXP) Address(es): USBFS.DCPMAXP 4009 005Eh DEVSEL[3:0] — — — — — MXPS[6:0] Value after reset: Symbol Bit name Description b6 to b0 MXPS[6:0] Maximum Packet Size* These bits set the maximum amount of data (maximum packet size) in payloads for the DCP.
Page 684 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.25 DCP Control Register (DCPCTR) Address(es): USBFS.DCPCTR 4009 0060h SUREQ SQCLR SQSET SQMO BSTS SUREQ — — — — PBUSY — — CCPL PID[1:0] Value after reset: Symbol Bit name Description b1, b0 PID[1:0] Response PID...
Page 685 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) a. Check that the FIFO buffer is empty (or empty the buffer) while the DVSTCTR0.UACT bit is 1 and PID is NAK.  Set PID[1:0] bits to 01b (BUF). The USBFS then executes the IN transaction. The USBFS changes the PID[1:0] setting as follows: ...
Page 686 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) SQSET (Sequence Toggle Bit Set* The SQSET bit specifies DATA1 as the expected value of the sequence toggle bit for the next transaction during a DCP transfer. Do not set the SQCLR and SQSET bits to 1 simultaneously. SQCLR (Sequence Toggle Bit Clear* The SQCLR bit specifies DATA0 as the expected value of the sequence toggle bit for the next transaction during a DCP...
Page 687 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.26 Pipe Window Select Register (PIPESEL) Address(es): USBFS.PIPESEL 4009 0064h — — — — — — — — — — — — PIPESEL[3:0] Value after reset: Symbol Bit name Description b3 to b0 PIPESEL[3:0] Pipe Window Select 0 0 0 0: No pipe selected...
Page 688 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.27 Pipe Configuration Register (PIPECFG) Address(es): USBFS.PIPECFG 4009 0068h SHTNA TYPE[1:0] — — — BFRE DBLB — — — EPNUM[3:0] Value after reset: Symbol Bit name Description b3 to b0 EPNUM[3:0] Endpoint Number* These bits specify the endpoint number for the selected pipe.
Page 689 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) EPNUM[3:0] bits (Endpoint Number* The EPNUM[3:0] bits specify the endpoint number for the selected pipe. Setting 0000b indicates the pipe is not used. Set these bits so that the combination of the DIR and EPNUM[3:0] settings is different from those for other pipes. The EPNUM[3:0] bits can be set to 0000b for all pipes.
Page 690 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.28 Pipe Maximum Packet Size Register (PIPEMAXP) Address(es): USBFS.PIPEMAXP 4009 006Ch DEVSEL[3:0] — — — MXPS[8:0] Value after reset: Symbol Bit name Description  Pipes 1 and 2: b8 to b0 MXPS[8:0] Maximum Packet Size* 1 byte (001h) to 256 bytes (100h)
Page 691 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.29 Pipe Cycle Control Register (PIPEPERI) Address(es): USBFS.PIPEPERI 4009 006Eh — — — IFIS — — — — — — — — — IITV[2:0] Value after reset: Symbol Bit name Description b2 to b0 IITV[2:0] Interval Error Detection Interval...
Page 692 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.30 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9) PIPEnCTR (n = 1 to 5) Address(es): USBFS.PIPE1CTR 4009 0070h, USBFS.PIPE2CTR 4009 0072h, USBFS.PIPE3CTR 4009 0074h, USBFS.PIPE4CTR 4009 0076h, USBFS.PIPE5CTR 4009 0078h BSTS INBUF ATREP ACLRM SQCLR SQSET SQMO...
Page 693 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) The USBFS changes the PIPEnCTR.PID[1:0] setting in the following cases:  The USBFS sets PID to NAK on recognizing completion of the transfer when the selected pipe is receiving and the PIPECFG.SHTNAK bit for the selected pipe is set to 1 by software ...
Page 694 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.8 Operation of the USBFS based on the PID[1:0] setting in device controller mode (2 of 2) Transfer direction PID[1:0] value Transfer type (DIR bit) USBFS operation 01b (BUF) Bulk Receiving direction Receives data and returns ACK in response to the OUT token from (DIR = 0)
Page 695 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.9 Data cleared by the USBFS when ACLRM = 1 (2 of 2) Number Data cleared by setting the ACLRM bit Situations requiring data clear Interval count value when the selected pipe is the isochronous When resetting the interval count value transfer type Internal flags related to the PIPECFG.BFRE bit...
Page 696 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.10 BSTS bit operation DIR value BFRE value DCLRM value BSTS bit function Set to 1 when received data can be read from the FIFO buffer, and set to 0 on completion of data read Setting prohibited Set to 1 when received data can be read from the FIFO buffer, and set to 0 when...
Page 697 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) PID[1:0] bits (Response PID) The PID[1:0] bits specify the response type for the next transaction of the selected pipe. The default PID[1:0] setting is NAK. Change the PID[1:0] setting to BUF to use the selected pipe for USB transfer. Table 28.7 Table 28.7...
Page 698 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.11 Data cleared by USBFS when ACLRM = 1 Number Data cleared by setting the ACLRM bit Situations requiring data clear All data in the FIFO buffer allocated to the selected pipe When initializing the selected pipe The interval count value when the selected pipe is for When resetting the interval count value...
Page 699 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.32 PIPEn Transaction Counter Register (PIPEnTRN) (n = 1 to 5) Address(es): USBFS.PIPE1TRN 4009 0092h, USBFS.PIPE2TRN 4009 0096h, USBFS.PIPE3TRN 4009 009Ah, USBFS.PIPE4TRN 4009 009Eh, USBFS.PIPE5TRN 4009 00A2h TRNCNT[15:0] Value after reset: Symbol Bit name Description...
Page 700 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.33 Device Address n Configuration Register (DEVADDn) (n = 0 to 5) Address(es): USBFS.DEVADD0 4009 00D0h, USBFS.DEVADD1 4009 00D2h, USBFS.DEVADD2 4009 00D4h, USBFS.DEVADD3 4009 00D6h, USBFS.DEVADD4 4009 00D8h, USBFS.DEVADD5 4009 00DAh —...
Page 701 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) VDDUSBE (USB Reference Power Supply Circuit On/Off Control) The USB reference power supply circuit generates the reference voltage for battery charging. Set this bit to 1 when using the battery charging function. VDCEN (USB Regulator On/Off Control)
Page 702 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) V) is applied to D+. IDPSINKE0 (D+ Pin 0.6 V Input Detection (Comparator and Sink) Control) When the IDPSINKE0 bit is set to 1 in device controller mode, the USBFS detects whether VDMSRC (0.6 V), output from the device to D-, is connected to D+ (DCP) by the host.
Page 703 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.12 Control settings for the USBFS data bus resistors SYSCFG register settings USB data bus control DRPD bit DPRPU Bit DMRPU Bit D– Function Open Open When resistors not used Open Pull-up When operating as the device controller at full-speed...
Page 704 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Input the same voltage as VCC 3.8 V to 5.5 V VCC to VCC_USB_LDO VCC_USB_LDO USB LDO Regulator 1.0 µF VCC_USB Control USB_DP USB_DM VDCEN VDDUSBE USB Module Control Register (USBMC) USBFS Transceiver This MCU...
Page 705 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Input the same voltage as VCC 4.0 V to 5.5 V VCC to VCC_USB_LDO VCC_USB_LDO USB LDO Regulator 1.0 µF VCC_USB Control USB_DP USB_DM VDCEN VDDUSBE USB Module Control Register (USBMC) USBFS Transceiver This MCU...
Page 706 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) External connection OTG power supply IC USB0_EXICEN SHDN# USB0_VBUSEN OFFVBUS# USB0_OVRCURA STATUS1 USB0_OVRCURB STATUS2 USB0_ID ID_OUT ID_IN VBUS USB transceiver AB connector VBUS USB0_DP USB0_DM D– : Output impedance : Pull-up resistor : Pull-down resistor Figure 28.5 Example OTG connection in self-powered state...
Page 707 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.6 shows an example of functional connection of the USB connector in the self-powered state. External connection 100  USB_VBUS 1 M  0.1 µF transceiver VBUS USB_DP USB_DM D– : Output impedance : Pull-up resistor Note 1.
Page 708 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.7 shows an example of host connection of the USB connector. External connection USB_VBUSEN Non-OTG power supply IC for USB USB_OVRCURA host VBUS At least 120 µF A connector transceiver VBUS USB_DP USB_DM...
Page 709 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.8 shows an example of functional connection of the USB connector in bus-powered state. External connection Each system power B connector supply (3.3 V) System power Regulator VBUS supply (3.3 V) USB_VBUS transceiver USB_DP...
Page 710 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.9 shows an example of functional connection of the USB connector in bus-powered state 2. External connection B connector USB_VBUS VBUS transceiver USB_DP USB_DM D– : Output impedance : Pull-up resistor Figure 28.9 Example device connection in bus-powered state 2 The examples of external circuits given in this section are simplified circuits, and their operation in every system is not...
Page 711 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.10 shows an example of functional connection of the USB connector with Battery Charging Rev 1.2 supported. External connection Charging IC supporting Battery Charging Spec 1.2 SCL0 SCL0 Charging battery SDA0 SDA0 USB_VBUS...
Page 712 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.13 Interrupt sources (1 of 2) Applicable Bit to be controller Name Interrupt source function Status flag  A change in the state of the USB_VBUS input pin was VBINT VBUS interrupt Host or INTSTS0.VBSTS...
Page 713 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.13 Interrupt sources (2 of 2) Applicable Bit to be controller Name Interrupt source function Status flag  A setup transaction normal response (ACK) was SACK Normal setup Host — operation received ...
Page 714 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.11 shows the circuits related to the USBFS interrupts. USBFS_USBR USB bus reset detected INTENB0 INTSTS0 VBSE Set_Address detected VBINT Set_Configuration RSME USBFS_USBI detected RESM SOFE Suspended state detected SOFR Control Write Data Stage DVSE DVST...
Page 715 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.14 shows the interrupts generated by the USBFS. Table 28.14 USBFS interrupts Interrupt DMAC name Interrupt status flag activation activation Priority D0FIFO DMA transfer request 0 Possible Possible High D1FIFO DMA transfer request 1 Possible Possible...
Page 716 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) interrupt status of the selected pipe can be set to 0 by writing 0 to the associated PIPEnBRDY bit through software. In this case, write 1 to the PIPEnBRDY bits for the other pipes. Clear the BRDY status before accessing the FIFO buffer. (2) When SOFCFG.BRDYM = 0 and PIPECFG.BFRE = 1 With these settings, the USBFS generates a BRDY interrupt on completion of reading all data for a single transfer using the receiving pipe, and sets 1 to the bit in BRDYSTS associated with the selected pipe.
Page 717 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.12 shows the timing of BRDY interrupt generation. (1) Example of zero-length packet reception or data packet reception when BFRE = 0 (single-buffer mode) Token Packet Data Packet ACK Handshake USB bus FIFO buffer status Ready for reception...
Page 718 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.3.2 NRDY interrupt On generating an internal NRDY interrupt request for the pipe whose PID bits are set to BUF by software, the USBFS sets the associated PIPEnNRDY bit in NRDYSTS to 1. If the associated bit in NRDYENB is set to 1 by software, the USBFS sets the INTSTS0.NRDY bit to 1 and generates a USBFS interrupt.
Page 719 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) (2) In device controller mode (a) For transmitting pipes  When an IN token is received while there is no data to be transmitted in the FIFO buffer. In this case, the USBFS generates a NRDY interrupt request on reception of the IN token and sets the NRDYSTS.PIPEnNRDY bit to 1.
Page 720 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) (1) Example of data transmission (single-buffer mode) IN token packet USB bus NAK handshake FIFO buffer status Ready for write access (there is no data to be transmitted) NRDY interrupt (NRDYSTS.PIPEnNRDY bit) An NRDY interrupt is generated (2) Example of data reception: OUT token reception (single-buffer mode) OUT token packet...
Page 721 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) controller mode. (2) For receiving pipes When a successfully-received data packet size exceeds the specified maximum packet size. In this case, the USBFS generates a BEMP interrupt request, sets the associated BEMPSTS.PIPEnBEMP bit to 1, discards the received data, and changes the associated PID[1:0] setting for the pipe to STALL (11b).
Page 722 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Suspended state detection (DVST is set to 1) Powered Suspended state state (DVSQ = 000b) (DVSQ = 100b) Resume (RESM is set to 1) USB bus reset detection (DVST is set to 1) Suspended state detection USB bus reset detection (DVST is set to 1)
Page 723 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS)  An IN token is received at the status stage  A data packet with DATAPID = DATA0 is received at the status stage. (2) Control write transfer errors  An IN token is received but no ACK is returned in response to the OUT token at the data stage ...
Page 724 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.3.8 Resume interrupt In device controller mode, a resume interrupt is generated when the device state is the Suspend state and the USB bus state has changed (from J-state to K-state, or from J-state to SE0). Recovery from the Suspend state is detected by means of the resume interrupt.
Page 725 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS)  Sets the DVSTCTR0.UACT bit for the port in which the EOFERR interrupt is detected to 0  Puts the port in which the EOFERR interrupt is generated into the idle state. 28.3.3.16 Portable device detection interrupt A portable device detection interrupt is generated when the USBFS detects a level change (high to low or low to high) in...
Page 726 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Do not change the following registers and bits when USB communication is enabled (PID = BUF):  Bits in DCPCFG and DCPMAXP  SQCLR and SQSET bits in DCPCTR  Bits in PIPECFG, PIPEMAXP, and PIPEPERI ...
Page 727 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.4.5 Transaction counter for pipes 1 to 5 in the receiving direction When the specified number of transactions is complete in the data packet receiving direction, the USBFS recognizes that the transfer ended. Two transaction counters are provided: ...
Page 728 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS)  If transaction counting ends when the SHTNAK bit is set to 1 for bulk transfers.  BUF setting: The USBFS does not write this setting.  STALL setting: PID = STALL is set in the following cases, and issuing of tokens is automatically stopped: ...
Page 729 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) To transition from OUT-NAK mode to normal mode, cancel OUT-NAK mode while pipe operation is disabled (NAK). Next enable pipe operation (BUF). In normal mode, reception of OUT data is enabled. 28.3.4.11 Null auto response mode For bulk IN transfer pipes, zero-length packets are continuously transmitted when the PIPEnCTR.ATREPM bit is set to...
Page 730 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Single or double buffering can be selected for pipes 1 to 5 in the PIPECFG.DBLB bit. Table 28.19 Buffer clearing methods Mode for automatically clearing FIFO buffer Clearing FIFO buffer on the the FIFO buffer after reading the Auto buffer clear mode for clearing mode...
Page 731 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) register determines the direction. Table 28.21 FIFO port access by pipe Pipe Access method Port that can be used CPU access CFIFO port register  CFIFO port register Pipe 1 to Pipe 9 CPU access ...
Page 732 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.9.1 Control transfers in host controller mode (1) Setup stage The USQREQ, USBVAL, USBINDX, and USBLENG registers are used to transmit USB requests for setup transactions. Writing the setup packet data to the registers and then writing 1 to the DCPCTR.SUREQ bit transmits the specified data for the setup transaction.
Page 733 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) = BUF cannot be set, and the data stage cannot be terminated. Using the VALID bit function, the USBFS can suspend the current request being processed when it receives a new USB request during a control transfer and return a response to the latest request.
Page 734 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.11.1 Interval counter for interrupt transfers in host controller mode Specify the transaction interval for interrupt transfers in the PIPEPERI.IITV[2:0] bits. (1) The USBFS issues interrupt transfer tokens based on this interval.Counter initialization The USBFS initializes the interval counter under the following conditions: ...
Page 735 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) In device controller mode:  There is no data to be sent in the FIFO buffer at token receive time in the IN (transmitting) direction  The FIFO buffer is full at token receive time in the OUT (receiving) direction. (e) Interval errors In device controller mode, the following cases are treated as an interval error: ...
Page 736 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) counter enables the functions as shown in Table 28.25. In host controller mode, the USBFS generates the token issuance timing, and the interval counter operation is the same as that for interrupt transfers. Table 28.25 Interval counter function in device controller mode Transfer...
Page 737 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) USB bus PID bit setting Token Token Token Token Token Token Token Token not issued not issued issued not issued issued not issued issued Interval counter started Figure 28.18 Token issuance when IITV = 1 When the selected pipe is set for isochronous transfers, the USB carries out the following operation in addition to controlling the token issuance interval.
Page 738 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) USB bus PID bit setting Token Token Token Token Token reception reception reception reception is not waited is not waited is waited is waited Interval counter started Figure 28.19 Relationship between frames and expected token reception when IITV = 0 ...
Page 739 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) When the FIFO buffer is ready to transmit data when an IN token is received, the data is transferred and a normal response is returned. However, if the FIFO buffer cannot transmit data, a zero-length packet is transmitted and an underrun error occurs.
Page 740 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS)  When IITV = 0: The buffer flush operation starts from the first frame after the pipe is enabled.  When IITV ≠ 0: The buffer flush operation starts after the first normal transaction. Figure 28.22 shows an example buffer flush.
Page 741 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.13 SOF Interpolation Function In device controller mode, if packet reception is disabled at intervals of 1 ms because the SOF packet is corrupted or missing, the USBFS interpolates the SOF. SOF interpolation begins when the USBE and SCKE bits in SYSCFG are set to 1 and an SOF packet is received.
Page 742 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.14.2 Transfer schedule This section describes the transfer scheduling within a frame of the USBFS. After the USBFS sends an SOF, the transfer is performed in the following sequence: 1. Execution of periodic transfers: A pipe is searched for in the order of pipe 1 ...
Page 743 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) current of 7 to 13 µA on the D+ line. The other method is to wait for 300 to 900 ms after VBUS is detected. Note 2. During primary detection, when the voltage on the D- line is detected to be 0.25 to 0.4 V or above and 0.8 to 2.0 V or below, the target device is recognized as the host device for battery charging, that is, charging downstream port.
Page 744 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Detect VBUS Set BATCHGE0 bit Set CNEN bit Data Contact Detection Data Contact Set RPDME0 bit (software waiting method) Detection Set IDPSRCE0 bit (hardware Wait for a minimum 300 ms? detection Use LNST[1:0] for method) check...
Page 745 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 2. Enable the portable device detection circuit. 3. Monitor the portable device detection signal, and start driving the D- line if the detection signal is high. 4. Detect when the portable device detection signal is a low level and stop driving the D- line. The following processing can also be used in associated with the battery charging specification: a.
Page 746 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.25 show the process flow for steps 1 to 4 and the process flow for steps a to b, respectively. Portable device detection processing Drive VBUS PD detection circuit enabled (IDPSINKE0 = 1) PD detection interrupt enabled (PDDETINTE = 1)
Page 747 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) D-Line Drive Control Drive VBUS Set VDMSRCE0 bit Connection detected? Clear VDMSRCE0 bit (within 10 ms) Normal state Disconnection detected? Set VDMSRCE0 bit (within 200 ms) Figure 28.26 Process flow for operating as charging downstream port (steps a to b) 28.4 Usage Notes 28.4.1...
Page 748 S3A3 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) unexpected interrupt might occur at this time, causing the VBINT and OVRCR bits in INTSTS0 and INTSTS1, or other interrupt status flags to set to 1. To avoid a malfunction, always clear the INTSTS0 and INTSTS1 registers after setting up the ports.
Page 749 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Serial Communications Interface (SCI) 29.1 Overview The Serial Communications Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces:  Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter (ACIA))  8-bit clock synchronous interface ...
Page 750 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.1 SCI specifications (2 of 2) Parameter Description Asynchronous mode Data length 7, 8, or 9 bits Transmission stop bit 1 or 2 bits Parity Even parity, odd parity, or no parity Receive error detection Parity, overrun, and framing errors Hardware flow control...
Page 751 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Internal Module data bus peripheral bus SCMR RDRHL FRDRH TDRHL FTDRH MDDR SSR/SSR_SMCI/ FRDRL FTDRL PCLK SSR_FIFO PCLK/4 Baud rate SCR/SCR_SMCI generator PCLK/16 SMR/SMR_SMCI Clock RXDn/SCLn/ SEMR PCLK/64 SPMR MISOn Parity addition SCIn_TEI (interrupt request) SCIn_TXI...
Page 752 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.2 SCI I/O pins (2 of 2) Channel Pin name Input/Output Function SCI1 SCK1 Input/Output SCI1 clock input/output RXD1/SCL1/ Input/Output SCI1 receive data input MISO1 SCI1 I C clock input/output SCI1 slave transmit data input/output TXD1/SDA1/ Input/Output SCI1 transmit data output...
Page 753 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.2.2 Receive Data Register (RDR) Address(es): SCI0.RDR 4007 0005h, SCI1.RDR 4007 0025h, SCI2.RDR 4007 0045h, SCI3.RDR 4007 0065h, SCI4.RDR 4007 0085h, SCI9.RDR 4007 0125h Value after reset: RDR is an 8-bit register that stores receive data. When one frame of serial data is received, it is transferred from RSR to RDR, and the RSR register can receive more data.
Page 754 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.2.4 Receive FIFO Data Register H, L, HL (FRDRH, FRDRL, FRDRHL) Receive FIFO Data Register H (FRDRH) Address(es): SCI0.FRDRH 4007 0010h, SCI1.FRDRH 4007 0030h Receive FIFO Data Register L (FRDRL) Address(es): SCI0.FRDRL 4007 0011h, SCI1.FRDRL 4007 0031h Receive FIFO Data Register HL...
Page 755 S3A3 User’s Manual 29. Serial Communications Interface (SCI) no received data in FRDRH and FRDRL, the value is undefined. When FRDRH and FRDRL are full, subsequent serial receive data is lost. The CPU can read from FRDRH and FRDRL but cannot write to them. Reading 1 from the RDF, ORER, or DR flags of the FRDRH register is the same as reading those bits from the SSR_FIFO register.
Page 756 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.2.7 Transmit FIFO Data Register H, L, HL (FTDRH, FTDRL, FTDRHL) Transmit FIFO Data Register H (FTDRH) Address(es): SCI0.FTDRH 4007 000Eh, SCI1.FTDRH 4007 002Eh Transmit FIFO Data Register L (FTDRL) Address(es): SCI0.FTDRL 4007 000Fh, SCI1.FTDRL 4007 002Fh Transmit FIFO Data Register HL...
Page 757 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.2.9 Serial Mode Register (SMR) for Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI0.SMR 4007 0000h, SCI1.SMR 4007 0020h, SCI2.SMR 4007 0040h, SCI3.SMR 4007 0060h, SCI4.SMR 4007 0080h, SCI9.SMR 4007 0120h STOP CKS[1:0] Value after reset:...
Page 758 S3A3 User’s Manual 29. Serial Communications Interface (SCI) STOP (Stop Bit Length) The STOP bit selects the stop bit length in transmission. In reception, only the first stop bit is checked regardless of this bit setting. If the second stop bit is 0, it is treated as the start bit of the next transmit frame.
Page 759 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Note 1. n is the decimal notation of the value of n in BRR. See section 29.2.17, Bit Rate Register (BRR). Note 2. Writable only when SCR_SMCI.TE = 0 and SCR_SMCI.RE = 0 (both serial transmission and reception are disabled). The SMR_SMCI register sets the communication format and clock source for the on-chip baud rate generator.
Page 760 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.2.11 Serial Control Register (SCR) for Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI0.SCR 4007 0002h, SCI1.SCR 4007 0022h, SCI2.SCR 4007 0042h, SCI3.SCR 4007 0062h, SCI4.SCR 4007 0082h, SCI9.SCR 4007 0122h MPIE TEIE CKE[1:0]...
Page 761 S3A3 User’s Manual 29. Serial Communications Interface (SCI) CKE[1:0] bits (Clock Enable) The CKE[1:0] bits select the clock source and SCKn pin function. TEIE (Transmit End Interrupt Enable) The TEIE bit enables or disables an SCIn_TEI interrupt request. Set the TEIE bit to 0 to disable the interrupt request. In simple IIC mode, SCIn_TEI is allocated to the interrupt on completion of issuing a start, restart, or stop condition (STI).
Page 762 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.2.12 Serial Control Register for Smart Card Interface Mode (SCR_SMCI)(SCMR.SMIF = 1) Address(es): SCI0.SCR_SMCI 4007 0002h, SCI1.SCR_SMCI 4007 0022h, SCI2.SCR_SMCI 4007 0042h, SCI3.SCR_SMCI 4007 0062h, SCI4.SCR_SMCI 4007 0082h, SCI9.SCR_SMCI 4007 0122h MPIE TEIE CKE[1:0] Value after reset:...
Page 763 S3A3 User’s Manual 29. Serial Communications Interface (SCI) When reception is halted by setting the RE bit to 0, the ORER, FER, and PER flags in SSR_SMCI are not affected and the previous values are saved. (Transmit Enable) The TE bit enables or disables serial transmission. When this bit is set to 1, serial transmission starts by writing transmit data to TDR.
Page 764 S3A3 User’s Manual 29. Serial Communications Interface (SCI) MPBT (Multi-Processor Bit Transfer) The MPBT bit selects the multi-processor bit in the transmit frame. bit (Multi-Processor) The MPB bit holds the value of the multi-processor bit in the reception frame. This bit does not change when the SCR.RE bit is 0.
Page 765 S3A3 User’s Manual 29. Serial Communications Interface (SCI)  When the next data is received before the receive data that does not have a parity error and a framing error is read from RDR. In RDR, data received prior to an overrun error occurrence is kept, but data received after the overrun error occurrence is lost.
Page 766 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description TEND Transmit End Flag 0: A character is transmitted R/(W)* 1: Character transfer is complete. Parity Error Flag 0: No parity error occurred R/(W)* 1: A parity error occurred. Framing Error Flag 0: No framing error occurred R/(W)*...
Page 767 S3A3 User’s Manual 29. Serial Communications Interface (SCI) when the address match function is disabled (DCCR.DCME = 0). [Setting condition]  When data is received and a parity error is detected, and the address match function is disabled (DCCR.DCME = 0). [Clearing condition] ...
Page 768 S3A3 User’s Manual 29. Serial Communications Interface (SCI) TDFE flag (Transmit FIFO Data Empty Flag) The TDFE flag indicates that when data is transferred from FTDRHL into TSR, the amount of data in FTDRHL has fallen below the specified transmit triggering number, and writing of transmit data to FTDRHL is enabled. [Setting conditions] ...
Page 769 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [Setting conditions]  When the SCR_SMCI.TE bit = 0 to disable serial transmission. When the SCR_SMCI.TE bit changes from 0 to 1, the TEND flag is not affected and keeps the value 1. ...
Page 770 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [Setting condition]  When the reception ends normally, and receive data is forwarded from the RSR register to the RDR register. [Clearing conditions]  When 0 is written to RDRF after 1 is read ...
Page 771 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description CHR1 Character Length 1 Only valid only in asynchronous mode* R/W* Selects the character length in combination with the CHR bit in SMR: CHR1 CHR 0: Transmit/receive in 9-bit data length 1: Transmit/receive in 9-bit data length 0: Transmit/receive in 8-bit data length (initial value) 1: Transmit/receive in 7-bit data length*...
Page 772 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.2.17 Bit Rate Register (BRR) Address(es): SCI0.BRR 4007 0001h, SCI1.BRR 4007 0021h, SCI2.BRR 4007 0041h, SCI3.BRR 4007 0061h, SCI4.BRR 4007 0081h, SCI9.BRR 4007 0121h Value after reset: BRR is an 8-bit register that adjusts the bit rate. As each SCI channel has independent baud rate generator control, different bit rates can be set for each.
Page 773 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.6 Calculating widths at high and low level for SCL Mode Formula (result in seconds) Width at high level 2n-1 (N+1) × 4 × 2 × 7 × (minimum value) PCLK × 10 Width at low level 2n-1 (N+1) ×...
Page 774 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.9 Examples of BRR settings for different bit rates in asynchronous mode (1) (2 of 2) Operating frequency PCLK (MHz) 9.8304 12.288 Bit rate (bps) Error (%) n Error (%) n Error (%) n Error (%) n Error (%)
Page 775 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.11 Maximum bit rate for each operating frequency in asynchronous mode (1 of 2) SEMR settings SEMR settings Maximum Maximum PCLK BGDM ABCS ABCSE bit rate PCLK BGDM ABCS ABCSE bit rate (MHz) (bps) (MHz)
Page 776 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.11 Maximum bit rate for each operating frequency in asynchronous mode (2 of 2) SEMR settings SEMR settings Maximum Maximum PCLK BGDM ABCS ABCSE bit rate PCLK BGDM ABCS ABCSE bit rate (MHz) (bps) (MHz)
Page 777 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.13 BRR settings for different bit rates in clock synchronous and simple SPI modes (2 of 2) Operating frequency PCLK (MHz) Bit rate (bps) — — — — — — 7.5 M Space: Setting prohibited.
Page 778 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.16 Maximum bit rate for each operating frequency in smart card interface mode, S = 32 (2 of 2) PCLK (MHz) Maximum bit rate (bps) 18.00 281250 20.00 312500 25.00 390625 30.00 468750 33.00...
Page 779 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Operating frequency PCLK (MHz) Min. widths at Min. widths at Min. widths at Min. widths at Bit rate high/low level high/low level high/low level high/low level (bps) for SCL (μs) for SCL (μs) for SCL (μs) for SCL (μs) 10 k...
Page 780 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.19 Relationship between MDDR setting (M) and bit rate (B) when bit rate modulation function is used (2 of 2) SEMR settings BGDM ABCS ABCSE Mode BRR setting Error Clock synchronous, PCLK ×...
Page 781 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Operating frequency PCLK (MHz) 19.6608 Bit rate BGDM Error BGDM Error BGDM Error (bps) 38400 (256)* 0.00 –0.01 0.00 57600 0.00 0.03 0.00 115200 0.00 0.03 0.00 230400 0.00 0.03 0.00 460800 0.00 0.14 0.00...
Page 782 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Note 1. Writable only when TE in SCR/SCR_SMCI = 0 and RE in SCR/SCR_SMCI = 0 (both serial transmission and reception are disabled). SEMR selects the clock source for 1-bit period in asynchronous mode. BRME (Bit Rate Modulation Enable)
Page 783 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.2.20 Noise Filter Setting Register (SNFR) Address(es): SCI0.SNFR 4007 0008h, SCI1.SNFR 4007 0028h, SCI2.SNFR 4007 0048h, SCI3.SNFR 4007 0068h, SCI4.SNFR 4007 0088h, SCI9.SNFR 4007 0128h — — — — — NFCS[2:0] Value after reset: Symbol Bit name Description...
Page 784 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description b7 to b3 IICDL[4:0] SDA Delay Output Select The following cycles are of the clock signal from the on-chip baud rate R/W* generator: 0 0 0 0 0: No output delay 0 0 0 0 1: 0 to 1 cycle 0 0 0 1 0: 1 to 2 cycles 0 0 0 1 1: 2 to 3 cycles...
Page 785 S3A3 User’s Manual 29. Serial Communications Interface (SCI) The SCLn clock signal is not synchronized if this bit is 0. The SCLn clock signal is generated according to the rate selected in the BRR regardless of the level input on the SCLn pin. Set this bit to 1 except during debugging.
Page 786 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [Setting condition]  Writing 1 to the bit. [Clearing condition]  When generation of a restart condition is complete. IICSTPREQ (Stop Condition Generation When a stop condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b and set the IICSTPREQ bit to 1.
Page 787 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description — Reserved The read value is undefined — Reserved This bit is read as 0 b5, b4 — Reserved The read values are undefined b7, b6 — Reserved These bits are read as 0 SISR monitors the state in simple IIC mode.
Page 788 S3A3 User’s Manual 29. Serial Communications Interface (SCI) (Master Slave Select) The MSS bit selects between master and slave operation in simple SPI mode. The functions of the TXDn and RXDn pins are reversed when the MSS bit is set to 1, so that data is received through the TXDn pin and transmitted through the RXDn pin.
Page 789 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description b11 to b8 RTRG[3:0] Receive FIFO Data Trigger Valid only in asynchronous mode, including multi-processor, or Number clock synchronous mode: 0000: Trigger number 0 1111: Trigger number 15. b15 to b12 RSTRG[3:0] RTS Output Active Trigger...
Page 790 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.2.27 FIFO Data Count Register (FDR) Address(es): SCI0.FDR 4007 0016h, SCI1.FDR 4007 0036h — — — T[4:0] — — — R[4:0] Value after reset: Symbol Bit name Description b4 to b0 R[4:0] Receive FIFO Data Count Indicates the amount of receive data stored in FRDRHL.
Page 791 S3A3 User’s Manual 29. Serial Communications Interface (SCI) ORER (Overrun Error Flag) The ORER bit reflects the value in SSR_FIFO.ORER. FNUM[4:0] bits (Framing Error Count) The value in the FNUM[4:0] bits indicates the amount of data stored in the FRDRHL register with a framing error. PNUM[4:0] bits (Parity Error...
Page 792 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description IDSEL ID Frame Select Valid only in asynchronous mode, including multi-processor: 0: Always compare data regardless of the MPB bit value 1: Compare data when the MPB bit is 1 (ID frame). DCME Data Compare Match Valid only in asynchronous mode, including multi-processor:...
Page 793 S3A3 User’s Manual 29. Serial Communications Interface (SCI) The write value should be 0 for any mode other than asynchronous mode. 29.2.31 Serial Port Register (SPTR) Address(es): SCI0.SPTR 4007 001Ch, SCI1.SPTR 4007 003Ch, SCI2.SPTR 4007 005Ch, SCI3.SPTR 4007 007Ch, SCI4.SPTR 4007 009Ch, SCI9.SPTR 4007 013Ch SPB2I...
Page 794 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Idle state (mark state) Serial data Start bit Transmit/receive data Parity bit Stop bit 1 bit 7, 8 or 9 bits 1 or 0 bit 1 or 2 bits One unit of transfer data (character or frame) Figure 29.2 Data format in asynchronous serial communications with 8-bit data, parity bit, and 2 stop bits 29.3.1...
Page 795 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.22 Serial transfer formats (asynchronous mode) (2 of 2) SCMR setting SMR setting Serial transfer format and frame length CHR1 STOP 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data —...
Page 796 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Because receive data is sampled on the rising edge of the 8th pulse of the base clock, data is latched at the middle of each bit, as shown in...
Page 797 S3A3 User’s Manual 29. Serial Communications Interface (SCI) When the SCI uses its internal clock, the clock can be output from the SCKn pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, Figure 29.4 shows.
Page 798 S3A3 User’s Manual 29. Serial Communications Interface (SCI)  After reception is complete, if it is terminated with SCR.RE = 0 without reading the RDR register, then RTS remains high. Read the SCR register for dummy after writing SCR.RE = 0. (b) FIFO selected ...
Page 799 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Data (ID1) Data (Data1) Start bit Stop bit Start bit Parity Parity SCIn_AM SCI0_DCUF DCME DCMF flag SCIn_RXI interrupt flag (ICU.IELSRn.IR) RDRF flag DPER flag DFER flag If compare mismatched, Not stored to RDR if CDR flag is not set setting value mismatched to receive data...
Page 800 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Data (Data0) Data (ID1) Start bit Stop bit Start bit MPB Stop bit Start bit SCIn_AM SCI0_DCUF DCME DCMF flag SCIn_RXI interrupt flag (ICU.IELSRn.IR) RDRF flag DPER flag DFER flag Not stored to RDR, if CDR If compare is mismatched, setting value is flag is not set...
Page 801 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.3.7 SCI Initialization in Asynchronous Mode Before transmitting and receiving data, start by writing the initial value 00h to SCR, and then continue through the SCI procedure (select non-FIFO or FIFO) shown in Figure 29.7 Figure 29.8.
Page 802 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Start initialization [ 1 ] Set FCR.FM, TFRST, and RFRST to 1. This enables FIFO mode and clears the FIFOs. Set the trigger values in FCR.TTRG[3:0], RTRG[3:0], and RSTRG[3:0] bits. Set SCR.TIE, RIE, TE, RE, and TEIE to 0 Set FCR.FM, TFRST, and RFRST to 1 [ 1 ] [ 2 ]...
Page 803 S3A3 User’s Manual 29. Serial Communications Interface (SCI) requests are in use, set TIE to 0 (an SCIn_TXI interrupt request is disabled) and TEIE to 1 (an SCIn_TEI interrupt request is enabled) in the SCR register after the last of the data to be transmitted is written to the TDR from the handling routine for SCIn_TXI requests.
Page 804 S3A3 User’s Manual 29. Serial Communications Interface (SCI) CTSn_RTSn pin Data Start bit Parity bit Stop bit D7 0/1 1 D7 0/1 Idle state 0 D0 D1 0 D0 (mark state) SCR.TE bit 1 frame SCIn_TXI interrupt flag (IELSRn.IR SSR.TEND flag Data written to TDR in SCIn_TXI interrupt Data written to TDR in...
Page 805 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI Initialization: Set data transmission. After SCR.TE is set to 1, 1 is output for a frame (preamble), and transmission is enabled. [ 1 ] Initialization [ 2 ] Transmit data write to TDR by an SCIn_TXI interrupt Start transmission request:...
Page 806 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Data Register Transmit data in FTDRH, FTDRL Length Setting FTDRHL FTDRH FTDRL SCMR. SMR. CHR1 7 bits — 7-bit transmit data — — — — — — — — 8 bits 8-bit transmit data —...
Page 807 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: Initialization [ 1 ] Set data transmission. After SCR.TE is set to 1, 1 is output for a frame Start data transmission (preamble), and transmission is enabled. [ 2 ] Transmit data write to FTDRL* by an SCIn_TXI interrupt...
Page 808 S3A3 User’s Manual 29. Serial Communications Interface (SCI) SCR is 1, an SCIn_ERI interrupt request is generated. 5. If a frame error is detected, the FER flag in the SSR is set to 1 and receive data is transferred to RDR .
Page 809 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 0 before resuming reception. In addition, be sure to read RDR or RDRHL during overrun error processing. When reception is forcibly terminated by setting the RE bit in SCR to 0 during operation, read RDR or RDRHL because the received data that is not read might be left in RDR or RDRHL.
Page 810 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] Initialization SCI initialization: Set data reception. Start data reception [2] [3] Receive error processing and break detection: If a receive error occurs, an SCIn_ERI interrupt is [ 2 ] generated.
Page 811 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 3 ] Error processing SSR.ORER flag = 1? Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR. In combination with step [ 7 ], this will make correct reception of the next frame possible.
Page 812 S3A3 User’s Manual 29. Serial Communications Interface (SCI) In asynchronous mode, 0 is written to the MPB flag bit in the FRDRH register. Data that corresponds to the data length is written to FRDRH and FRDRL. Unused bits are written as 0. Read in order from FRDRH to FRDRL. If software reads FRDRL, SCI updates FER, PER and receive data (RDAT[8:0]) in the FRDRL register with the next data.
Page 813 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] Initialization SCI initialization: Start data reception Set data reception. [2] [3] Receive error processing and break detection: If a receive error occurs, an SCIn_ERI interrupt Read ORER , PER, FER, and DR [ 2 ] flags in SSR_FIFO is generated.
Page 814 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 3 ] Error processing SSR_FIFO.ORER flag = 1? Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: FRDRHL is read and a space is made in FRDRHL. SSR_FIFO.FER flag = 1? Break? Framing error processing...
Page 815 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.4 Multi-Processor Communications Function The multi-processor communication function enables the SCI to transmit and receive data by sharing a communication line between multiple processors, using asynchronous serial communication in which the multi-processor bit is added. In multi-processor communication, a unique ID code is allocated to each receiving station.
Page 816 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Transmitting station Communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) (MPB = 1) Serial data (MPB = 1) (MPB = 0) ID transmission cycle =...
Page 817 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Initialization [ 1 ] [ 1 ] SCI initialization: Start data transmission Set data transmission. After SCR.TE is set to 1, 1 is output for a frame, and transmission is enabled. SCIn_TXI interrupt? [ 2 ] [ 2 ] SCIn_TXI interrupt request:...
Page 818 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Data Register Transmit data in FTDRH, FTDRL Length Setting FTDRHL FTDRH FTDRL SCMR. SMR. CHR1 7 bits MPBT — — — — — — — — 7-bit transmit data 8 bits — —...
Page 819 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Initialization [ 1 ] [ 1 ] SCI initialization: Start data transmission Set data transmission. After SCR.TE is set to 1, 1 is output for a frame, and transmission is enabled. SCIn_TXI interrupt? [ 2 ] [ 2 ] Transmit data write to FTDRHL by an SCIn_TXI interrupt...
Page 820 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Data (ID1) Data (Data1) Start bit Stop bit Start bit Stop bit Idle state (mark state) MPIE SCIn_RXI interrupt flag (IELSRn.IR RDR value MPIE = 0 SCIn_RXI interrupt RDR data read in MPIE bit set to 1 again SCIn_RXI interrupt request (multi-processor...
Page 821 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: [ 1 ] Initialization Set data reception. [ 2 ] ID reception cycle: Set SCR.MPIE to 1 and wait for ID reception. Start data reception [ 3 ] SCI status confirmation and reception and comparison of ID: [ 2 ]...
Page 822 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 5 ] Error processing SSR.ORER flag = 1? Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR . In combination with step [ 7 ], this makes correct reception of the next frame possible.
Page 823 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Data Register Receive data in FRDRH, FRDRL Length Setting FRDRHL FRDRH FRDRL SCMR. SMR. CHR1 7 bits — ORER 7-bit receive data 8 bits — ORER 8-bit receive data Don’t 9 bits —...
Page 824 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: Initialization [ 1 ] Set data reception. [ 2 ] ID reception cycle: Start data reception Set SCR.MPIE to 1 and wait for ID reception. [ 3 ] SCI status confirmation and reception and comparison of ID: [ 2 ]...
Page 825 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Within the SCI, the transmitter and receiver are independent units, enabling full-duplex communications by using a common clock. Both the transmitter and the receiver have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer.
Page 826 S3A3 User’s Manual 29. Serial Communications Interface (SCI) (a) Non-FIFO selected when all of the following conditions are satisfied  The value of the RE or TE bit in SCR is 1  When serial communication is enabled  There is no received data available to be read (when SCR.RE is 1) ...
Page 827 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] Set FCR.FM to 0. Start initialization [ 2 ] Set the clock selection in SCR. Set SCR.TIE, RIE, TE, RE, and TEIE to 0 [ 3 ] Set SIMR1.IICM to 0. Set SPMR.CKPH and CKPOL.
Page 828 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Start initialization [ 1 ] Set FCR.FM, TFRST, and RFRST to 1. This enables FIFO mode and clears the FIFOs. Set the trigger values in FCR.TTRG[3:0], RTRG[3:0], and RSTRG[3:0]. Set SCR.TIE, RIE, TE, RE, and TEIE to 0 [ 2 ] Set the clock selection in SCR.
Page 829 S3A3 User’s Manual 29. Serial Communications Interface (SCI) data to be transmitted is written to TDR. 3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when the clock output mode is specified, and in synchronization with the input clock when the use of an external clock is specified. Output of the clock signal is suspended until the input CTSn_RTSn signal is low while the CTSE bit in SPMR register is 1.
Page 830 S3A3 User’s Manual 29. Serial Communications Interface (SCI) CTSn_RTSn pin Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 SCR.TE bit SCIn_TXI interrupt flag (IELSRn.IR SSR.TEND flag SCIn_TXI interrupt SCIn_TXI interrupt SCIn_TXI interrupt request generated Request generated request generated Data written to TDR in Data written to TDR in...
Page 831 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: [ 1 ] Initialization Set data transmission. [ 2 ] Writing transmit data to TDR by an SCIn_TXI interrupt Start transmission request: When transmit data is transferred from TDR to TSR, a transmit data empty interrupt (SCIn_TXI) request is [ 2 ] generated.
Page 832 S3A3 User’s Manual 29. Serial Communications Interface (SCI) signal is suspended until the CTSn_RTSn input signal is low and while the CTSE bit in SPMR is 1. 4. The SCI checks whether non-transmitted data remains in FTDRL on the output of the stop bit. 5.
Page 833 S3A3 User’s Manual 29. Serial Communications Interface (SCI) In serial data reception, the SCI operates as follows: 1. When the value of SCR.RE becomes 1, the CTSn_RTSn pin goes low. 2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock input or output, and stores the receive data in RSR.
Page 834 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Synchronization clock Serial data Bit 6 Bit 7 Bit 0 Bit 7 Bit 0 SCIn_RXI interrupt flag (IELSRn.IR* SSR.ORER flag SCIn_RXI SCIn_RXI interrupt SCIn_ERI interrupt request RDR data read in interrupt request request generated generated by overrun error SCIn_RXI interrupt...
Page 835 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: Initialization [ 1 ] Set the input port for pins to be used as RXDn pins. Start data reception [ 2 ] [ 3 ] Receive error processing: If a receive error occurs, read SSR.ORER, perform the relevant error processing, and set [ 2 ]...
Page 836 S3A3 User’s Manual 29. Serial Communications Interface (SCI) In serial data reception, the SCI operates as follows: 1. When the value of SCR.RE becomes 1, the CTSn_RTSn pin goes low. 2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock input or output, and stores the receive data in RSR.
Page 837 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: Initialization [ 1 ] Set the input port for pins to be used as RXDn pins. Start data reception [ 2 ] [ 3 ] Receive error processing: If a receive error occurs, read the SSR_FIFO.ORER flag, perform the relevant error [ 2 ]...
Page 838 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.5.6 Simultaneous Serial Data Transmission and Reception in Clock Synchronous Mode (1) Non-FIFO selected Figure 29.43 shows an example flow for simultaneous serial transmission and reception operations in clock synchronous mode. After initializing the SCI, use the following procedure for simultaneous serial data transmission and reception operations.
Page 839 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: [ 1 ] Initialization The TXDn pin can act as the output pin for transmitted data and the RXDn pin can act as the input pin for received data at the same time. Start data transmission/reception [ 2 ] Transmit data write:...
Page 840 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 3. Set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously using a single instruction. [ 1 ] SCI initialization: [ 1 ] Initialization The TXDn pin can act as the output pin for transmitted data and the RXDn pin can act as the input pin for received data at the same time.
Page 841 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Setting the TE and RE bits in SCR_SMCI to 1 with an IC card disconnected enables closed-loop transmission or reception allowing self-diagnosis. To supply an IC card with the clock pulses generated by the SCI, input the SCKn pin output to the CLK pin of an IC card.
Page 842 S3A3 User’s Manual 29. Serial Communications Interface (SCI) In normal transmission/reception Output from the transmitting station When a parity error occurs Output from the transmitting station Output from the receiving station Start bit D0 to D7: Data bits Parity bit Error signal Figure 29.46 Data formats in smart card interface mode...
Page 843 S3A3 User’s Manual 29. Serial Communications Interface (SCI) (Z) state D7 D6 D5 D4 D3 D2 D1 D0 Dp Figure 29.48 Inverse convention with SDIR in SCMR = 1, SINV in SCMR = 1, and PM in SMR_SMCI = 1 29.6.3 Block Transfer Mode Block transfer mode differs from non-block transfer mode of the smart card interface mode in the following respects:...
Page 844 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 372 clocks 372 clocks 186 clocks 186 clocks 371 0 Base clock Start bit Receive data (RXDn) Synchronization sampling timing Data sampling timing Figure 29.49 Receive data sampling timing in smart card interface mode for clock frequency 372 times the bit rate 29.6.5 SCI Initialization...
Page 845 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Start initialization Set SCR_SMCI.TIE, RIE, TE, RE, TEIE, [ 1 ] and CKE[1:0] to 0 [ 1 ] Stop the communication and initialize SKE[1:0]. Set SIMR1.IICM to 0 [ 2 ] Set SCMR.SMIF to 1 [ 2 ] Set to smart card interface mode.
Page 846 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Connect port SCKn starts when CKE[0]=1 SCKn Hi-Z Smart card interface mode Mode SCR.TE Preamble period Data transfer TXDn Hi-Z Write transfer data TE=1 Figure 29.51 Example timing of data transmission in smart card interface mode 29.6.6 Serial Data Transmission (Except in Block Transfer Mode) Serial data transmission in smart card interface mode (except in block transfer mode) is different from that in non-smart...
Page 847 S3A3 User’s Manual 29. Serial Communications Interface (SCI) (n + 1)-th transfer nth transfer frame Retransfer frame frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 D6 D7 Dp Ds D0 D1 D2 D3 D4 SCIn_TXI interrupt signal SSR_SMCI.ERS flag Figure 29.52...
Page 848 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Start Initialization Start data transmission SSR_SMCI.ERS flag = 0? Error processing SCIn_TXI interrupt Write transmit data to TDR Write all transmit data SSR_SMCI.ERS flag = 0? Error processing SCIn_TXI interrupt? Set SCR_SMCI.TIE, RIE, and TE to 0 Figure 29.54 Example flow of smart card interface transmission...
Page 849 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Figure 29.56 shows an example flow of serial data reception. All the processing steps are automatically performed using an SCIn_RXI interrupt request to activate the DMAC or DTC. In reception, setting the RIE bit to 1 allows an SCIn_RXI interrupt request to be generated. The DMAC or DTC is activated by an SCIn_RXI interrupt request if the SCIn_RXI interrupt request is specified as a source of DMAC or DTC activation beforehand, allowing the transfer of receive data.
Page 850 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Start Initialization Start data reception SSR_SMCI.ORER = 0 and SSR_SMCI.PER = 0? Error processing SCIn_RXI interrupt? Read data from RDR All data received? Set SCR_SMCI.RIE and RE to 0 Figure 29.56 Example flow of smart card interface reception 29.6.8 Clock Output Control When the GM bit in SMR_SMCI is set to 1, the clock output can be controlled by the CKE[1: 0] bits in SCR_SMCI.
Page 851 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Base clock CKE[0] When GM = 0 When GM = 1 Figure 29.57 Clock output control 29.7 Operation in Simple IIC Mode Simple I C bus format is composed of 8 data bits and an acknowledge bit. By continuing into a slave-address frame after a start condition or restart condition, a master device can specify a slave device as a partner for communications.
Page 852 S3A3 User’s Manual 29. Serial Communications Interface (SCI) SDAn D7-D1 D7-D1 D7-D1 SCLn R/W# DATA DATA Figure 29.59 C bus timing when SLA is 7 bits Indicates a start condition, when the master device changes the level on the SDAn line from high to low while the SCLn line is high.
Page 853 S3A3 User’s Manual 29. Serial Communications Interface (SCI)  When the high level on the SCLn line is detected, the setup time for the stop condition is set as half of a bit period at the bit rate determined by the BRR setting ...
Page 854 S3A3 User’s Manual 29. Serial Communications Interface (SCI) SCLn output from the other device SCLn line Internal SCLn clock Clock driving transfer internally Counting of the period Counting of the period Counting of the period at high level starts at high level starts at low level starts Counting stops while the SCLn line Counting stops until the SCLn line is...
Page 855 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.7.4 SCI Initialization in Simple IIC Mode Before transferring data, write the initial value of 00h to SCR and initialize the interface as shown in the example in Figure 29.63. Before making any changes to the operating mode or transfer format, be sure to set SCR to its initial value. In simple IIC mode, the open-drain setting for the communication ports should be made on the port side.
Page 856 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Start condition Slave address (7 bits) Transmitted data Stop condition SCLn SDAn ACK/NACK SCIn_TXI interrupt flag (IELSRn.IR* Acceptance of SCIn_TXI interrupt request STI interrupt flag Generation of SCIn_TXI interrupt request Generation of SCIn_TXI interrupt request (IELSRn.IR* Generation of STI interrupt Acceptance of request...
Page 857 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Initialization [1] Initialization for simple IIC mode: For transmission, set the SCR.RIE bit to 0 to disable RXI and ERI interrupts requests. Start of transmission Simultaneously set SIMR3.IICSTAREQ to 1 and [2] Generate a start condition. SIMR3.IICSCLS[1:0] and IICSDAS[1:0] to 01b STI interrupt? [3] Writing to TDR:...
Page 858 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.7.6 Master Reception in Simple IIC Mode Figure 29.67 shows an example of master reception operation in simple IIC mode and Figure 29.68 shows an example flow of master reception. The value of the IICINTM bit in SIMR2 register is assumed to be 1 using reception and transmission interrupts. In simple IIC mode, the transmit data empty interrupt (SCIn_TXI) is generated when communication of one frame completes, unlike the timing of the SCIn_TXI interrupt request generation during clock synchronous transmission.
Page 859 S3A3 User’s Manual 29. Serial Communications Interface (SCI) [1] Initialization for simple IIC mode: Initialization Set the RIE bit in SCR to 0. Start of reception Simultaneously set SIMR3.IICSTAREQ to 1 and [2] Generate a start condition. SIMR3.IICSCLS[1:0] and IICSDAS[1:0] to 01b STI interrupt? Set SIMR3.IICSTIF to 0 and set SIMR3.IICSCLS[1:0] and IICSDAS[1:0] to 00b...
Page 860 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 29.8 Operation in Simple SPI Mode As an extended function, the SCI supports a simple SPI mode that handles transfer in one or multiple master devices and multiple slave devices. To place the SCI in simple SPI mode, use the settings for clock synchronous mode (SCMR.SMIF = 0, SIMR1.IICM = 0, SMR.CM = 1) and set the SSE bit in SPMR register to 1.
Page 861 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.24 Pin states by mode and input level on SSn pin Mode Input on SSn pin State of TXDn pin State of RXDn pin State of SCKn pin Master mode* High Output for data Input for received data Clock output*...
Page 862 S3A3 User’s Manual 29. Serial Communications Interface (SCI) One unit of transfer data (character or frame) (1) When CKPH = 0 SSn pin (slave) SCKn pin (CKPOL = 0) SCKn pin (CKPOL = 1) MOSIn pin Bit 0 Bit 1 Bit 2 Bit 3 Bit 4...
Page 863 S3A3 User’s Manual 29. Serial Communications Interface (SCI) are set to 0 and 160 respectively, in asynchronous mode. In this example, the cycle of the base clock is evenly corrected (256/160) and the bit rate is also corrected (160/256). Note: Enabling an internal clock causes bias and expansion.
Page 864 S3A3 User’s Manual 29. Serial Communications Interface (SCI) If the TIE bit in SCR register is 1, an SCIn_TXI interrupt request is generated when transmit data is transferred from TDR or TDRHL to the TSR. An SCIn_TXI interrupt request can also be generated using a single instruction to set the TE and TIE bits to 1 in the SCR simultaneously.
Page 865 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Table 29.25 SCI interrupt sources with non-FIFO selected (2 of 2) Name Interrupt source Interrupt flag Interrupt enable DTC activation DMAC activation SCIn_AM Address match DCMF — Possible Possible SCIn_TXI Transmit data empty TDRE Possible Possible...
Page 866 S3A3 User’s Manual 29. Serial Communications Interface (SCI) SCIn_ERI interrupt request is issued to the CPU instead. The error flag must be cleared. 29.10.5 Interrupts in Simple IIC Mode Table 29.28 lists the interrupt sources in simple IIC mode. The STI interrupt is allocated to the transmit end interrupt (SCIn_TEI) request.
Page 867 S3A3 User’s Manual 29. Serial Communications Interface (SCI) number is in the receive FIFO buffer, 15 ETUs elapse when FIFO is selected and FCR.DRES is 1. (2) Receive data full event output  Indicates that ACK is detected if the IICINTM bit in SIMR2 register is 0 in simple IIC mode ...
Page 868 S3A3 User’s Manual 29. Serial Communications Interface (SCI) When SEMR.ABCS = 0 and SEMR.ABCSE = 0, the cycle is 1/16 the period of 1 transfer bit. When SEMR.ABCS = 1 and SEMR.ABCSE = 0, the cycle is 1/8 the period of 1 transfer bit. When SEMR.ABCSE = 1, the cycle is 1/6 the period of 1 transfer bit.
Page 869 S3A3 User’s Manual 29. Serial Communications Interface (SCI) To transmit data in the same transmission mode after cancellation of the low power state: Set the TE bit to 1. 2. Read SSR/SSR_FIFO/SSR_SMCI. 3. Write data to TDR sequentially to start data transmission. To transmit data with a different transmission mode, initialize the SCI first.
Page 870 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Data Transmission [ 1 ] Data being transmitted is lost. Data can [ 1 ] All data transmitted? be normally transmitted from the CPU by setting the TE bit in SCR/SCR_SMCI to 1, reading SSR/SSR_FIFO/SSR_SMCI, and writing in Software Standby mode.
Page 871 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Transition to Software Standby Software Standby mode mode canceled PmnPFS.PMR bit setting (TXDn pin function setting) SPTR.SPB2IO SCR/SCR_SMCI.TE The level at transition to software standby mode is retained SCKn output pin TXDn output pin The level before Port input/output Stop...
Page 872 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Data reception [ 1 ] Received data is invalid. [ 1 ] SCIn_RXI interrupt? Read receive data in RDR SCR/SCR_SMCI.RE = 0 Transition to Software Standby mode [ 2 ] Setting for the module-stop state is included. [ 2 ] Cancel Software Standby mode Change operating mode?
Page 873 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Data reception [ 1 ] Received data is invalid. [ 1 ] SCIn_RXI interrupt? Read receive data in RDR SCR/SCR_SMCI.RE = 0 [ 2 ] Setting for the module-stop state is included. Set the operation mode to cancel software standby Set compare data to CDR...
Page 874 S3A3 User’s Manual 29. Serial Communications Interface (SCI) (2) FIFO selected After a framing error is detected and when the SCI detects that continuous receive data is 0 for one frame, reception stops. When a framing error is detected, a break can be detected by reading the RXDMON bit value in SPTR. After the RXD signal is in the mark state and the break ends, reception of data to FRDRHL resumes.
Page 875 S3A3 User’s Manual 29. Serial Communications Interface (SCI) Set t  1 PCLK cycle + data output delay time for the slave (tDO) + setup time for the master (tSU) before transmission is started when the external clock is used. Update TDR before bit [7] is started to transmit when continuous transmission is performed on the external clock.
Page 876 S3A3 User’s Manual 29. Serial Communications Interface (SCI) (2) Reading data from RDR (FRDRHL) When using the DMAC or DTC to read RDR and RDRHL, be sure to set the receive data full interrupt (SCIn_RXI) as the activation source of the relevant SCI channel. 29.14.8 Notes on Starting Transfer At the point where transfer starts when the Interrupt Status flag, IELSRn.IR, in the ICU is 1, follow the procedure in this...
Page 877 S3A3 User’s Manual 29. Serial Communications Interface (SCI) 1 PCLK cycle + data output delay time for the slave (tDO) + setup time for the master (tSU) Also, wait at least 5 PCLK cycles from the input of the low level on the SSn pin to the start of the external clock input.
Page 878 S3A3 User’s Manual 30. I C Bus Interface (IIC) C Bus Interface (IIC) 30.1 Overview The MCU has a 3-channel I C Bus Interface (IIC). The IIC module conforms with and provides a subset of the NXP I (Inter-Integrated Circuit) bus interface functions. Table 30.1 lists the IIC specifications, Figure 30.1...
Page 879 S3A3 User’s Manual 30. I C Bus Interface (IIC) Table 30.1 IIC specifications (2 of 2) Parameter Description  Transfer error or event occurrences (arbitration detection, NACK, timeout, start or restart condition, or Event link function (output) stop condition)  Receive data full, including matching with a slave address ...
Page 880 S3A3 User’s Manual 30. I C Bus Interface (IIC) Power supply for pull-up SCLin SCLout# SDAin SDAout# (Master) SCLin SCLin SCLout# SCLout# SDAin SDAin SDAout# SDAout# (Slave 1) (Slave 2) Figure 30.2 I/O pin connection to the external circuit (I C bus configuration example) The input level of the signals for IIC is CMOS when I C bus is selected (ICMR3.SMBS = 0), or TTL when SMBus is...
Page 881 S3A3 User’s Manual 30. I C Bus Interface (IIC) 30.2 Register Descriptions 30.2.1 C Bus Control Register 1 (ICCR1) Address(es): IIC0.ICCR1 4005 3000h, IIC1.ICCR1 4005 3100h, IIC2.ICCR1 4005 3200h IICRST SOWP SCLO SDAO SCLI SDAI Value after reset: Symbol Bit name Description SDAI SDA Line Monitor...
Page 882 S3A3 User’s Manual 30. I C Bus Interface (IIC) IICRST (IIC Bus Interface Internal Reset) The IICRST bit initiates an internal state reset of the IIC. Setting this bit to 1 initiates an IIC reset or internal reset. Whether an IIC reset or internal reset is initiated is determined by setting this bit in combination with the ICE bit. Table 30.3 lists the IIC resets.
Page 883 S3A3 User’s Manual 30. I C Bus Interface (IIC) 30.2.2 C Bus Control Register 2 (ICCR2) Address(es): IIC0.ICCR2 4005 3001h, IIC1.ICCR2 4005 3101h, IIC2.ICCR2 4005 3201h BBSY — — Value after reset: Symbol Bit name Description — Reserved This bit is read as 0. The write value should be 0. Start Condition Issuance 0: Do not issue a start condition request Request...
Page 884 S3A3 User’s Manual 30. I C Bus Interface (IIC) [Clearing conditions]  When 0 is written to the RS bit  When a restart condition is issued (a start condition is detected)  When the AL (arbitration-lost) flag in ICSR2 is set to 1 ...
Page 885 S3A3 User’s Manual 30. I C Bus Interface (IIC)  When the AL (arbitration-lost) flag in ICSR2 is set to 1  When the R/W# bit appended to the slave address is set to 1 in master mode  In slave mode, on a match between the received address and the address enabled in ICSER when the value of the received R/W# bit is 0, including when the received address is the general call address ...
Page 886 S3A3 User’s Manual 30. I C Bus Interface (IIC) 30.2.3 C Bus Mode Register 1 (ICMR1) Address(es): IIC0.ICMR1 4005 3002h, IIC1.ICMR1 4005 3102h, IIC2.ICMR1 4005 3202h MTWP CKS[2:0] BCWP BC[2:0] Value after reset: Symbol Bit name Description b2 to b0 BC[2:0] Bit Counter R/W*...
Page 887 S3A3 User’s Manual 30. I C Bus Interface (IIC) 30.2.4 C Bus Mode Register 2 (ICMR2) Address(es): IIC0.ICMR2 4005 3003h, IIC1.ICMR2 4005 3103h, IIC2.ICMR2 4005 3203h DLCS SDDL[2:0] — TMOH TMOL TMOS Value after reset: Symbol Bit name Description TMOS Timeout Detection Time Select 0: Select long mode 1: Select short mode.
Page 888 S3A3 User’s Manual 30. I C Bus Interface (IIC) held high and the timeout function is enabled (ICFER.TMOE bit = 1). SDDL[2:0] bits (SDA Output Delay Counter) The SDDL[2:0] bits can be used to delay the SDA output. This counter works with the clock source selected by the DLCS bit.
Page 889 S3A3 User’s Manual 30. I C Bus Interface (IIC) NF[1:0] bits (Noise Filter Stage Select) The NF[1:0] bits select the number of stages in the digital noise filter. For details on the digital noise filter function, see section 30.6, Digital Noise Filter Circuits.
Page 890 S3A3 User’s Manual 30. I C Bus Interface (IIC) Note: When the WAIT bit value is to be read, be sure to first read the ICDRR. SMBS (SMBus/I C Bus Select) Setting the SMBS bit to 1 selects the SMBus and enables the HOAE bit in ICSER. 30.2.6 C Bus Function Enable Register (ICFER)
Page 891 S3A3 User’s Manual 30. I C Bus Interface (IIC) NACKE (NACK Reception Transfer Suspension Enable) The NACKE bit specifies whether to continue or discontinue the transfer operation when NACK is received from the slave device in transmit mode. Normally, set this bit to 1. When NACK is received with the NACKE bit set to 1, the next transfer operation is suspended.
Page 892 S3A3 User’s Manual 30. I C Bus Interface (IIC) When this bit is set to 1, if the received slave address matches the general call address, the IIC recognizes the received slave address as the general call address independently of the slave addresses set in SARLy and SARUy (y = 0 to 2) and performs data receive operation.
Page 893 S3A3 User’s Manual 30. I C Bus Interface (IIC) ALIE (Arbitration-Lost Interrupt Request Enable) The ALIE bit enables or disables arbitration-lost interrupt (ALIn) requests when the AL flag in ICSR2 is set to 1. To cancel an ALI interrupt request, set the AL flag or the ALIE bit to 0. STIE (Start Condition Detection Interrupt Request Enable)
Page 894 S3A3 User’s Manual 30. I C Bus Interface (IIC) Symbol Bit name Description Host Address Detection Flag 0: Host address not detected R/(W) 1: Host address detected. This bit is set to 1 when the received slave address matches the host address (0001 000b).
Page 895 S3A3 User’s Manual 30. I C Bus Interface (IIC)  When the first frame received immediately after a start condition or restart condition is detected matches a value of (device ID (1111 100b) + 0 [W]), with the DIDE bit in ICSER set to 1 (device ID address detection is enabled). This flag is set to 1 on the rising edge of the 9 SCL clock cycle in the frame.
Page 896 S3A3 User’s Manual 30. I C Bus Interface (IIC) Symbol Bit name Description TEND Transmit End Flag 0: Data being transmitted R/(W) 1: Data transmission complete. TDRE Transmit Data Empty Flag 0: ICDRT contains transmit data 1: ICDRT contains no transmit data. Note 1.
Page 897 S3A3 User’s Manual 30. I C Bus Interface (IIC) Table 30.4 Relationship between arbitration-lost generation sources and arbitration-lost enable functions ICFER ICSR2 MALE NALE SALE Error Arbitration-lost generation source × × Start condition When internal SDA output state does not match SDAn line level when a issuance error start condition is detected while the ST bit in ICCR2 is 1 When ST in ICCR2 is set to 1 and BBSY in ICCR2 set to 1...
Page 898 S3A3 User’s Manual 30. I C Bus Interface (IIC) in ICCR2 set to 0. [Clearing conditions]  When 0 is written to the RDRF bit after reading RDRF = 1  When data is read from ICDRR  When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset. TEND flag (Transmit End...
Page 899 S3A3 User’s Manual 30. I C Bus Interface (IIC) Symbol Bit name Description WUIE Wakeup Interrupt Request Enable 0: Wakeup Interrupt Request (IIC0_WUI) disabled 1: Wakeup Interrupt Request (IIC0_WUI) enabled. Wakeup Function Enable 0: Wakeup function disabled 1: Wakeup function enabled. Table 30.5 Wakeup mode IICRST...
Page 900 S3A3 User’s Manual 30. I C Bus Interface (IIC)  When a stop condition is detected with a wakeup event undetected. WUASYF flag (Wakeup Function Asynchronous Operation Status Flag) This flag can place the IIC in PCLKB asynchronous operation when the wakeup function is enabled (ICWUR.WUE = 1). [Setting condition] ...
Page 901 S3A3 User’s Manual 30. I C Bus Interface (IIC) SVA[6:0] bits (7-Bit Address/10-Bit Address Lower Bits) When the 7-bit address format is selected (SARUy.FS = 0), the SVA[6:0] bits function as a 7-bit address. When the 10- bit address format is selected (SARUy.FS = 1), these bits combined with the SVA0 bit to form the lower 8 bits of a 10-bit address.
Page 902 S3A3 User’s Manual 30. I C Bus Interface (IIC) automatic SCL low-hold operation (see section 30.9, Automatic Low-Hold Function for SCL). When the IIC is used only in slave mode, the BRL[4:0] bits must be set to a value longer than the data setup time * If the digital noise filter is enabled (the NFE bit in ICFER is 1), set the ICBRL register to a value at least one greater than the number of stages in the noise filter.
Page 903 S3A3 User’s Manual 30. I C Bus Interface (IIC) Table 30.6 Example of ICBRH/ICBRL settings for transfer rate when SCLE = 0 BRH[4:0] BRL[4:0] Transfer rate (kbps) CKS[2:0] (ICBRH) (ICBRL) PCLKB (MHz) NF[1:0] Computation expression 15 (EFh) 18 (F2h) 9 (E9h) 20 (F4h) Table 30.7 Example of ICBRH/ICBRL settings for transfer rate when SCLE = 1 and NFE = 0...
Page 904 S3A3 User’s Manual 30. I C Bus Interface (IIC) 30.2.19 C Bus Shift Register (ICDRS) — — — — — — — — Value after reset: ICDRS is an 8-bit shift register to transmit and receive data. During transmission, transmit data is transferred from ICDRT to ICDRS and is sent from the SDAn pin.
Page 905 S3A3 User’s Manual 30. I C Bus Interface (IIC) Start condition. The master device drives the SDAn line low from high while the SCLn line is high. SLA: Slave address, by which the master device selects a slave device R/W#: Indicates the direction of data transfer: from the slave device to the master device when R/W# is 1, or from the master device to the slave device when R/W# is 0 Acknowledge.
Page 906 S3A3 User’s Manual 30. I C Bus Interface (IIC) Initial settings Set ICE in ICCR1 to 0 SCLn, SDAn pins not driven Set IICRST in ICCR1 to 1 IIC reset Set ICE in ICCR1 to 1 Internal reset, SCLn and SDAn pins in active state Set SARLy and SARUy.
Page 907 S3A3 User’s Manual 30. I C Bus Interface (IIC) communications, write 1 to the ICCR2.SP bit to issue a stop condition. To transmit data with an address in the 10-bit format, start by writing 1111 0b, the 2 upper bits of the slave address, and W to ICDRT as the first address transmission.
Page 908 S3A3 User’s Manual 30. I C Bus Interface (IIC) Master transmission [1] Initial settings. Initial settings ICCR2.BBSY = 0? [2] Check I C bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.NACKF = 0? ICSR2.TDRE = 1? [3] Transmit slave address and W (first byte). [4] Check ACK and set transmit data.
Page 909 S3A3 User’s Manual 30. I C Bus Interface (IIC) Automatic low-hold (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + W) Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF ICDRT...
Page 910 S3A3 User’s Manual 30. I C Bus Interface (IIC) SCLn SDAn A/NA DATA n-2 DATA n-1 DATA n BBSY Transmit data (DATA n) Transmit data (DATA n-1) TDRE TEND RDRF DATA n-1 ICDRT DATA n DATA n-2 ICDRS DATA n-1 DATA n XXXX (Initial value/final receive data) ICDRR...
Page 911 S3A3 User’s Manual 30. I C Bus Interface (IIC) the R bit to place the IIC in master receive mode. 4. Dummy read ICDRR after confirming that the RDRF flag in ICSR2 is 1. Doing so causes the IIC to start output of the SCL clock and start data reception.
Page 912 S3A3 User’s Manual 30. I C Bus Interface (IIC) Master reception starts Initial settings (1) Initial settings. ICCR2.BBSY = 0? (2) Check I C bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.TDRE = 1? Write the ICDRT register (3) Transmit the slave address followed by R and check ACK.
Page 913 S3A3 User’s Manual 30. I C Bus Interface (IIC) Master reception Initial settings [1] Initial settings. ICCR2.BBSY = 0? [2] Check I C bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.TDRE = 1? Write data to ICDRT [3] Transmit the slave address followed by R and check ACK.
Page 914 S3A3 User’s Manual 30. I C Bus Interface (IIC) Automatic low hold Master transmit mode Master receive mode (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + R) TDRE Receive data (7-bit address + R) Receive data (DATA 1) TEND RDRF...
Page 915 S3A3 User’s Manual 30. I C Bus Interface (IIC) Automatic low hold (WAIT) Automatic low hold (WAIT) SCLn NACK SDAn DATA n-2 DATA n-1 DATA n BBSY TDRE Receive data (DATA n-2) Receive data (DATA n-1) Receive data (DATA n) TEND RDRF XXXX (last data for transmission...
Page 916 S3A3 User’s Manual 30. I C Bus Interface (IIC) Slave transmission [1] Initial settings. Initial settings ICSR2.NACKF = 0? ICSR2.TDRE = 1? Write data to ICDRT [2], [3] Check ACK and set transmit data. Checking of ACK is not required immediately after the address is received. All data transmitted? ICSR2.TEND = 1? Read ICDRR...
Page 917 S3A3 User’s Manual 30. I C Bus Interface (IIC) Slave receive mode Slave transmit mode Automatic low hold (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (DATA 2) Transmit data (DATA 1) TDRE TEND RDRF...
Page 918 S3A3 User’s Manual 30. I C Bus Interface (IIC) 30.3.6 Slave Receive Operation In a slave receive operation, the master device outputs the SCL clock and transmit data, and the IIC returns acknowledgments as a slave device. Figure 30.18 shows an example of slave reception. Figure 30.19 Figure 30.20 show the timing of operations in slave...
Page 919 S3A3 User’s Manual 30. I C Bus Interface (IIC) Automatic low hold (to prevent failure to receive data) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY TDRE Receive data (7-bit address + W) Receive data (DATA 1) TEND RDRF AASy ICDRT...
Page 920 S3A3 User’s Manual 30. I C Bus Interface (IIC) 30.4 SCL Synchronization Circuit To generate the SCL clock, the IIC starts counting the value for the high-level period specified in ICBRH when it detects a rising edge on the SCLn line and drives the SCLn line low when it completes counting. When the IIC detects the falling edge of the SCLn line, it starts counting the value for the low-level period specified in ICBRL, and then stops driving the SCLn line (releases the line) when it completes counting.
Page 921 S3A3 User’s Manual 30. I C Bus Interface (IIC) 30.5 SDA Output Delay Function The IIC module provides a function for delaying output on the SDA line. The delay can be applied to all output on the SDA line, including issuing of the start, restart, and stop conditions, data, and the ACK and NACK signals. With this function, SDA output is delayed from the detection of a falling edge of the SCL signal to ensure that the SDA signal is output within the interval during which the SCL clock is low.
Page 922 S3A3 User’s Manual 30. I C Bus Interface (IIC) level matches the output level of the number of effective flip-flop circuit stages as selected in the NF[1:0] bits in ICMR3, the signal level is seen in the subsequent stage. If the signal levels do not match, the previous value is saved. If the ratio between the frequency of the internal operating clock (PCLKB) and the transfer rate is small, for example, for data transfer at 400 kbps with PCLKB at 4 MHz, the digital noise filter might lead to the elimination of the required signals as noise.
Page 923 S3A3 User’s Manual 30. I C Bus Interface (IIC) 7-bit address format: Slave reception SCLn SDAn 7-bit slave address Data (DATA 1) Data (DATA 2) BBSY Address match AASy Receive data (7-bit address) Receive data (DATA 1) TDRE RDRF Read ICDRR Read ICDRR (Dummy read [7-bit address]) (DATA 1)
Page 924 S3A3 User’s Manual 30. I C Bus Interface (IIC) [In the case of SAR0L : 7-bit address, SAR1L : 7-bit address, SAR2 : 10-bit address (1)] 1 to 8 7-bit slave address (SAR0L) R/W# DATA 7-bit slave address (SAR1L) R/W# BBSY Address mismatch AAS0...
Page 925 S3A3 User’s Manual 30. I C Bus Interface (IIC) [General call address reception] Data (DATA 1) Data (DATA 2) BBSY AAS0 Receive data (7-bit address) Receive data (DATA 1) AAS1 AAS2 General call address match (0000 000b + W) RDRF Read ICDRR Read ICDRR (Dummy read [7-bit address])
Page 926 S3A3 User’s Manual 30. I C Bus Interface (IIC) [Device-ID reception] Address BBSY Slave address match AASy Device-ID match (1111 100b + R) Device-ID match (1111 100b + W) Receive data (7-bit address/lower 10 bits) TDRE RDRF Read ICDRR (Dummy read [7-bit address/lower 10 bits]) [When address received after a restart condition is detected does not match the device-ID ] 7-bit slave address (other station) Address...
Page 927 S3A3 User’s Manual 30. I C Bus Interface (IIC) [Host address reception] SCLn SDAn Data (DATA 1) Data (DATA 2) BBSY AAS0 Receive data (7-bit address) Receive data (DATA 1) AAS1 AAS2 Host address match (0001 000b) RDRF Read ICDRR Read ICDRR (Dummy read [7-bit address]) (DATA 1)
Page 928 S3A3 User’s Manual 30. I C Bus Interface (IIC)  When the wakeup function is enabled, do not use the timeout function  If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, for example IRQn, the WUF flag is not set to 1.
Page 929 S3A3 User’s Manual 30. I C Bus Interface (IIC) IIC normal operation BBSY = 0 [1] Wait until I C bus is free and stay in standby state. MST = 0 & TRS = 0 (Slave receive) IICRST = 0 (& ICE = 1) [2] Negate internal reset (if asserted).
Page 930 S3A3 User’s Manual 30. I C Bus Interface (IIC) WUE = 1 WUSEN = 0 [1] Start PCLKB to IIC due to other return factor (IRQ). WUASYF = 1 [2] Set WUSEN to 1. [3] Disable wakeup interrupts. ICIER = 00h [4] Disable wakeup function.
Page 931 S3A3 User’s Manual 30. I C Bus Interface (IIC) [Normal Wakeup Mode 1] As with the normal operation, ACK response when there is match with own slave address; SCL held low until return. Before wakeup: Own slave ACK response. / During wakeup: SCL low hold after 9th SCL. / After wakeup: Continue normal operation. Software Standby ...
Page 932 S3A3 User’s Manual 30. I C Bus Interface (IIC) IIC normal operation BBSY = 0 [1] Wait until I C bus is free and stay in standby state. MST = 0 & TRS = 0 (Slave receive) IICRST = 0 (& ICE = 1) [2] Negate internal reset (if asserted).
Page 933 S3A3 User’s Manual 30. I C Bus Interface (IIC) [Normal Wakeup Mode 2] IIC holds SCL low until wakeup after its own slave match. ACK response after wakeup. Before wakeup: Own slave – response. / During wakeup: SCL low hold between 8th and 9th SCL. / After wakeup: Continue normal operation after own slave ACK response. Software Standby ...
Page 934 S3A3 User’s Manual 30. I C Bus Interface (IIC) IIC normal operation [1] Wait until I C bus is free and stay in standby state. BBSY = 0 MST = 0 & TRS = 0 (Slave receive) IICRST = 1 & ICE = 1 [2] Internal reset is asserted.
Page 935 S3A3 User’s Manual 30. I C Bus Interface (IIC) WUE = 1 [1] Start PCLKB to IIC due to other return factor (IRQ). WUSEN = 0 [2] Set WUSEN to 1. [3] Disable wakeup interrupts. WUASYF = 1 [4] Disable wakeup function. [5] Reset IIC (ICE = 0 &...
Page 936 S3A3 User’s Manual 30. I C Bus Interface (IIC) [Command return mode/ EEP response mode] Reply ACK / NACK in response to own slave address. Reply ACK in response to own slave again after IICRST release after wakeup. Before wakeup: Own slave ACK/NACK response. / During wakeup: No SCL low hold. / After wakeup: Continue normal operation. Software Standby ...
Page 937 S3A3 User’s Manual 30. I C Bus Interface (IIC) Automatic low-hold [Master transmit mode] (to prevent wrong Automatic low-hold (to prevent wrong transmission) Automatic low-hold (to prevent wrong transmission) transmission) SCLn 7-bit slave address Data (DATA 1) SDAn BBSY Transmit data (7-bit address + W) Transmit data (DATA 1) Transmit data (DATA 2) AASy...
Page 938 S3A3 User’s Manual 30. I C Bus Interface (IIC) [Master transmit mode] Automatic low-hold (to prevent wrong transmission) Bus free time (ICBRL) SCLn 7-bit slave address NACK 7-bit slave address SDAn Transfer suspended BBSY Transmit data Transmit data Transmit data (DATA 1) Transmit data (DATA 1) (7-bit address + W) (7-bit address + W)
Page 939 S3A3 User’s Manual 30. I C Bus Interface (IIC) function. When the RDRFS bit is set to 1, the RDRF flag (receive data full) in ICSR2 is set to 1 on the rising edge of the SCL clock cycle, and the SCLn line is automatically held low on the falling edge of the 8 SCL clock cycle.
Page 940 S3A3 User’s Manual 30. I C Bus Interface (IIC) After a loss in arbitration of mastership, the IIC immediately enters slave receive mode. If a slave address, including the general call address, matches its own address at this time, the IIC continues in slave operation. A loss in arbitration of mastership is detected when the following conditions are met while the MALE bit in ICFER register is 1 (master arbitration-lost detection enabled).
Page 941 S3A3 User’s Manual 30. I C Bus Interface (IIC) Bus free (BBSY = 0) start condition issuance (ST = 1) error Bus busy (BBSY =1) start condition issuance (ST = 1) error SDA mismatch PCLKB PCLKB PCLKB SCLn SCLn SCLn SDAn SDAn SDAn...
Page 942 S3A3 User’s Manual 30. I C Bus Interface (IIC) The NACK transmission from master A and the ACK transmission from master B conflict. In general, if a conflict like this occurs, master A cannot detect the ACK transmitted by master B and issues a stop condition. Therefore, the stop condition issue conflicts with the SCL clock output of master B, which disrupts communication.
Page 943 S3A3 User’s Manual 30. I C Bus Interface (IIC) 30.11 Start, Restart, and Stop Condition Issuing Function 30.11.1 Issuing a Start Condition The IIC issues a start condition when the ST bit in ICCR2 is set to 1. When the ST bit is set to 1, a start condition request is made. The IIC issues a start condition when the BBSY flag in ICCR2 is 0 (bus free state).
Page 944 S3A3 User’s Manual 30. I C Bus Interface (IIC) [Start condition issuing operation] [Restart condition issuing operation] Hold time Setup time Hold time ICBRH ICBRL ICBRH ICBRL ICBRL ICBRH ICBRL SCLn SCLn Issue start Issue restart condition SDAn SDAn condition ACK/NACK IIC...
Page 945 S3A3 User’s Manual 30. I C Bus Interface (IIC) Automatic low-hold (to prevent wrong transmission) SCL0 SDA0 7-bit slave address Data (DATA 1) 7-bit slave address BBSY Transmit data (7-bit address + W) Transmit data (DATA 1) Transmit data (7-bit address + R) TDRE TEND RDRF...
Page 946 S3A3 User’s Manual 30. I C Bus Interface (IIC) Setup time Bus free time ICBRL ICBRH ICBRL ICBRH ICBRL ICBRH ICBRL SCLn Issue stop condition ACK/NACK SDAn IIC  BBSY TDRE STOP Accept stop condition issuance Write 1 to SP Clear STOP to 0 Figure 30.47 Stop condition issue timing using the SP bit...
Page 947 S3A3 User’s Manual 30. I C Bus Interface (IIC) [Timeout function] Start internal Start internal Start internal Start internal Start internal Start internal counter counter counter counter counter counter Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal counter counter...
Page 948 S3A3 User’s Manual 30. I C Bus Interface (IIC)  When the bus is free (ICCR2.BBSY = 0) or in master mode (ICCR2.MST = 1 and ICCR2.BBSY = 1)  When the communication device does not hold the SCLn line low. Figure 30.49 shows the operation timing of the extra SCL clock cycle output function (CLO bit).
Page 949 S3A3 User’s Manual 30. I C Bus Interface (IIC) the GPT using the IIC start condition detection interrupt (STIn) and stop condition detection interrupt (SPIn). The measured timeout period must be within the total clock low-level period [slave device] T : 25 ms (maximum) LOW: SEXT of the SMBus standard.
Page 950 S3A3 User’s Manual 30. I C Bus Interface (IIC) Cyclic Redundancy Check (CRC) Calculator. The PEC data in master transmit mode can be generated by writing all transmit data to the CRC Data Input Register (CRCDIR) in the CRC calculator. The PEC data in master receive mode can be checked by writing all receive data to the CRCDIR register in the CRC calculator and comparing the obtained value in the CRC Data Output Register (CRCDOR) with the received PEC data.
Page 951 S3A3 User’s Manual 30. I C Bus Interface (IIC) (ICSR2.STOP = 1). Note 2. Because IICn_RXI is an edge-detected interrupt, it does not require clearing. Additionally, the ICSR2.RDRF flag (a condition for IICn_RXI) is automatically set to 0 when data is read from ICDRR. Note 3.
Page 952 S3A3 User’s Manual 30. I C Bus Interface (IIC) Table 30.11 State of registers when issuing each condition (2 of 2) IIC reset Internal reset Start or restart Stop condition Registers Reset (ICE = 0, IICRST = 1) (ICE = 1, IICRST = 1) condition detection detection ICDRR...
Page 953 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Controller Area Network (CAN) Module 31.1 Overview The CAN module uses a message-based protocol to receive and transmit data between multiple slaves and masters in electromagnetically noisy applications. The module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO modes.
Page 954 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Table 31.1 CAN module specifications (2 of 2) Parameter Description Software support unit Three software support units:  Acceptance filter support  Mailbox search support, including receive mailbox search, transmit mailbox search, and message lost search ...
Page 955 S3A3 User’s Manual 31. Controller Area Network (CAN) Module  Timer Used for the time stamp function. The timer value when a message is stored in the mailbox is written as the time stamp value.  Interrupt generator for five types of interrupts: ...
Page 956 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Symbol Bit name Description b7, b6 TSPS[1:0] Time Stamp Prescaler b7 b6 0 0: Every 1-bit time Select* 0 1: Every 2-bit time 1 0: Every 4-bit time 1 1: Every 8-bit time. b9, b8 CANM[1:0] CAN Mode of...
Page 957 S3A3 User’s Manual 31. Controller Area Network (CAN) Module When the TPM bit is 0, ID priority transmit mode is selected and transmission priority complies with the CAN bus arbitration rule, as defined in the ISO11898-1 CAN specification. In ID priority transmit mode, mailboxes 0 to 31 (in normal mailbox mode), mailboxes 0 to 23 (in FIFO mailbox mode), and the transmit FIFO are compared for the IDs of mailboxes configured for transmission.
Page 958 S3A3 User’s Manual 31. Controller Area Network (CAN) Module CPU request has higher priority. RBOC (Forcible Return from Bus-Off) When the RBOC bit is set to 1 in the bus-off state, the CAN module forcibly exits the bus-off state. This bit is automatically set to 0, and the error state changes from bus-off to error-active.
Page 959 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Symbol Bit name Description b15, b14 — Reserved These bits are read as 0. The write value should be 0. b25 to b16 BRP[9:0] Baud Rate Prescaler select* These bits set the frequency of the CAN communication clock (fCANCLK) b27, b26 —...
Page 960 S3A3 User’s Manual 31. Controller Area Network (CAN) Module 31.2.3 Mask Register k (MKRk) (k = 0 to 7) Address(es): CAN0.MKR0 4005 0400h CAN0.MKR7 4005 041Ch — — — SID[10:0] EID[17:0] Value after reset: EID[17:0] Value after reset: x: Undefined Symbol Bit name Description...
Page 961 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Symbol Bit name Description b28 to b18 SID[10:0] Standard ID Standard ID of the data and remote frames — Reserved The read value is undefined. The write value should be 0. Remote Transmission 0: Data frame Request...
Page 962 S3A3 User’s Manual 31. Controller Area Network (CAN) Module 31.2.5 Mask Invalid Register (MKIVLR) Address(es): CAN0.MKIVLR 4005 0428h MB31 MB30 MB29 MB28 MB27 MB26 MB25 MB24 MB23 MB22 MB21 MB20 MB19 MB18 MB17 MB16 Value after reset: MB15 MB14 MB13 MB12 MB11 MB10...
Page 963 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Table 31.4 CAN0 mailbox memory mapping (2 of 2) Address for CAN0 Mapped message content 4005 0200h + 16 × j + 13 Data byte 7 4005 0200h + 16 × j + 14 Time stamp upper byte 4005 0200h + 16 ×...
Page 964 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Symbol Bit Name Description b3 to b0 DLC[3:0] Data Length Code 0 0 0 0: Data length = 0 byte 0 0 0 1: Data length = 1 byte 0 0 1 0: Data length = 2 bytes 0 0 1 1: Data length = 3 bytes 0 1 0 0: Data length = 4 bytes 0 1 0 1: Data length = 5 bytes...
Page 965 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Address(es): CAN0.MB0_D6 4005 020Ch CAN0.MB31_D6 4005 03FCh DATA6 Value after reset: Address(es): CAN0.MB0_D7 4005 020Dh CAN0.MB31_D7 4005 03FDh DATA7 Value after reset: x: Undefined Symbol Bit name Description b7 to b0 DATA0 Data Bytes 0 to 7* DATA0 to DATA7 store the transmitted or received CAN message data.
Page 966 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Extension) The IDE bit sets the ID format to standard ID or extended ID. The IDE bit is enabled when the IDFM[1:0] bits in the CTLR register are 10b (mixed ID mode): ...
Page 967 S3A3 User’s Manual 31. Controller Area Network (CAN) Module 31.2.8 Mailbox Interrupt Enable Register for FIFO Mailbox Mode (MIER_FIFO) Address(es): CAN0.MIER_FIFO 4005 042Ch — — MB29 MB28 — — MB25 MB24 MB23 MB22 MB21 MB20 MB19 MB18 MB17 MB16 Value after reset: MB15 MB14 MB13...
Page 968 S3A3 User’s Manual 31. Controller Area Network (CAN) Module 31.2.9 Message Control Registers for Transmit (MCTL_TXj) (j = 0 to 31)  Transmit mode (when the TRMREQ bit is 1 and the RECREQ bit is 0) Address(es): CAN0.MCTL_TX0 4005 0820h CAN0.MCTL_TX31 4005 083Fh TRMRE RECRE...
Page 969 S3A3 User’s Manual 31. Controller Area Network (CAN) Module  In one-shot transmission mode (RECREQ = 0, TRMREQ = 1, and ONESHOT = 1), when the CAN module detects CAN bus arbitration-lost or CAN bus error. The TRMABT flag is not set to 1 when data transmission is complete. The SENTDATA flag is set to 1 and the TRMABT flag is set to 0 through a software write.
Page 970 S3A3 User’s Manual 31. Controller Area Network (CAN) Module 31.2.10 Message Control Register for Receive (MCTL_RXj) (j = 0 to 31)  Receive mode (when the TRMREQ bit is 0 and the RECREQ bit is 1) Address(es): CAN0.MCTL_RX0 4005 0820h CAN0.MCTL_RX31 4005 083Fh TRMRE RECRE...
Page 971 S3A3 User’s Manual 31. Controller Area Network (CAN) Module ONESHOT (One-Shot Enable) When the ONESHOT bit is set to 1 in receive mode (RECREQ = 1 and TRMREQ = 0), the mailbox receives a message only one time. The mailbox does not behave as a receive mailbox after it receives the message. The behavior of the NEWDATA and INVALDATA flags is the same as in normal receive mode.
Page 972 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Symbol Bit name Description b3 to b1 RFUST[2:0] Receive FIFO Unread Message 0 0 0: No unread message Number Status 0 0 1: 1 unread message 0 1 0: 2 unread messages 0 1 1: 3 unread messages 1 0 0: 4 unread messages 1 0 1: Reserved...
Page 973 S3A3 User’s Manual 31. Controller Area Network (CAN) Module RFEST flag (Receive FIFO Empty Status Flag) The RFEST flag is set to 1 (no unread message in receive FIFO) when the number of unread messages in the receive FIFO is 0. The RFEST flag is set to 1 when the RFE bit is set to 0. The RFEST flag is set to 0 (unread message in receive FIFO) when the number of unread messages in the receive FIFO is one or more.
Page 974 S3A3 User’s Manual 31. Controller Area Network (CAN) Module 31.2.13 Transmit FIFO Control Register (TFCR) Address(es): CAN0.TFCR 4005 084Ah TFEST TFFST — — TFUST[2:0] Value after reset: Symbol Bit name Description Transmit FIFO Enable 0: Disable transmit FIFO 1: Enable transmit FIFO. b3 to b1 TFUST[2:0] Transmit FIFO Unsent Message...
Page 975 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Figure 31.3 shows the transmit FIFO mailbox operation. Transmit FIFO mailbox Frame 1 Frame 2 Frame 3 Frame 4 CAN bus Frame 1 Frame 2 Frame 3 Frame 4 Frame 1 Frame 2 Frame 3 Frame 4 Internal bus TFCR.TFEST flag TFCR.TFFST bit...
Page 976 S3A3 User’s Manual 31. Controller Area Network (CAN) Module 31.2.15 Status Register (STR) Address(es): CAN0.STR 4005 0842h — RECST TRMST BOST EPST SLPST HLTST RSTST TABST FMLST NMLST TFST RFST SDST NDST Value after reset: Symbol Bit name Description NDST NEWDATA Status Flag 0: No mailbox with NEWDATA = 1 1: 1 or more mailboxes with NEWDATA = 1.
Page 977 S3A3 User’s Manual 31. Controller Area Network (CAN) Module TFST flag (Transmit FIFO Status Flag) The TFST flag is set to 1 when the transmit FIFO is not full. The TFST flag is set to 0 when the transmit FIFO is full or normal mailbox mode is selected.
Page 978 S3A3 User’s Manual 31. Controller Area Network (CAN) Module 31.2.16 Mailbox Search Mode Register (MSMR) Address(es): CAN0.MSMR 4005 0853h — — — — — — MBSM[1:0] Value after reset: Symbol Bit name Description b1, b0 MBSM[1:0] Mailbox Search Mode Select b1 b0 0 0: Receive mailbox search mode 0 1: Transmit mailbox search mode...
Page 979 S3A3 User’s Manual 31. Controller Area Network (CAN) Module MBNST[4:0]  When the respective NEWDATA, SENTDATA or MSGLOST flag is set to 1 for a mailbox with a smaller number than that in MBNST[4:0]. If the MBSM[1:0] bits are set to 00b (receive mailbox search mode) or 10b (message lost search mode), the receive FIFO (mailbox 28) is output when it is not empty and there are no unread received messages or no lost messages in any of the normal mailboxes (0 to 23).
Page 980 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Address CAN0 4005 0851h CSSR 8/3 encoder CAN0 4005 0852h MSSR read) (Search result: Channel number 0 read) read) (Search result: Channel number 3 read) read) (Search result: Channel number 6 read) read) (Search result: No corresponding channel number) Figure 31.4...
Page 981 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Figure 31.5 shows the write and read operation in the AFSR register. Address CAN0 When writing* 4005 0856h 3/8 decoder CAN0 When reading 4005 0856h Column (bit) position in data table Row (byte offset) position in data table Note 1.
Page 982 S3A3 User’s Manual 31. Controller Area Network (CAN) Module EWIE bit is 1, an error interrupt request is generated if the EWIF flag is set to 1. EPIE (Error-Passive Interrupt Enable) When the EPIE bit is 0, no error interrupt request is generated even if the EPIF flag in the EIFR register is 1. When the EPIE bit is 1, an error interrupt request is generated if the EPIF flag is set to 1.
Page 983 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Clear the bits to 0 through a software write. If a bit is set to 1 at the same time that software clears it, the bit becomes 1. When setting a single bit to 0 in software, use the transfer instruction (MOV) to ensure that only the specified bit is set to 0 and the other bits are set to 1.
Page 984 S3A3 User’s Manual 31. Controller Area Network (CAN) Module In overrun mode with normal mailbox mode, if an overrun occurs in any of the mailboxes 0 through 31, the ORIF flag is set to 1. In overrun mode with FIFO mailbox mode, if an overrun occurs in any of the mailboxes 0 through 23, or the receive FIFO, the ORIF flag is set to 1.
Page 985 S3A3 User’s Manual 31. Controller Area Network (CAN) Module 31.2.24 Error Code Store Register (ECSR) Address(es): CAN0.ECSR 4005 0850h EDPM ADEF BE0F BE1F Value after reset: Symbol Bit name Description Stuff Error Flag 0: No stuff error detected 1: Stuff error detected. Form Error Flag 0: No form error detected 1: Form error detected.
Page 986 S3A3 User’s Manual 31. Controller Area Network (CAN) Module ADEF flag (ACK Delimiter Error Flag) The ADEF flag is set to 1 when a form error is detected with the ACK delimiter during transmission. EDPM (Error Display Mode Select) The EDPM bit selects the output mode of ECSR. When the EDPM bit is set to 0, the ECSR register outputs the first error code.
Page 987 S3A3 User’s Manual 31. Controller Area Network (CAN) Module CTX0 CRX0 Recessive level CTX0 CRX0 (internal) (internal) Figure 31.6 Connection when listen-only mode is selected (2) Self-test mode 0 (external loopback) Self-test mode 0 is provided for CAN transceiver tests. In this mode, the protocol module treats its own transmitted messages as those received by the CAN transceiver and stores them into the receive mailbox.
Page 988 S3A3 User’s Manual 31. Controller Area Network (CAN) Module CTX0 CRX0 Recessive level CTX0 CRX0 (internal) (internal) Figure 31.8 Connection when self-test mode 1 is selected 31.3 Modes of Operation The CAN module operation modes include:  CAN reset mode ...
Page 989 S3A3 User’s Manual 31. Controller Area Network (CAN) Module CTLR.CANM[1:0] bits until the RSTST flag is set to 1. Set the BCR register before exiting CAN reset mode to enter any other modes. The following registers are initialized to their reset values after entering CAN reset mode, and their initial values are retained during CAN reset mode: ...
Page 990 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Table 31.8 Operation in CAN reset mode and CAN halt mode Operation mode Receiver Transmitter Bus-off CAN reset mode CAN module enters CAN reset CAN module enters CAN reset CAN module enters CAN reset mode (forced transition) mode without waiting for the end mode without waiting for the end...
Page 991 S3A3 User’s Manual 31. Controller Area Network (CAN) Module During CAN operation mode, the CAN module may be in one of the following three sub-modes, depending on the status of the CAN bus:  Idle mode: No transmission or reception is occurring ...
Page 992 S3A3 User’s Manual 31. Controller Area Network (CAN) Module 31.4 Data Transfer Rate Configuration This section describes how to configure the data transfer rate. 31.4.1 Clock Setting The CAN module has a CAN clock generator. The CAN clock can be set by the CCLKS bit and the BRP[9:0] bits in the BCR register.
Page 993 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Table 31.9 lists data transfer rate examples. Table 31.9 Data transfer rate examples when fCAN = 32 MHz Data transfer rate Tq count P + 1 1 Mbps 16Tq 500 kbps 16Tq 250 kbps 16Tq...
Page 994 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Address CAN0 SID10 SID9 SID8 SID7 SID6 4005 0400h + 4  k + 0 SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16 4005 0400h + 4  k + 1 4005 0400h + 4 ...
Page 995 S3A3 User’s Manual 31. Controller Area Network (CAN) Module The receive FIFO mailboxes 28 to 31 use two registers, MKR6 and MKR7, for acceptance filtering. The receive FIFO uses two registers, FIDCR0 and FIDCR1, for ID comparison. The EID[17:0], SID[10:0], RTR, and IDE bits in mailbox 28 to mailbox 31 for the receive FIFO are disabled.
Page 996 S3A3 User’s Manual 31. Controller Area Network (CAN) Module ID setting of MBj_ID Mask bit values Setting of MKIVLR* (j = 0 to 31)* 0: IDs not compared 1: IDs compared ID value of received Setting of MKRk message (k = 0 to 7) Acceptance judge signal (internal signal) Acceptance judge signal...
Page 997 S3A3 User’s Manual 31. Controller Area Network (CAN) Module When configuring a mailbox as a transmit mailbox or a one-shot transmit mailbox:  Before configuring the mailbox, ensure that the MCTL_TXj register is 00h and that there is no pending abort process.
Page 998 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Figure 31.19 shows an operation example of data frame reception in overrun mode. The example shows the overrunning of the second message when the CAN module receives two consecutive CAN messages that match the receiving conditions of MCTL_RXj (j = 0 to 31).
Page 999 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Transmission message in mailbox j Transmission message in mailbox k IFS SOF delimiter delimiter CAN bus Next transmission scan Next transmission scan Next transmission scan MCTL_TXj.TRMREQ MCTL_TXj.TRMACTIVE MCTL_TXj.SENTDATA MCTL_TXk.TRMREQ MCTL_TXk.TRMACTIVE MCTL_TXk.SENTDATA CAN0 transmission complete interrupt STR.TRMST...
Page 1000 S3A3 User’s Manual 31. Controller Area Network (CAN) Module Eight interrupt sources are available for the CAN0 error interrupts. Check the EIFR register to determine the interrupt sources:  Bus error  Error-warning  Error-passive  Bus-off entry  Bus-off recovery ...

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