Renesas R7F0C80112ESP User Manual
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Renesas R7F0C80112ESP User Manual

Renesas R7F0C80112ESP User Manual

8-bit single-chip microcontrollers
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R7F0C80112ESP, R7F0C80212ESP
8
8-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
The sales of these products are limited for China and Hong Kong.
User's Manual: Hardware
Rev.1.00 Sep 2013

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Summary of Contents for Renesas R7F0C80112ESP

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
  • Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
  • Page 4 This manual is intended to give users an understanding of the functions described in the Organization below. Organization The R7F0C80112ESP, R7F0C80212ESP manual is separated into two parts: this manual and the software edition (common to the RL78 family). R7F0C80112ESP, R7F0C80212ESP RL78 Family User’s Manual...
  • Page 5 C11892E Semiconductor Reliability Handbook R51ZZ0001E Note See the “Semiconductor Package Mount Manual” website (http://www.renesas.com/products/package/manual/index.jsp). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. All trademarks and registered trademarks are the property of their respective owners.

  • Page 6: Table Of Contents

    CONTENTS CHAPTER 1 OUTLINE..........................1 1.1 Features............................1 1.2 List of Part Numbers ........................2 1.3 Pin Configuration (Top View) ......................3 1.4 Pin Identification..........................3 1.5 Block Diagram ..........................4 1.6 Outline of Functions........................5 CHAPTER 2 PIN FUNCTIONS ......................... 6 2.1 Port Functions ..........................
  • Page 7 3.4.5 SFR addressing..........................34 3.4.6 Register indirect addressing ......................35 3.4.7 Based addressing..........................36 3.4.8 Based indexed addressing ....................... 40 3.4.9 Stack addressing..........................41 CHAPTER 4 PORT FUNCTIONS ......................45 4.1 Port Functions ..........................45 4.2 Port Configuration........................45 4.2.1 Port 0..............................46 4.2.2 Port 4..............................
  • Page 8 5.5 Clock Generator Operation ......................67 5.6 Controlling Clock.......................... 69 5.6.1 Example of setting high-speed on-chip oscillator ................69 5.6.2 CPU clock status transition diagram....................70 CHAPTER 6 TIMER ARRAY UNIT......................72 6.1 Functions of Timer Array Unit..................... 73 6.1.1 Independent channel operation function ..................73 6.1.2 Simultaneous channel operation function..................
  • Page 9 6.7.1 Operation as interval timer/square wave output ................119 6.7.2 Operation as external event counter ....................125 6.7.3 Operation as frequency divider (channel 0 only) ................130 6.7.4 Operation as input pulse interval measurement ................134 6.7.5 Operation as input signal high-/low-level width measurement............139 6.7.6 Operation as delay counter ......................
  • Page 10 9.3.7 Port mode control register 0 (PMC0)....................185 9.3.8 Port mode register 0 (PM0) ......................186 9.4 A/D Converter Conversion Operations ..................187 9.5 Input Voltage and Conversion Results ..................189 9.6 A/D Converter Operation Modes....................190 9.7 A/D Converter Setup Flowchart ....................191 9.8 How to Read A/D Converter Characteristics Table..............
  • Page 11 10.3.5 Serial data register 0n (SDR0nH, SDR0nL) ................. 213 10.3.6 Serial flag clear trigger register 0n (SIR0n) .................. 214 10.3.7 Serial status register 0n (SSR0n) ....................215 10.3.8 Serial channel start register 0 (SS0)..................... 217 10.3.9 Serial channel stop register 0 (ST0) ..................... 218 10.3.10 Serial channel enable status register 0 (SE0) ................
  • Page 12 11.3.5 Program status word (PSW)......................321 11.4 Interrupt Servicing Operations ....................322 11.4.1 Maskable interrupt request acknowledgment ................322 11.4.2 Software interrupt request acknowledgment ................325 11.4.3 Multiple interrupt servicing......................325 11.4.4 Interrupt request hold ........................329 CHAPTER 12 KEY INTERRUPT FUNCTION ..................330 12.1 Functions of Key Interrupt ......................
  • Page 13 16.1.2 On-chip debug option byte (000C3H) ................... 359 16.2 Format of User Option Byte ....................360 16.3 Format of On-chip Debug Option Byte................... 362 16.4 Setting of Option Byte......................363 CHAPTER 17 FLASH MEMORY ......................364 17.1 Serial Programming by Using Flash Memory Programmer ..........365 17.1.1 Programming environment ......................
  • Page 14 20.1.4 PREFIX instruction ........................384 20.2 Operation List ........................... 385 CHAPTER 21 ELECTRICAL SPECIFICATIONS ................. 402 21.1 Absolute Maximum Ratings ....................403 21.2 Oscillator Characteristics......................404 21.2.1 On-chip oscillator characteristics....................404 21.3 DC Characteristics ........................405 21.3.1 Pin characteristics ........................405 21.3.2 Supply current characteristics ......................

  • Page 15: Chapter 1 Outline

    R01UH0400EJ0100 R7F0C80112ESP, R7F0C80212ESP Rev. 1.00 RENESAS MCU Sep 20, 2013 CHAPTER 1 OUTLINE 1.1 Features μ Minimum instruction execution time can be changed from high speed (0.05 s @ 20 MHz operation) to low speed μ (0.8 s @ 1.25 MHz operation) General-purpose register: 8 bits ×...

  • Page 16: List Of Part Numbers

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 1 OUTLINE 1.2 List of Part Numbers R7F0C80112ESP, R7F0C80212ESP Figure 1-1. Part Number, Memory Size, and Package of Part No. R 7 F 0C801 1 2E SP #AA0 Packaging style, Environmental #AA0 : Tray, Lead free (Pure Sn)

  • Page 17: Pin Configuration (Top View)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) • 10-pin plastic SSOP (4.4 × 3.6) P40/KR0/TOOL0/(PCLBUZ0)/(TI01/TO01) P04/ANI3/TI01/TO01/KR5 P03/ANI2/TO00/KR4/(INTP1) P125/KR1/RESET P02/ANI1/SCK00/PCLBUZ0/KR3 P137/TI00/INTP0 P01/ANI0/SI00/RXD0/KR2 P00/SO00/TXD0/INTP1 Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR).

  • Page 18: Block Diagram

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 1 OUTLINE 1.5 Block Diagram PORT 0 P00 to P04 TAU0 (2 ch) PORT 4 TI00 /TO00 ch00 PORT 12 P125 TI01 /TO01 ch01 PORT 13 P137 Code flash: 1 KB/2 KB SAU0 (1 ch) RxD0 Buzzer/clock...

  • Page 19: Outline Of Functions

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 1 OUTLINE 1.6 Outline of Functions This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H. Item R7F0C80212ESP R7F0C80112ESP Code flash memory 2 KB 1 KB 256 B 128 B •...

  • Page 20: Chapter 2 Pin Functions

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Port Functions The input or output, buffer, and pull-up resistor settings are also valid for the alternate functions. Function Function After Reset Alternate Function Name Port 0. Input port SO00/TXD0/INTP1 5-bit I/O port.

  • Page 21: Functions Other Than Port Pins

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 2 PIN FUNCTIONS 2.2 Functions other than port pins Function Name Functions ANI0 to ANI3 Input Analog input pins of A/D converter (See, Figure 9-22. Analog Input Pin Connection.) INTP0, INTP1 Input External interrupt request input Specified available edge: rising edge, falling edge, or both rising and falling edges...

  • Page 22: Pin I/O Circuits And Recommended Connection Of Unused Pins

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Tables 2-1 and 2-2 show the types of pin I/O circuits and the recommended connections of unused pins. Table 2-1. Connection of Unused Pins...
  • Page 23 R7F0C80112ESP, R7F0C80212ESP CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List Type 8-R Type 11-U pull-up P-ch enable data P-ch pullup IN/OUT P-ch enable output N-ch disable data P-ch input enable IN/OUT output N-ch P-ch disable Comparator N-ch Series resistor string voltage...

  • Page 24: Chapter 3 Cpu Architecture

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE <R> R7F0C80112ESP, R7F0C80212ESP have the RL78-S1 core. The features of the RL78-S1 core are as follows. • CISC architecture with 3-stage pipeline • Address space: 1 MB • General-purpose register: 8-bit register x 8 •...

  • Page 25: Address Space

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE 3.1 Address Space Products in the R7F0C80112ESP, R7F0C80212ESP can access a 1 MB address space. Figures 3-1 and 3-2 show the memory maps. Figure 3-1. Memory Map for the R7F0C80112ESP 003FFH FFFFFH Special function register (SFR)
  • Page 26 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map for the R7F0C80212ESP 007FFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 8 bytes FFEF8H FFEF7H Prohibited area FFEE0H FFEDFH 256 bytes FFDE0H FFDDFH Program area Prohibited area...

  • Page 27: Internal Program Memory Space

    CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The R7F0C80112ESP, R7F0C80212ESP products incorporate internal ROM (flash memory), as shown below. Table 3-1. Internal ROM Capacity Part Number Internal ROM...
  • Page 28 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area of 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is 2 bytes).

  • Page 29: Mirror Area

    See 3.1 Address Space for the mirror area of each product. The mirror area can only be read and no instruction can be fetched from this area. The following shows examples. Example R7F0C80112ESP (Flash memory: 2 KB) FFFFFH Special function register (SFR)

  • Page 30: Internal Data Memory Space

    Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the R7F0C80112ESP, R7F0C80212ESP, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of the special function registers (SFR) and general- purpose registers are available for use.
  • Page 31 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Correspondence Between Data Memory and Addressing <R> FFFFFH SFR addressing FFF20H Special function register (SFR) 256 bytes FFF1FH FFF00H FFEFFH General-purpose Register addressing register 8 bytes FFEF8H Short direct FFEF7H addressing Prohibited area...

  • Page 32: Processor Registers

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The R7F0C80112ESP, R7F0C80212ESP products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
  • Page 33 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE (d) In-service priority flags (ISP1, ISP0) These flags manage the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PR00L, PR00H, PR10L, PR10H) (see 11.3.3 Priority specification flag registers (PR00L, PR00H, PR10L, PR10H)) can not be...

  • Page 34: General-Purpose Registers

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Data to Be Saved to Stack Memory PUSH PSW instruction PUSH rp instruction Register pair lower Register pair higher CALL, CALLT instruction Interrupt, BRK instruction (4-byte stack) (4-byte stack) PC7 to PC0...
  • Page 35 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Configuration of General-Purpose Registers (a) Function name 16-bit processing 8-bit processing FFEFFH General-purpose register FFEF8H (b) Absolute name 16-bit processing 8-bit processing FFEFFH General-purpose register FFEF8H R01UH0400EJ0100 Rev. 1.00 Sep. 20, 2013...

  • Page 36: And Cs Registers

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE <R> 3.2.3 ES and CS registers The ES register and CS register are used to specify the higher address for data access and when a branch instruction is executed (register direct addressing), respectively. The default value of the ES register after reset is 0FH, and that of the CS register is 00H.

  • Page 37: Special Function Registers (Sfrs)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
  • Page 38 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Table 3-4. SFR List (1/2) Address Special Function Register Symbol Manipulable Bit After Reset (SFR) Name Range 1-bit 8-bit √ √ FFF00H Port register 0 √ √ FFF04H Port register 4 √ √ FFF0CH...
  • Page 39 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Table 3-4. SFR List (2/2) Address Special Function Register Symbol Manipulable Bit After Reset (SFR) Name Range 1-bit 8-bit √ √ FFFA5H Clock output select register 0 CKS0 − √ Note 1 FFFA8H Reset control flag register...

  • Page 40: Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area.
  • Page 41 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Table 3-5. Extended SFR (2nd SFR) List (1/2) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit √ √ F0010H A/D converter mode register 2 ADM2 √ √ F0030H Pull-up resistor option register 0 √...
  • Page 42 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Table 3-5. Extended SFR (2nd SFR) List (2/2) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit − √ F0190H Timer mode register 00L TMR00L − √ F0191H Timer mode register 00H TMR00H −...

  • Page 43: Instruction Address Addressing

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination.

  • Page 44: Register Direct Addressing

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address.

  • Page 45: Addressing For Processing Data Addresses

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word.

  • Page 46: Direct Addressing

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE <R> 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description !addr16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable: automatically...

  • Page 47: Short Direct Addressing

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH.

  • Page 48: Sfr Addressing

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format]...

  • Page 49: Register Indirect Addressing

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE <R> 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description −...

  • Page 50: Based Addressing

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE <R> 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
  • Page 51 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Figure 3-25. Example of [HL + byte], [DE + byte] [HL + byte], [DE + byte] <1> <2> <1> <2> FFFFFH Instruction code Target OP-code Target memory array <2> Offset of data <2> byte <1>...
  • Page 52 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Figure 3-28. Example of ES:[HL + byte], ES:[DE + byte] ES: [HL + byte], ES: [DE + byte] <1> <2> <3> <1> <2> <3> XFFFFH Instruction code <2> <3> Target memory Target OP-code array...
  • Page 53 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Figure 3-30. Example of ES:word[BC] ES: word [BC] <1> <2> <3> XFFFFH Array of Instruction code Target memory <3> word-sized <3> Offset data OP-code rp(BC) <2> Low Addr. Address of a word within an array <2>...

  • Page 54: Based Indexed Addressing

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing <R> [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address.

  • Page 55: Stack Addressing

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing <R> [Function] The stack area is indirectly addressed with the stack pointer (SP) values. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request.
  • Page 56 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Figure 3-34. Example of POP POP rp <1> <2> SP + 2 <1> SP +1 (SP+1) Stack Instruction code area (SP) <2> OP-code F0000H Stack addressing is specified <1>. The contents of addresses SP and SP + 1 are stored in the lower-order and higher-order bytes of the pair of registers indicated by rp <2>, respectively.
  • Page 57 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Figure 3-36. Example of RET <1> SP+4 <1> SP+3 (SP+3) Instruction code Stack SP+2 (SP+2) area OP-code (SP+1) SP+1 <3> (SP) <2> F0000H Stack addressing is specified <1>. The contents of addresses SP, SP + 1, and SP + 2 are stored in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>.
  • Page 58 R7F0C80112ESP, R7F0C80212ESP CHAPTER 3 CPU ARCHITECTURE Figure 3-38. Example of RETI, RETB RETI, RETB <1> SP+4 <1> (SP+3) SP+3 Instruction code (SP+2) SP+2 Stack OP-code (SP+1) area SP+1 <3> (SP) <2> F0000H Stack addressing is specified <1>. Memory The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively <2>.

  • Page 59: Chapter 4 Port Functions

    CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The R7F0C80112ESP, R7F0C80212ESP microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS.

  • Page 60: Port 0

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is an I/O port with output latches. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P04 pins are used as input pins, use of the on-chip pull-up resistors can be specified in 1-bit units by pull-up resistor option register 0 (PU0).

  • Page 61: Registers Controlling Port Function

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers. • Port mode registers 0, 4 (PM0, PM4) • Port registers 0, 4, 12, 13(P0, P4, P12, P13) • Pull-up resistor option registers 0, 4, 12(PU0, PU4, PU12) •...

  • Page 62: Port Mode Registers 0, 4(Pm0, Pm4)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.3.1 Port mode registers 0, 4(PM0, PM4) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.

  • Page 63: Port Registers 0, 4, 12, 13 (P0, P4, P12, P13)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.3.2 Port registers 0, 4, 12, 13 (P0, P4, P12, P13) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is...

  • Page 64: Pull-Up Resistor Option Registers 0, 4, 12 (Pu0, Pu4, Pu12)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.3.3 Pull-up resistor option registers 0, 4, 12 (PU0, PU4, PU12) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set satisfied following three conditions which the use of an on-chip pull-up resistor has been specified in these registers.

  • Page 65: Port Output Mode Register (Pom0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.3.4 Port output mode register (POM0) These registers set CMOS output or N-ch open drain output in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.

  • Page 66: Port Mode Control Registers (Pmc0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.3.5 Port mode control registers (PMC0) These registers set the digital I/O or analog input in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.

  • Page 67: Peripheral I/O Redirection Register (Pior)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.3.6 Peripheral I/O redirection register (PIOR) This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned.

  • Page 68: Port Function Operations

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.

  • Page 69: Register Settings When An Alternate Function Is Used

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.5 Register Settings When an Alternate Function Is Used <R> 4.5.1 Basic concepts on using an alternate function If a given pin is also used alternately for analog input, first in the port mode control register 0 (PMC0) specify whether the pin is to be used in analog input or digital output.

  • Page 70: Register Settings For Alternate Functions That Do Not Use An Output Function

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.5.2 Register settings for alternate functions that do not use an output function If the output from an alternate function associated with a pin is not used, the settings described below must be specified.
  • Page 71 R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS <R> Table 4-5. Examples of Register And Output Latch Settings With Pin Functions (1/2) Function PIOR POM0 PMC0 Alternate function output Name SAU output Non-SAU function − × − × × − Input −...
  • Page 72 R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS Table 4-5. Examples of Register And Output Latch Settings With Pin Functions (2/2) Function PIOR POM0 PMC0 Notes Name − − − − × P125 P125 Input Optional bytes 000C1H − − − −...

  • Page 73: Cautions When Using Port Function

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.6 Cautions When Using Port Function 4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.

  • Page 74: Notes On Specifying The Pin Settings

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 4 PORT FUNCTIONS 4.6.2 Notes on specifying the pin settings For an output pin to which multiple functions are assigned and a given function is selected for output, any unused alternate function must be set to its initial state so as to prevent conflict with the selected function. This also applies to the functions assigned by using the peripheral I/O redirection register (PIOR).

  • Page 75: Chapter 5 Clock Generator

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable.

  • Page 76: Configuration Of Clock Generator

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Peripheral enable register 0 (PER0) High-speed on-chip oscillator frequency selection register (HOCODIV)
  • Page 77 R7F0C80112ESP, R7F0C80212ESP CHAPTER 5 CLOCK GENERATOR R01UH0400EJ0100 Rev. 1.00 Sep. 20, 2013...

  • Page 78: Registers Controlling Clock Generator

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 5 CLOCK GENERATOR Remark f High-speed on-chip oscillator clock frequency : Main system clock frequency MAIN CPU/peripheral hardware clock frequency Low-speed on-chip oscillator clock frequency 5.3 Registers Controlling Clock Generator The following registers are used to control the clock generator.

  • Page 79: Peripheral Enable Register 0 (Per0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 5 CLOCK GENERATOR 5.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise.

  • Page 80: High-Speed On-Chip Oscillator Frequency Selection Register (Hocodiv)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 5 CLOCK GENERATOR 5.3.2 High-speed on-chip oscillator frequency selection register (HOCODIV) This register is used to change the frequency of the high-speed on-chip oscillator clock set with the option byte (000C2H). HOCODIV can be set by an 8-bit memory manipulation instruction.

  • Page 81: System Clock Oscillator

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the R7F0C80112, R7F0C80212. The frequency can be selected from among 20, 10, 5, 2.5, or 1.25 MHz by using the option byte (000C2H).
  • Page 82 R7F0C80112ESP, R7F0C80212ESP CHAPTER 5 CLOCK GENERATOR Figure 5-4. Clock Generator Operation When Power Supply Voltage Is Turned On Power supply voltage (V SPOR release reset voltage <1> Internal reset signal SPOR Note 2 Reset processing <3> CPU clock High-speed on-chip oscillator clock <2>...

  • Page 83: Controlling Clock

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock <R> 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected by using FRQSEL0 to FRQSEL2 of the option byte (000C2H).

  • Page 84: Cpu Clock Status Transition Diagram

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 5 CLOCK GENERATOR 5.6.2 CPU clock status transition diagram Figure 5-5 shows the CPU clock status transition diagram of this product. Figure 5-5. CPU Clock Status Transition Diagram Power ON High-speed on-chip oscillator: Woken up ≥ 2.4 V (operation guaranteed range:Transition voltage is defined by the SPOR) <R>...
  • Page 85 R7F0C80112ESP, R7F0C80212ESP CHAPTER 5 CLOCK GENERATOR Table 5-2 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-2. CPU Clock Transition and SFR Register Setting Examples (1/3) (1) • HALT mode (B) set while CPU is operating with high-speed on-chip oscillator clock (A)

  • Page 86: Chapter 6 Timer Array Unit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The timer array unit has two 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer.

  • Page 87: Functions Of Timer Array Unit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.1 Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels.

  • Page 88: Simultaneous Channel Operation Function

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT (6) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TI0n), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.

  • Page 89: 8-Bit Timer Operation Function (Channel 1 Only)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT (2) PWM (Pulse Width Modulation) output Two channels are used as a set to generate a pulse with a specified period and a specified duty factor. Compare operation Operation clock Interrupt signal (INTTM0n)

  • Page 90: Configuration Of Timer Array Unit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Configuration Timer/counter Timer/counter register 0n (TCR0nH, TCR0nL) Register Timer data register 0n (TDR0nH, TDR0nL)
  • Page 91 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figures 6-1 and 6-2 show the block diagrams of the timer array unit. Figure 6-1. Entire Configuration of Timer Array Unit Timer clock select register 0 (TPS0) PRS013 PRS012PRS011 PRS010 PRS003 PRS002 PRS001 PRS000...
  • Page 92 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-2. Internal Block Diagram of Channel of Timer Array Unit (a) Channel 0 Master channel Slave/master controller Trigger signal to slave channel Clock signal to slave channel Interrupt signal to slave channel...

  • Page 93: Timer/Counter Register 0N (Tcr0N)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.2.1 Timer/counter register 0n (TCR0n) TCR0n register consists of 8-bit read-only registers (TCR0nH and TCR0nL) and is used to count clocks. When data is read from the TCR0n register, the TCR0nH and TCR0nL registers must be accessed consecutively.
  • Page 94 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Table 6-2. Timer/counter Register 0n (TCR0n) Read Value in Various Operation Modes Note Operation Mode Count Mode Timer/Counter Register 0n (TCR0n) Read Value Value if the operation Value if the count Value if the operation...

  • Page 95: Timer Data Register 0N (Tdr0N)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.2.2 Timer data register 0n (TDR0n) The TDR0 register consists of two eight bit registers (TCR0nH, TCR0nL) for which the capture or comparison functions can be selected. Switching between the capture and comparison functions is by using the MD0n3 to MD0n0 bits of the timer mode register 0n (TMR0n) to select the operating mode.
  • Page 96 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-4. Format of Timer Data Register 0n (TDR0nH, TDR0nL) (n = 0) Address: FFF18H (TDR00L), FFF19H (TDR00H), After reset: 00H FFF19H (TDR00H) FFF18H (TDR00L) TDR00 Figure 6-5. Format of Timer Data Register 0n (TDR0nH, TDR0nL) (n = 1)

  • Page 97: Registers Controlling Timer Array Unit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers. • Peripheral enable register 0 (PER0) • Timer clock select register 0 (TPS0) • Timer channel enable status register 0 (TE0, TEH0) •...

  • Page 98: Peripheral Enable Register 0 (Per0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.1 Peripheral enable register 0 (PER0) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 99: Timer Clock Select Register 0 (Tps0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.2 Timer clock select register 0 (TPS0) The TPS0 register is a 8-bit register that is used to select two types of operation clocks (CK00, CK01) that are commonly supplied to each channel from external prescaler.
  • Page 100 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-7. Format of Timer Clock Select Register 0 (TPS0) Address: F01B6H After reset: 00H Symbol TPS0 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 Note Selection of operation clock (CK0k) (k = 0, 1) 1.25 MHz...

  • Page 101: Timer Mode Register 0N (Tmr0Nh, Tmr0Nl)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.3 Timer mode register 0n (TMR0nH, TMR0nL) The TMR0n register consists of two eight-bit registers (TMR0nH, TMR0nL) which set an operation mode of channel n. This register is used to select the operation clock (f...
  • Page 102 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-8. Format of Timer Mode Register 0n (TMR0n) (2/4) Address: F0190H (TMR00L), F0191H (TMR00H) After reset: 00H : F0192H (TMR01L), F0193H (TMR01H) Symbol TMR01H CKS011 CCS01 SPLIT01 STS012 STS011 STS010 Symbol TMR00H...
  • Page 103 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-8. Format of Timer Mode Register 0n (TMR0n) (3/4) Symbol TMR0nL CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 (n = 0, 1) Selection of TI0n pin input valid edge Falling edge Rising edge...
  • Page 104 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-8. Format of Timer Mode Register 0n (TMR0n) (4/4) Symbol TMR0nL CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 (n = 0, 1) Setting of operation mode Corresponding function Count operation of TCR of channel n...

  • Page 105: Timer Status Register 0N (Tsr0N)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.4 Timer status register 0n (TSR0n) The TSR0n register indicates the overflow status of the counter of channel n. The TSR0n register is valid only in the capture mode (MD0n3 to MD0n1 = 010B) and capture & one-count mode (MD0n3 to MD0n1 = 110B).

  • Page 106: Timer Channel Enable Status Register 0 (Te0, Teh0 (8-Bit Mode))

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.5 Timer channel enable status register 0 (TE0, TEH0 (8-bit mode)) The TE0 and TEH0 registers are used to enable or stop the timer operation of each channel. Each bit of the TE0 and TEH0 registers correspond to each bit of the timer channel start register 0 (TS0, TSH0) and the timer channel stop register 0 (TT0, TTH0).

  • Page 107: Timer Channel Start Register 0 (Ts0, Tsh0 (8-Bit Mode))

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.6 Timer channel start register 0 (TS0, TSH0 (8-bit mode)) The TS0 and TSH0 registers are trigger registers that are used to initialize timer/counter register 0n (TCR0n) and start the counting operation of each channel.

  • Page 108: Timer Channel Stop Register 0 (Tt0, Tth0 (8-Bit Mode))

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.7 Timer channel stop register 0 (TT0, TTH0 (8-bit mode)) The TT0 and TTH0 registers are trigger registers that are used to stop the counting operation of each channel. When a bit of TT0 and TTH0 registers is set to 1, the corresponding bit of timer channel enable status register 0 (TE0, TEH0) is cleared to 0.

  • Page 109: Timer Output Enable Register 0 (Toe0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.8 Timer output enable register 0 (TOE0) The TOE0 register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TO0n bit of timer output register 0 (TO0) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TO0n).

  • Page 110: Timer Output Register 0 (To0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.9 Timer output register 0 (TO0) The TO0 register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TO0n) of each channel.

  • Page 111: Timer Output Level Register 0 (Tol0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.10 Timer output level register 0 (TOL0) The TOL0 register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOE0n = 1) in the Slave channel output mode (TOM0n = 1).

  • Page 112: Timer Output Mode Register 0 (Tom0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.11 Timer output mode register 0 (TOM0) The TOM0 register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.

  • Page 113: Noise Filter Enable Register 1 (Nfen1)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.12 Noise filter enable register 1 (NFEN1) The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.

  • Page 114: Port Mode Register 0 (Pm0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.3.13 Port mode register 0 (PM0) This register sets input/output of port 0 in 1-bit units. When using the ports that share the pin with the timer output (such as P04/ANI3/TI01/TO01/KR5) for timer output, set the bit in the port mode register 0 (PM0), the port register 0 (P0), and the port mode control register 0 (PMC0) corresponding to each port to 0.

  • Page 115: Basic Rules Of Timer Array Unit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.4 Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.

  • Page 116: Basic Rules Of 8-Bit Timer Operation Function (Only Channel 1)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (only channel 1) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8- bit timer channels.

  • Page 117: Operation Of Counter

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.5 Operation of Counter 6.5.1 Count clock (f TCLK The count clock (f ) of the timer array unit can be selected between following by CCS0n bit of timer mode register 0n TCLK (TMR0n).
  • Page 118 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TI0n pin is selected (CCS0n = 1) The count clock (f ) becomes the signal that detects valid edge of input signal via the TI0n pin and synchronizes...

  • Page 119: Start Timing Of Counter

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Timer count register 0n (TCR0n) becomes enabled to operation by setting of TS0n bit of timer channel start register 0 (TS0). Operations from count operation enabled state to timer count Register 0n (TCR0n) count start is shown in Table 6-4.

  • Page 120: Counter Operation

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.5.3 Counter Operation Here, the counter operation in each mode is explained. (1) Interval timer mode operation <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. Timer count register 0n (TCR0n) holds the initial value until count clock generation.
  • Page 121 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT (2) Event counter mode operation <1> Timer count register 0n (TCR0n) holds its initial value while operation is stopped (TE0n = 0). <2> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit.
  • Page 122 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT (3) Capture mode operation (input pulse interval measurement) <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. <2> Timer count register 0n (TCR0n) holds the initial value until count clock generation.
  • Page 123 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT (4) One-count mode operation <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. <2> Timer count register 0n (TCR0n) holds the initial value until start trigger generation. <3> Rising edge of the TI0n input is detected.
  • Page 124 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT (5) Capture & one-count mode operation (high-level width is measured) <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit of timer channel start register 0 (TS0). <2> Timer count register 0n (TCR0n) holds the initial value until start trigger generation.

  • Page 125: Channel Output (To0N Pin) Control

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.6 Channel Output (TO0n pin) Control 6.6.1 TO0n pin output circuit configuration Figure 6-29. Output Circuit Configuration TO0n register Interrupt signal of the master channel (INTTM0n) TO0n pin Interrupt signal of the slave channel...

  • Page 126: To0N Pin Output Setting

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TO0n pin output setting The following figure shows the procedure and status transition of the TO0n output pin from initial setting to timer operation start. Figure 6-30. Status Transition from Timer Output Setting to Operation Start...

  • Page 127: Cautions On Channel Output Operation

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Cautions on channel output operation (1) Changing values set in the registers TO0, TOE0, and TOL0 during timer operation Since the timer operations (operations of timer count register 0n (TCR0n) and timer data register 0n (TDR0n)) are...
  • Page 128 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOM0p = 1) setting (PWM output)) When slave channel output mode (TOM0p = 1), the active level is determined by timer output level register 0 (TOL0p) setting.
  • Page 129 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TO0n pin in slave channel output mode (TOM0n = 1) (a) When timer output level register 0 (TOL0) setting has been changed during timer operation When the TOL0 register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TO0n pin change condition.
  • Page 130 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-34. Set/Reset Timing Operating Statuses (a) Basic operation timing TCLK INTTM0n Internal reset Master signal channel TO0n pin/ TO0n Toggle Toggle Internal set signal 1 clock delay INTTM0p Slave channel Internal reset...

  • Page 131: Collective Manipulation Of To0N Bit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TO0n bit In timer output register 0 (TO0), the setting bits for all the channels are located in one register in the same way as timer channel start register 0 (TS0). Therefore, the TO0n bit of all the channels can be manipulated collectively.

  • Page 132: Timer Interrupt And To0N Pin Output At Operation Start

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.6.5 Timer interrupt and TO0n pin output at operation start In the interval timer mode or capture mode, the MD0n0 bit in timer mode register 0n (TMR0n) sets whether or not to generate a timer interrupt at count start.

  • Page 133: Independent Channel Operation Function Of Timer Array Unit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.7 Independent Channel Operation Function of Timer Array Unit 6.7.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTM0n (timer interrupt) at fixed intervals.
  • Page 134 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-38. Block Diagram of Operation as Interval Timer/Square Wave Output CK01 Operation clock Timer counter Output CK00 TO0n pin register 0n (TCR0n) controller Timer data Interrupt Interrupt signal TS0n register 0n (TDR0n)
  • Page 135 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-40. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1...
  • Page 136 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-40. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Cleared to 0 when master channel output mode (TOM0n = 0)
  • Page 137 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-41. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).
  • Page 138 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-41. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation Hardware Status To hold the TO0n pin output level Clears the TO0n bit to 0 after the value to stop be held is set to the port register.

  • Page 139: Operation As External Event Counter

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.7.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TI0n pin. When a specified count value is reached, the event counter generates an interrupt.
  • Page 140 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Basic Timing of Operation as External Event Counter TS0n TE0n TI0n TCR0n 0000H TDR0n 0003H 0002H INTTM0n 4 events 4 events 3 events Remarks 1. n: Channel number (n = 0, 1).
  • Page 141 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Example of Set Contents of Registers in External Event Counter Mode (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n CKS0n1 CCS0n Note STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3...
  • Page 142 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Example of Set Contents of Registers in External Event Counter Mode (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Cleared to 0 when master channel output mode (TOM0n = 0).
  • Page 143 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-45. Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).

  • Page 144: Operation As Frequency Divider (Channel 0 Only)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Operation as frequency divider (channel 0 only) The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result from the TO00 pin.
  • Page 145 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1) TS00 TE00 TI00 TCR00 0000H TDR00 0002H 0001H TO00 INTTM00 Divided Divided by 6 by 4 Remark TS00: Bit n of timer channel start register 0 (TS0)
  • Page 146 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Example of Set Contents of Registers During Operation as Frequency Divider (a) Timer mode register 00 (TMR00H, TMR00L) TMR00H TMR00L TMR00 CKS001 CCS00 STS002 STS001 STS000 CIS001 CIS000 MD003 MD002 MD001...
  • Page 147 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-49. Operation Procedure When Frequency Divider Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).

  • Page 148: Operation As Input Pulse Interval Measurement

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.7.4 Operation as input pulse interval measurement The count value can be captured at the TI0n valid edge and the interval of the pulse input to TI0n can be measured. The pulse interval can be calculated by the following expression.
  • Page 149 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MD0n0 = 0) TS0n TE0n TI0n FFFFH TCR0n 0000H TDR0n 0000H INTTM0n Remarks 1. n: Channel number (n = 0, 1).
  • Page 150 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Example of Set Contents of Registers to Measure Input Pulse Interval (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2...
  • Page 151 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Cleared to 0 when master channel output mode (TOM0n = 0). TOL0n (e) Timer output mode register 0 (TOM0) Bit n TOM0 0: Sets master channel output mode.
  • Page 152 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-53. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).

  • Page 153: Operation As Input Signal High-/Low-Level Width Measurement

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.7.5 Operation as input signal high-/low-level width measurement By starting counting at one edge of the TI0n pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TI0n can be measured. The signal width of TI0n can be calculated by the following expression.
  • Page 154 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-54. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement CK01 Operation clock CK00 Timer counter Interrupt Interrupt signal register 0n (TCR0n) controller (INTTM0n) TNFEN0n Timer data Noise Edge TI0n pin...
  • Page 155 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3...
  • Page 156 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-57. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).

  • Page 157: Operation As Delay Counter

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.7.6 Operation as delay counter It is possible to start counting down when the valid edge of the TI0n pin input is detected (an external event), and then generate INTTM0n (a timer interrupt) after any specified interval.
  • Page 158 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Basic Timing of Operation as Delay Counter TS0n TE0n TI0n FFFFH TCR0n 0000H TDR0n INTTM0n Remarks 1. n: Channel number (n = 0, 1). 2. TS0n: Bit n of timer channel start register 0 (TS0)
  • Page 159 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n Note CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1...
  • Page 160 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Cleared to 0 when master channel output mode (TOM0n = 0).
  • Page 161 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-61. Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).

  • Page 162: Simultaneous Channel Operation Function Of Timer Array Unit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.8 Simultaneous Channel Operation Function of Timer Array Unit 6.8.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TI0n pin.
  • Page 163 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Block Diagram of Operation as One-Shot Pulse Output Function Master channel (one-count mode) CK01 Operation clock Timer counter register 0n (TCR0n) CK00 TS0n Timer data Interrupt Interrupt signal register 0n (TDR0n)
  • Page 164 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Basic Timing of Operation as One-Shot Pulse Output Function TS0n TE0n TI0n Master FFFFH channel TCR0n 0000H TDR0n TO0n INTTM0n TS0p TE0p FFFFH TCR0p Slave 0000H channel TDR0p TO0p INTTM0p Remarks 1.
  • Page 165 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1...
  • Page 166 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (a) Timer mode register 0p (TMR0pH, TMR0pL) TMR0pH TMR0pL TMR0p CKS0p1 CCS0p STS0p2 STS0p1 STS0p0 CIS0p1...
  • Page 167 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable registers 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write Power-on status.
  • Page 168 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Hardware Status Operation Sets the TOE0p bit (slave) to 1 (only when operation is start resumed). The TS0n (master) and TS0p (slave) bits of timer channel start register 0 (TS0) are set to 1 at the same time.

  • Page 169: Operation As Pwm Function

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions.
  • Page 170 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Block Diagram of Operation as PWM Function Master channel (interval timer mode) CK01 Operation clock Timer counter register 0n (TCR0n) CK00 Timer data Interrupt Interrupt signal TS0n register 0n (TDR0n) controller...
  • Page 171 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Basic Timing of Operation as PWM Function TS0n TE0n FFFFH Master TCR0n channel 0000H TDR0n TO0n INTTM0n TS0p TE0p FFFFH TCR0p Slave 0000H channel TDR0p TO0p INTTM0p Remark 1. n: Master channel number (n = 0) p: Slave channel number (p = 1) 2.
  • Page 172 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL TMR0n CKS0n1 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3...
  • Page 173 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (a) Timer mode register 0p (TMR0pH, TMR0pL) TMR0pH TMR0pL TMR0p CKS0p1 CCS0p STS0p2 STS0p1 STS0p0 CIS0p1 CIS0p0 MD0p3...
  • Page 174 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1 (when the TAU0EN bit is 0, read/write operation is disabled).
  • Page 175 R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Operation Procedure When PWM Function Is Used (2/2) Software Operation Hardware Status Operation Sets the TOE0p bit (slave) to 1 (only when operation is start resumed). The TS0n (master) and TS0p (slave) bits of timer...

  • Page 176: Cautions When Using Timer Array Unit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 6 TIMER ARRAY UNIT 6.9 Cautions When Using Timer Array Unit 6.9.1 Cautions when using timer output Depending on the product, a timer output and other alternate functions may be assigned to some pins. In such case, the outputs of the other alternate functions must be set to their initial states.

  • Page 177: Chapter 7 Clock Output/Buzzer Output Controller

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 7.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for clock output for supply to peripheral ICs. Buzzer output is a function to output a square wave of buzzer frequency.

  • Page 178: Configuration Of Clock Output/Buzzer Output Controller

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 7.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 7-1. Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output select register 0 (CKS0)
  • Page 179 R7F0C80112ESP, R7F0C80212ESP CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 7-2. Format of Clock Output Select Register 0 (CKS0) Address: FFFA5H After reset: 00H Symbol <7> CKS0 PCLOE0 CCS02 CCS01 CCS00 PCLOE0 PCLBUZ0 pin output enable/disable specification Output disable (default) Output enable...

  • Page 180: Port Mode Registers 0, 4 (Pm0, Pm4)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 7.3.2 Port mode registers 0, 4 (PM0, PM4) These registers set input/output of ports 0, 4 in 1-bit units. When using the P02/ANI1/SCK00/PCLBUZ0/KR3 (P40/KR0/TOOL0/(PCLBUZ0)/(TI01/TO01)) pin for clock output and buzzer output, clear PM02 (PM40) bit and the output latch of P02 (P40) to 0. And set 0 to PMC02 bit for port mode control register 0.

  • Page 181: Operations Of Clock Output/Buzzer Output Controller

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 7.4 Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).

  • Page 182: Chapter 8 Watchdog Timer

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 8 WATCHDOG TIMER CHAPTER 8 WATCHDOG TIMER 8.1 Functions of Watchdog Timer The count operation is specified by the user option byte (000C0H) in the watchdog timer. The watchdog timer operates on the low-speed on-chip oscillator clock.

  • Page 183: Configuration Of Watchdog Timer

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 8 WATCHDOG TIMER 8.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 8-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled and overflow time are set by the option byte.

  • Page 184: Register Controlling Watchdog Timer

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 8 WATCHDOG TIMER 8.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 8.3.1 Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.

  • Page 185: Operation Of Watchdog Timer

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 8 WATCHDOG TIMER 8.4 Operation of Watchdog Timer 8.4.1 Controlling operation of watchdog timer <1> When the watchdog timer is used, its operation is specified by the option byte (000C0H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 16).

  • Page 186: Setting Overflow Time Of Watchdog Timer

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 8 WATCHDOG TIMER 8.4.2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H). If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts counting again by writing “ACH”...

  • Page 187: Chapter 9 A/D Converter

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER CHAPTER 9 A/D CONVERTER 9.1 Function of A/D Converter <R> The A/D converter converts analog input signals into digital values, and is configured to control up to 4 channels of A/D converter analog inputs (ANI0 to ANI3). Ten-bit or eight-bit resolution can also be selected by using the ADTYP bit of A/D converter mode register 2 (ADM2).
  • Page 188 R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER R01UH0400EJ0100 Rev. 1.00 Sep. 20, 2013...

  • Page 189: Configuration Of A/D Converter

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI3 pins These are the analog input pins of the 4 channels of the A/D converter. They input analog signals to be converted into digital signals.
  • Page 190 R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER (5) Successive approximation register (SAR) The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).

  • Page 191: Registers Used In A/D Converter

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.3 Registers Used in A/D Converter The A/D converter uses the following registers. • Peripheral enable register 0 (PER0) • A/D converter mode register 0 (ADM0) • A/D converter mode register 2 (ADM2) • A/D conversion result higher bit storage register (ADCRH) •...

  • Page 192: A/D Converter Mode Register 0 (Adm0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 193 R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER Table 9-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation Stop status Conversion standby mode Setting prohibited Conversion mode Figure 9-4. Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables operation...
  • Page 194 R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER Table 9-2. A/D Conversion Time Selection (1) 2.4 V ≤ V ≤ 5.5 V A/D Converter Mode Conversion Number of Conversion Conversion Time Selection Register 0 (ADM0) Clock Conversion Time Clock 1.25 MHz 2.5 MHz...
  • Page 195 R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER Figure 9-5. A/D Converter Sampling and A/D Conversion Timing ADCS ←1 <R> ADCS Sampling timing INTAD Sampling Successive conversion Conversion start Conversion Conversion time Conversion time start time R01UH0400EJ0100 Rev. 1.00 Sep. 20, 2013...

  • Page 196: A/D Converter Mode Register 2 (Adm2)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.3.3 A/D converter mode register 2 (ADM2) This register is used to select the resolution of A/D conversion. The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.

  • Page 197: A/D Conversion Result Lower Bit Storage Register (Adcrl)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.3.5 A/D conversion result lower bit storage register (ADCRL) This register is an 8-bit register that holds the two lower bits of the result of 10-bit A/D conversion. The six lower bits are fixed to 0.

  • Page 198: Analog Input Channel Specification Register (Ads)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.3.6 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 199: Port Mode Control Register 0 (Pmc0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.3.7 Port mode control register 0 (PMC0) This register is used to set the digital I/O/analog input of port 0 in 1-bit units. When using the digital I/O/analog input of port 0 as an analog input pin, set PMC01, PMC02, PMC03, and PMC04 bits to 1.

  • Page 200: Port Mode Register 0 (Pm0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.3.8 Port mode register 0 (PM0) This register is used to set the input/output of the port in 1-bit units. When using the ANI0 to ANI3 pins as analog input ports, set PM0n bits to 1. At this time, the output latches of PM0n may be 0 or 1.

  • Page 201: A/D Converter Conversion Operations

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended.
  • Page 202 R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER <R> Figure 9-13. Conversion Operation of A/D Converter 1 is written to ADCS ADCS Conversion time Conversion Sampling start time time Conversion Conversion Sampling Conversion A/D converter standby A/D conversion start operation standby Conversion...

  • Page 203: Input Voltage And Conversion Results

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the A/D conversion result register (ADCR) (= ADCRH + ADCRL)) is shown by the following expression.

  • Page 204: A/D Converter Operation Modes

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER <R> 9.6 A/D Converter Operation Modes The operation of A/D converter is described below. In addition, the procedure for specifying is described in 9.7 A/D Converter Setup Flowchart. <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 205: A/D Converter Setup Flowchart

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.7 A/D Converter Setup Flowchart The A/D converter setup flowchart is described below. Start of setup PER0 register setting The ADCEN bit of the PER0 register is set to 1, and supplying the clock starts.

  • Page 206: How To Read A/D Converter Characteristics Table

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.8 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. 9.8.1 Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).

  • Page 207: Full-Scale Error

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.8.5 Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. 9.8.6 Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.

  • Page 208: Cautions For A/D Converter

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.9 Cautions for A/D Converter 9.9.1 Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time.

  • Page 209: Analog Input (Anin) Pins

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER <R> Figure 9-22. Analog Input Pin Connection If there is a possibility that noise equal to or higher than V equal to or lower than V may enter, clamp with a diode with a small V value (0.3 V or lower).

  • Page 210: Interrupt Request Flag (Adif)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.9.7 Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. When A/D conversion is stopped and then resumed, clear ADIF flag before the A/D conversion operation is resumed.

  • Page 211: Internal Equivalent Circuit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 9 A/D CONVERTER 9.9.10 Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 9-24. Internal Equivalent Circuit of ANIn Pin ANIn <R> Table 9-4. Resistance and Capacitance Values of Equivalent Circuit Pins R1 [kΩ]...

  • Page 212: Chapter 10 Serial Array Unit

    CHAPTER 10 SERIAL ARRAY UNIT CHAPTER 10 SERIAL ARRAY UNIT Serial array unit 0 has two serial channels. Each channel can achieve 3-wire serial (CSI) and UART communication. Function assignment of each channel supported by the R7F0C80112ESP, R7F0C80212ESP is as shown below. Unit Channel...

  • Page 213: Functions Of Serial Array Unit

    CHAPTER 10 SERIAL ARRAY UNIT 10.1 Functions of Serial Array Unit Each serial interface supported by the R7F0C80112ESP, R7F0C80212ESP has the following features. 10.1.1 3-wire serial I/O (CSI00) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.

  • Page 214: Uart (Uart0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.1.2 UART (UART0) This is a start-stop synchronization function using two lines: serial data transmission (T D) and serial data reception D) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.

  • Page 215: Configuration Of Serial Array Unit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 10-1. Configuration of Serial Array Unit Item Configuration Shift register 8 bits Buffer register Serial data register 0n (SDR0nH, SDR0nL)
  • Page 216 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-1 shows the block diagram of the serial array unit 0. Figure 10-1. Block Diagram of Serial Array Unit 0 Noise filter enable Serial output register 0 (SO0) Serial clock output register 0 (CKO0)

  • Page 217: Shift Register

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.2.1 Shift register This is a 9-bit register that converts parallel data into serial data or vice versa. During reception, it converts data input to the serial pin into parallel data. When data is transmitted, the value set to this register is output as serial data from the serial output pin.
  • Page 218 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-2. Format of Serial Data Register 0n (SDR0nH, SDR0nL) (n = 0, 1) Address: FFF10H (SDR00L), FFF11H (SDR00H), After reset: 00H FFF12H (SDR01L), FFF13H (SDR01H) FFF11H (SDR00H) FFF10H (SDR00L) Remark For the function of the higher 7 bits of the SDR0nH register, see 10.3 Registers Controlling Serial Array Unit.

  • Page 219: Registers Controlling Serial Array Unit

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers. • Peripheral enable register 0 (PER0) • Serial clock select register 0 (SPS0) • Serial mode register 0n (SMR0nH, SMR0nL) •...

  • Page 220: Peripheral Enable Register 0 (Per0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.1 Peripheral enable register 0 (PER0) PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 221: Serial Clock Select Register 0 (Sps0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.2 Serial clock select register 0 (SPS0) The SPS0 register is an 8-bit register that is used to select two types of operation clocks (CK00, CK01) that are commonly supplied to each channel. CK01 is selected by bits 7 to 4 of the SPS0 register, and CK00 is selected by bits 3 to 0.

  • Page 222: Serial Mode Register 0N (Smr0Nh, Smr0Nl)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.3 Serial mode register 0n (SMR0nH, SMR0nL) The SMR0nH and SMR0nL registers are registers that set an operation mode of channel n. It is also used to select an operation clock (f ), specify whether the serial clock (f ) may be input or not, set a start trigger, an operation mode (CSI or UART), and an interrupt source.
  • Page 223 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-6. Format of Serial Mode Register 0n (SMR0nL) Address: F0110H (SMR00L), F0112H (SMR01L) After reset: 20H Symbol: SMR0nL Note Controls inversion of level of receive data of channel n in UART mode Note Falling edge is detected as the start bit.

  • Page 224: Serial Communication Operation Setting Register 0N (Scr0Nh, Scr0Nl)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.4 Serial communication operation setting register 0n (SCR0nH, SCR0nL) The SCR0nH and SCR0nL registers are communication operation setting registers of channel n. It is used to set a data transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length.
  • Page 225 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-7. Format of Serial Communication Operation Setting Register 0n (SCR0nH, SCR0nL) (1/2) Address: F0119H (SCR00H) , F011BH (SCR01H) Address: F0118H (SCR00L) , F011AH (SCR01L) After reset: 00H After reset: 87H Symbol: SCR0nH...
  • Page 226 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-7. Format of Serial Communication Operation Setting Register 0n (SCR0nH, SCR0nL) (2/2) Address: F0119H (SCR00H) , F011BH (SCR01H) Address: F0118H (SCR00L) , F011AH (SCR01L) After reset: 00H After reset: 87H Symbol: SCR0nH...

  • Page 227: Serial Data Register 0N (Sdr0Nh, Sdr0Nl)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.5 Serial data register 0n (SDR0nH, SDR0nL) The SDR0nH and SDR0nL registers are the transmit/receive data registers of channel n. Considering the SDR0nH register is used as a register that sets the division ratio of the operating clock (f ).

  • Page 228: Serial Flag Clear Trigger Register 0N (Sir0N)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.6 Serial flag clear trigger register 0n (SIR0n) The SIR0n register is a trigger register that is used to clear each error flag of channel n. When each bit (FECT0n, PECT0n, OVCT0n) of this register is set to 1, the corresponding bit (FEF0n, PEF0n, OVF0n) of serial status register 0n (SSR0n) is cleared to 0.

  • Page 229: Serial Status Register 0N (Ssr0N)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.7 Serial status register 0n (SSR0n) The SSR0n register indicates the communication status and error occurrence status of channel n. The errors indicated by this register are framing errors, parity errors, and overrun errors.
  • Page 230 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-10. Format of Serial Status Register 0n (SSR0n) (2/2) Address: F0100H (SSR00) - F0102H (SSR01) , After reset: 0000H Symbol: Note SSR0n TSF0n BFF0n FEF0n PEF0n OVF0n Note FEF0n Framing error detection flag of channel n No error occurs.

  • Page 231: Serial Channel Start Register 0 (Ss0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.8 Serial channel start register 0 (SS0) The SS0 register is a trigger register that is used to enable communication/count for each channel. When 1 is written to a bit of this register (SS0n), the corresponding bit (SE0n) of serial channel enable status register 0 (SE0) is set to 1 (operation is enabled).

  • Page 232: Serial Channel Stop Register 0 (St0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.9 Serial channel stop register 0 (ST0) The ST0 register is a trigger register that is used to enable stopping communication/count for each channel. When 1 is written to a bit of this register (ST0n), the corresponding bit (SE0n) of serial channel enable status register 0 (SE0) is cleared to 0 (operation is stopped).

  • Page 233: Serial Channel Enable Status Register 0 (Se0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.10 Serial channel enable status register 0 (SE0) The SE0 register indicates whether the data transmission/reception operation of each channel is enabled or disabled. When 1 is written to a bit of serial channel start register 0 (SS0), the corresponding bit of this register is set to 1. When 1 is written to a bit of serial channel stop register 0 (ST0), the corresponding bit of this register is cleared to 0.

  • Page 234: Serial Output Enable Register 0 (Soe0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.11 Serial output enable register 0 (SOE0) The SOE0 register is used to enable or disable output of the serial communication operation of each channel. If serial output is enabled for channel n, the value of the SO0n bit of serial output register 0 (SO0) cannot be rewritten by software, and a value is output from the serial data output pin according to the communication operation.

  • Page 235: Serial Output Register 0 (So0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.12 Serial output register 0 (SO0) The SO0 register is a buffer register for serial output of each channel. The value of the SO0n bit of this register is output from the serial data output pin of channel n.

  • Page 236: Serial Clock Output Register (Cko0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.13 Serial clock output register (CKO0) The CKO0 register is a buffer register for serial clock output of each channel. The value of the CKO0n bit of this register is output from the serial clock output pin of channel n.

  • Page 237: Serial Output Level Register 0 (Sol0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.14 Serial output level register 0 (SOL0) The SOL0 register is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 to corresponding bit in the CSI mode.

  • Page 238: Noise Filter Enable Register 0 (Nfen0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.15 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel.

  • Page 239: Input Switch Control Register (Isc)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.16 Input switch control register (ISC) The ISC1 and ISC0 bits in the ISC register are used to handle the combination of the external interrupt and the timer array unit at the time of baud rate correction for reception by UART0.

  • Page 240: Port Output Mode Register 0 (Pom0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.17 Port output mode register 0 (POM0) This register sets the output mode of port 1 in 1-bit units. In addition, POM0 register is set with PMxx, PMCxx, and PUxx registers, whether or not to use the on-chip pull-up resistor (see 4.3.3 Pull-up resistor option register s 0, 4, 12 (PU0, PU4, PU12)).

  • Page 241: Port Mode Register 0 (Pm0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.3.18 Port mode register 0 (PM0) This register sets input/output of port 0 in 1-bit units. When using the ports (such as P02/ANI1/SCK00/PCLBUZ0/KR3) to be shared with the serial data output pin or serial clock output pin for serial data output or serial clock output, set the port mode register (PM0) and port mode control register (PMC0) bit corresponding to each port to 0.

  • Page 242: Operation Stop Mode

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.4 Operation Stop Mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the serial interface function alternate pins can be used as port function pins in this mode.

  • Page 243: Stopping The Operation By Channels

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 10-23. Each Register Setting When Stopping Operation by Channels (a) Serial channel stop register 0 (ST0) … This register is a trigger register that is used to enable stopping communication/count by each channel.

  • Page 244: Operation Of 3-Wire Serial I/O (Csi00) Communication

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.5 Operation of 3-Wire Serial I/O (CSI00) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception] • Data length of 7 or 8 bits •...

  • Page 245: Master Transmission

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.5.1 Master transmission Master transmission is that the R7F0C80112ESP, R7F0C80212ESP output a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0 Pins used SCK00, SO00...
  • Page 246 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (1) Register setting Figure 10-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n STS0n...
  • Page 247 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00) (2/2) (e) Serial output register 0 (SO0) … Sets only the bits of the target channel. Symbol: SO00 (f) Serial output enable register 0 (SOE0) …...
  • Page 248 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (2) Operation procedure Figure 10-25. Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 249 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-26. Procedure for Stopping Master Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSF0n = 0? (If there is an urgent must stop, do not wait) Write 1 to the ST0n bit of the target channel.
  • Page 250 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-27. Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop the communication target (slave) or communication operation (Essential) Master ready? completed Disable data output and clock output of Port manipulation...
  • Page 251 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 10-28. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0) SS0n ST0n SE0n SDR0nH/L Transmit data 1 Transmit data 2...
  • Page 252 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-29. Flowchart of Master Transmission (in Single-Transmission Mode) Starting C SI com m unication For the initial setting, refer to Figure 10-25. SAU default setting (Select Transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag...
  • Page 253 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 10-30. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0) <1> SS0n <6> ST0n SE0n SDR0nH Transmit data 2...
  • Page 254 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-31. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 10-25. <1> SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag...

  • Page 255: Master Reception

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.5.2 Master reception Master reception is that the R7F0C80112ESP, R7F0C80212ESP output a transfer clock and receives data from other device. CSI00 3-Wire Serial I/O Target channel Channel 0 of SAU0 Pins used SCK00, SI00...
  • Page 256 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (1) Register setting Figure 10-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n STS0n...
  • Page 257 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00) (2/2) (f) Serial output enable register 0 (SOE0) … The register that not used in this mode. Symbol:...
  • Page 258 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (2) Operation procedure Figure 10-33. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPS0 register Set the operation clock.
  • Page 259 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-35. Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation Completing master (Essential) completed preparations? Disable clock output of the target channel by setting a port register and a...
  • Page 260 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 10-36. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) SS0n ST0n SE0n Receive data 2 Receive data 3...
  • Page 261 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-37. Flowchart of Master Reception (in Single-Reception Mode) Starting C SI com m unication For the initial setting, refer to Figure 10-33. SAU default setting (Select Transfer end interrupt) Setting storage area of the receive data, number of communication data...
  • Page 262 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 10-38. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) <1> SS0n <8> ST0n SE0n Receive data 3...
  • Page 263 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-39. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication For the initial setting, refer to Figure 10-33. buffer empty (Select interrupt) SAU default setting <1> Setting storage area of the receive data, number of communication data...

  • Page 264: Master Transmission/Reception

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.5.3 Master transmission/reception Master transmission/reception is that the R7F0C80112ESP, R7F0C80212ESP output a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0 Pins used SCK00, SI00, SO00...
  • Page 265 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (1) Register setting Figure 10-40. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol:SMR0nH Symbol:SMR0nL CKS0n CCS0n STS0n SIS0n0 MD0n1...
  • Page 266 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-40. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00) (2/2) (f) Serial output enable register 0 (SOE0) … Sets only the bits of the target channel to 1.
  • Page 267 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (2) Operation procedure Figure 10-41. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 268 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-42. Procedure for Stopping Master Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSF0n = 0? (If there is an urgent must stop, do not wait) Write 1 to the ST0n bit of the target channel.
  • Page 269 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-43. Procedure for Resuming Master Transmission/Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation Completing slave (Essential) completed preparations? Disable data output and clock output of...
  • Page 270 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 10-44. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAP0n =0, CKP0n = 0) SS0n ST0n SE0n Receive data 3 Receive data 2 Receive data 1...
  • Page 271 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-45. Flowchart of Master Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication For the initial setting, refer to Figure 10-41. SAU default setting (Select transfer end interrupt) Setting storage data and number of data for transmission/reception data...
  • Page 272 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 10-46. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) <1> SS0n ST0n <8> SE0n Receive data 3...
  • Page 273 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-47. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, refer to Figure 10-41. <1> SAU default setting (Select buffer empty interrupt) Setting storage data and number of data for transmission/reception data...

  • Page 274: Slave Transmission

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.5.4 Slave transmission Slave transmission is that the R7F0C80112ESP, R7F0C80212ESP transmit data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel...
  • Page 275 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (1) Register setting Figure 10-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n STS0n...
  • Page 276 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00) (2/2) (f) Serial output enable register 0 (SOE0) … Sets only the bits of the target channel to 1.
  • Page 277 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (2) Operation procedure Figure 10-49. Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 278 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-50. Procedure for Stopping Slave Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSF0n = 0? (If there is an urgent must stop, do not wait) Write 1 to the ST0n bit of the target channel.
  • Page 279 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-51. Procedure for Resuming Slave Transmission Starting setting for resumption Wait until stop the communication target Completing master (Essential) preparations? (master) Disable data output of the target channel by setting a port register and a port...
  • Page 280 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 10-52. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0) SS0n ST0n SE0n SDR0n Transmit data 1 Transmit data 2...
  • Page 281 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-53. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting C SI com m unication For the initial setting, refer to Figure 10-49. SAU default setting (Select transfer end interrupt) Set storage area and the number of data for transmit data...
  • Page 282 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 10-54. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0) <1> SS0n ST0n <6> SE0n SDR0nL Transmit data 1...
  • Page 283 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-55. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 10-49. <1> SAU default setting (Select buffer empty interrupt) Setting transmit data Set storage area and the number of data for transmit data...

  • Page 284: Slave Reception

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.5.5 Slave reception Slave reception is that the R7F0C80112ESP, R7F0C80212ESP receive data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel...
  • Page 285 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (1) Register setting Figure 10-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol:SMR0nH Symbol:SMR0nL CKS0n CCS0n STS0n SIS0n0 MD0n1...
  • Page 286 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00) (2/2) (f) Serial output enable register 0 (SOE0) … The Register that not used in this mode. Symbol:...
  • Page 287 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (2) Operation procedure Figure 10-57. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 288 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-59. Procedure for Resuming Slave Reception Starting setting for resumption Wait until stop the communication target (master) Completing master (Essential) preparations? Disable clock output of the target channel by setting a port register and a...
  • Page 289 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 10-60. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) SS0n ST0n SE0n Receive data 3 SDR0nL Receive data 1...
  • Page 290 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-61. Flowchart of Slave Reception (in Single-Reception Mode) Starting C SI com m unication For the initial setting, refer to Figure 10-57. SAU default setting (Select transfer end interrupt only) Clear storage area setting and the number of receive data...

  • Page 291: Slave Transmission/Reception

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.5.6 Slave transmission/reception Slave transmission/reception is that the R7F0C80112ESP, R7F0C80212ESP transmit/receive data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel...
  • Page 292 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (1) Register setting Figure 10-62. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n STS0n...
  • Page 293 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-62. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00) (2/2) (f) Serial output enable register 0 (SOE0) … Sets only the bits of the target channel to 1.
  • Page 294 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (2) Operation procedure Figure 10-63. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPS0 register Set the operation clock.
  • Page 295 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-64. Procedure for Stopping Slave Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSF0n = 0? (If there is an urgent must stop, do not wait) Write 1 to the ST0n bit of the target channel.
  • Page 296 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-65. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Wait until stop the communication target Completing master (Essential) (master) preparations? Disable data output of the target channel by setting a port register and a port...
  • Page 297 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 10-66. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) SS0n ST0n SE0n Receive data 1 Receive data 2...
  • Page 298 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-67. Flowchart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) Starting C SI com m unication For the initial setting, refer to Figure 10-63. SAU default setting (Select Transfer end interrupt) Setting storage area and number of data for transmission/reception data...
  • Page 299 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 10-68. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0) <1> SS0n <8> ST0n SE0n Receive data 3...
  • Page 300 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-69. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, refer to Figure 12-63. <1> SAU default setting (Select buffer empty interrupt) Setting storage area and number of data for transmission/reception data...

  • Page 301: Calculating Transfer Clock Frequency

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT <R> 10.5.7 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00) communication can be calculated by the following expressions. (1) Master ) frequency of the target channel } ÷ (SDRnH[7:1] + 1) ÷ 2 [Hz]...

  • Page 302: Procedure For Processing Errors That Occurred During 3-Wire Serial I/O (Csi00) Communication

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00) communication is described in Figure 10-70. Figure 10-70. Processing Procedure in Case of Overrun Error...

  • Page 303: Operation Of Uart (Uart0) Communication

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.6 Operation of UART (UART0) Communication This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception (RXD) lines. By using these two communication lines, each data frame, which consists of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.

  • Page 304: Uart Transmission

    CHAPTER 10 SERIAL ARRAY UNIT 10.6.1 UART transmission UART transmission is an operation to transmit data from the R7F0C80112ESP, R7F0C80212ESP to another device asynchronously (start-stop synchronization). Of the two channels used for UART, the even-numbered channel is used for UART transmission.
  • Page 305 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (1) Register setting Figure 10-71. Example of Contents of Registers for UART Transmission (UART0) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n MD0n1 MD0n0 Interrupt source of channel n...
  • Page 306 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-71. Example of Contents of Registers for UART Transmission (UART0) (2/2) (e) Serial clock output register 0 (CKO0) … Sets only the bits of the target channel. Symbol: CKO0 CKO00 × (f) Serial output register 0 (SO0) … Sets only the bits of the target channel.
  • Page 307 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (2) Operation procedure Figure 10-72. Initial Setting Procedure for UART Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 308 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-73. Procedure for Stopping UART Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSF0n = 0? (If there is an urgent must stop, do not wait) Write 1 to the ST0n bit of the target channel.
  • Page 309 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-74. Procedure for Resuming UART Transmission Starting setting for resumption Completing master Wait until stop the communication target (Essential) preparations? or communication operation completed Disable data output of the target channel (Selective)
  • Page 310 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 10-75. Timing Chart of UART Transmission (in Single-Transmission Mode) SS0n ST0n SE0n SDR0nL Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin Transmit data 1...
  • Page 311 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-76. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication For the initial setting, refer to Figure 10-72. SAU default setting (Select transfer end interrupt) Set data for transmission and the number of data.
  • Page 312 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 10-77. Timing Chart of UART Transmission (in Continuous Transmission Mode) <1> SS0n <6> ST0n SE0n SDR0nL Transmit data 1 Transmit data 2 Transmit data 3...
  • Page 313 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-78. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication For the initial setting, refer to Figure 10-72. <1> SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag...

  • Page 314: Uart Reception

    CHAPTER 10 SERIAL ARRAY UNIT 10.6.2 UART reception UART reception is an operation wherein the R7F0C80112ESP, R7F0C80212ESP asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
  • Page 315 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (1) Register setting Figure 10-79. Example of Contents of Registers for UART Reception (UART0) (1/2) (a) Serial mode register 0n (SMR0nH, SMR0nL) Symbol: SMR0nH Symbol: SMR0nL CKS0n CCS0n STS0n SIS0n0 MD0n1 MD0n0 0: Normal reception...
  • Page 316 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-79. Example of Contents of Registers for UART Reception (UART0) (2/2) (e) Serial clock output register 0 (CKO0) … The register that not used in this mode. Symbol: CKO0 CKO00 × (f) Serial output register 0 (SO0) … The register that not used in this mode.
  • Page 317 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (2) Operation procedure Figure 10-80. Initial Setting Procedure for UART Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 318 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-82. Procedure for Resuming UART Reception Starting setting for resumption Completing master Stop the target for communication or (Essential) preparations? wait Re-set the register to change the operation (Selective) Changing setting of the SPS0 register clock setting.
  • Page 319 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (3) Processing flow Figure 10-83. UART Reception Timing Chart SS0n ST0n SE0n Receive data 3 SDR0nL Receive data 1 Receive data 2 RxDq pin Receive data 3 Receive data 2 Receive data 1...
  • Page 320 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT Figure 10-84. Flowchart of UART Reception Starting UART communication For the initial setting, refer to Figure 10-80. (setting to mask for error interrupt) SAU default setting Setting storage area of the receive data, number of communication...

  • Page 321: Calculating Baud Rate

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.6.3 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (f ) frequency of target channel} ÷ (SDR0nH[7:1] + 1) ÷ 2 [bps] Caution Setting serial data register 0n (SDR0nH) SDR0nH[7:1] = (0000000B to 0000001B) is prohibited.
  • Page 322 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
  • Page 323 R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.

  • Page 324: Procedure For Processing Errors That Occurred During Uart (Uart0) Communication

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 10 SERIAL ARRAY UNIT 10.6.4 Procedure for processing errors that occurred during UART (UART0) communication The procedure for processing errors that occurred during UART (UART0) communication is described in Figures 10-86 and 10-87. Figure 10-86. Processing Procedure in Case of Parity Error or Overrun Error...

  • Page 325: Chapter 11 Interrupt Functions

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS CHAPTER 11 INTERRUPT FUNCTIONS The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. Number of interrupt sources Maskable interrupts External Internal 11.1 Interrupt Function Types...
  • Page 326 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS Table 11-1. Interrupt Source List Interrupt Source Name Trigger INTWDTI Watchdog timer interval Internal 0004H (75% of overflow time +3/(4 x f INTP0 Pin input edge detection External 0006H INTP1 0008H INTST0/ UART0 transmission transfer end or buffer...
  • Page 327 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-1. Basic Configuration of Interrupt Function (1/2) (a) Internal maskable interrupt Internal bus ISP1 ISP0 Vector table Interrupt Priority controller address generator request Standby release signal (b) External maskable interrupt (INTPn) Internal bus...
  • Page 328 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-1. Basic Configuration of Interrupt Function (2/2) (c) External maskable interrupt (INTKR) Internal bus Key return mode ISP1 ISP0 register (KRM0) KRMn Vector table Key interrupt Priority controller address generator KRn pin input...

  • Page 329: Registers Controlling Interrupt Functions

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS 11.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag registers (IF0L, IF0H) • Interrupt mask flag registers (MK0L, MK0H) • Priority specification flag registers (PR00L, PR00H, PR10L, PR10H) •...

  • Page 330: Interrupt Request Flag Registers (If0L, If0H)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS 11.3.1 Interrupt request flag registers (IF0L, IF0H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when the interrupt request is acknowledged, a reset signal is generated, or an instruction is executed.

  • Page 331: Interrupt Mask Flag Registers (Mk0L, Mk0H)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS 11.3.2 Interrupt mask flag registers (MK0L, MK0H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. The MK0L, and MK0H registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.

  • Page 332: Priority Specification Flag Registers (Pr00L, Pr00H, Pr10L, Pr10H)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS 11.3.3 Priority specification flag registers (PR00L, PR00H, PR10L, PR10H) The priority specification flag registers are used to set the priority level of the corresponding maskable interrupt. A priority level is set by using the PR0xy and PR1xy registers in combination (0xy = 0L, 0H).
  • Page 333 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR10L, PR10H) Address: FFFE8H After reset: FFH Symbol <7> <6> <5> <4> <3> <2> <1> <0> PR00L TMPR000 TMPR001H SREPR00 SRPR00 STPR00 PPR01 PPR00...

  • Page 334: External Interrupt Rising Edge Enable Register (Egp0)

    R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS 11.3.4 External interrupt rising edge enable register (EGP0), external interrupt falling edge enable register (EGN0) These registers specify the valid edge for INTP0, and INTP1. The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 335 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS 11.3.5 Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW.
  • Page 336 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS 11.4 Interrupt Servicing Operations 11.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt servicing is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
  • Page 337 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-7. Interrupt Request Acknowledgment Processing Algorithm Start xxIF = 1? Yes (interrupt request generation) xxMK = 0? Interrupt request held pending No (Low priority) (xxPR 1, xx < (ISP1, ISP0) Interrupt request held pending...
  • Page 338 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-8. Interrupt Request Acknowledgment Timing (Minimum Time) 8 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing xxIF 11 clocks Remark 1 clock: 1/f : CPU clock) Figure 11-9.
  • Page 339 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS 11.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched.
  • Page 340 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS Table 11-4. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request Software Interrupt Priority Level 0 Priority Level 1 Priority Level 2 Priority Level 3...
  • Page 341 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy...
  • Page 342 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 00)
  • Page 343 R7F0C80112ESP, R7F0C80212ESP CHAPTER 11 INTERRUPT FUNCTIONS 11.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
  • Page 344 R7F0C80112ESP, R7F0C80212ESP CHAPTER 12 KEY INTERRUPT FUNCTION CHAPTER 12 KEY INTERRUPT FUNCTION 12.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a rising edge/falling edge to the key interrupt input pins (KR0 to KR5).
  • Page 345 R7F0C80112ESP, R7F0C80212ESP CHAPTER 12 KEY INTERRUPT FUNCTION Figure 12-1. Block Diagram of Key Interrupt KRF0 KREG KRM00 KRMD KRF1 KREG KRM01 KRMD KRF2 KREG KRM02 KRMD KRF3 KRM03 KREG KRMD KRF4 KREG KRM04 INTKR KRMD KRF5 KREG KRM05 KRMD 12.3 Register Controlling Key Interrupt The key interrupt function is controlled by the following five registers: •...
  • Page 346 R7F0C80112ESP, R7F0C80212ESP CHAPTER 12 KEY INTERRUPT FUNCTION 12.3.1 Key return control register (KRCTL) This register controls the usage of the key return flags (KRF0 to KRF5) and sets the detection edge. The KRCTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 347 R7F0C80112ESP, R7F0C80212ESP CHAPTER 12 KEY INTERRUPT FUNCTION 12.3.2 Key return mode register (KRM0) This register sets the key interrupt mode. The KRM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
  • Page 348 R7F0C80112ESP, R7F0C80212ESP CHAPTER 12 KEY INTERRUPT FUNCTION 12.3.3 Key return flag register (KRF) This register controls the key return flags (KRF0 to KRF5). The KRF register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
  • Page 349 R7F0C80112ESP, R7F0C80212ESP CHAPTER 12 KEY INTERRUPT FUNCTION 12.4 Key Interrupt Operation <R> 12.4.1 When not using the key interrupt flag (KRMD = 0) A key interrupt (INTKR) is generated when the valid edge specified by the setting of the KREG bit is input to a key interrupt pin (KR0 to KR5).
  • Page 350 R7F0C80112ESP, R7F0C80212ESP CHAPTER 12 KEY INTERRUPT FUNCTION 12.4.2 When using the key interrupt flag (KRMD = 1) A key interrupt (INTKR) is generated when the valid edge specified by the setting of the KREG bit is input to a key interrupt pin (KR0 to KR5).
  • Page 351 R7F0C80112ESP, R7F0C80212ESP CHAPTER 12 KEY INTERRUPT FUNCTION The operation when a valid edge is input to multiple key interrupt input pins is shown in Figure 12-9 below. A falling edge is also input to the KR1 and KR5 pins after a falling edge was input to the KR0 pin (when KREG = 0). The KRF1 bit is set when the KRF0 bit is cleared.
  • Page 352 R7F0C80112ESP, R7F0C80212ESP CHAPTER 12 KEY INTERRUPT FUNCTION The operation when a valid edge is input to the KR5 pins without generating a key interrupt (INTKR) is shown in Figure 12-10 below. A falling edge is also input to the KR1 and KR5 pins after a falling edge was input to the KR0 pin (when KREG = 0).
  • Page 353 R7F0C80112ESP, R7F0C80212ESP CHAPTER 13 STANDBY FUNCTION CHAPTER 13 STANDBY FUNCTION 13.1 Overview The standby function reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high- speed on-chip oscillator is operating before the HALT mode is set, oscillation of clock continues.
  • Page 354 R7F0C80112ESP, R7F0C80212ESP CHAPTER 13 STANDBY FUNCTION 13.2 Standby Function Operation 13.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operating statuses in the HALT mode are shown below. <R> Caution Because the interrupt request signal is used to clear the HALT mode, if there is an interrupt source with the interrupt request flag set (1) and the interrupt mask flag cleared (0), the HALT mode is not entered.
  • Page 355 R7F0C80112ESP, R7F0C80212ESP CHAPTER 13 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
  • Page 356 R7F0C80112ESP, R7F0C80212ESP CHAPTER 13 STANDBY FUNCTION 13.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. Caution If there is an interrupt source whose corresponding interrupt request flag is set (1) and interrupt mask flag is cleared (0), the interrupt request signal is used to release the STOP mode.
  • Page 357 R7F0C80112ESP, R7F0C80212ESP CHAPTER 13 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two sources. (a) STOP mode release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
  • Page 358 R7F0C80112ESP, R7F0C80212ESP CHAPTER 13 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
  • Page 359 R7F0C80112ESP, R7F0C80212ESP CHAPTER 14 RESET FUNCTION CHAPTER 14 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of selectable power-on-reset (SPOR) circuit...
  • Page 360 R7F0C80112ESP, R7F0C80212ESP CHAPTER 14 RESET FUNCTION R01UH0400EJ0100 Rev. 1.00 Sep. 20, 2013...
  • Page 361 R7F0C80112ESP, R7F0C80212ESP CHAPTER 14 RESET FUNCTION 14.1 Timing of Reset Operation This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level on the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts.
  • Page 362 R7F0C80112ESP, R7F0C80212ESP CHAPTER 14 RESET FUNCTION Release from the reset state is automatic in the cases of a reset due to the watchdog timer overflow or a reset due to the execution of an illegal instruction. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts.
  • Page 363 R7F0C80112ESP, R7F0C80212ESP CHAPTER 14 RESET FUNCTION 14.2 Operation States During Reset Periods Table 14-1 shows the operation states during reset periods. Table 14-2 shows the state of the hardware after acceptance of a reset. Table 14-1. Operation States During Reset Period...
  • Page 364 R7F0C80112ESP, R7F0C80212ESP CHAPTER 14 RESET FUNCTION Table 14-2. State of Hardware After Acceptance of Reset (1/3) Note 1 Hardware After Acceptance of Reset Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP)
  • Page 365 R7F0C80112ESP, R7F0C80212ESP CHAPTER 14 RESET FUNCTION Table 14-2. State of Hardware After Acceptance of Reset (2/3) After Acceptance of Hardware Note Reset A/D converter A/D conversion result lower bit storage register (ADCRL) A/D conversion result higher bit storage register (ADCRH)
  • Page 366 R7F0C80112ESP, R7F0C80212ESP CHAPTER 14 RESET FUNCTION Table 14-2. State of Hardware After Acceptance of Reset (3/3) After Acceptance of Hardware Note 1 Reset Reset function Reset control flag register (RESF) Note 2 Interrupt Request flag registers 0L, 0H (IF0L, IF0H)
  • Page 367 R7F0C80112ESP, R7F0C80212ESP CHAPTER 14 RESET FUNCTION 14.3 Register for Confirming Reset Source 14.3.1 Reset control flag register (RESF) Many internal reset generation sources exist in the RL78 Microcontroller. The reset control flag register (RESF) is used to store which source has generated the reset request.
  • Page 368 R7F0C80112ESP, R7F0C80212ESP CHAPTER 14 RESET FUNCTION Figure 14-6. Procedure for Checking Reset Source After receiving a reset Read the RESF register (clear the RESF) Read the RESF register Store the value of the RESF register in any RAM TRAP of RESF...
  • Page 369 R7F0C80112ESP, R7F0C80212ESP CHAPTER 15 SELECTABLE POWER-ON-RESET CIRCUIT CHAPTER 15 SELECTABLE POWER-ON-RESET CIRCUIT 15.1 Functions of Selectable Power-on-reset Circuit <R> The selectable power-on-reset (SPOR) circuit has the following functions. • Generates internal reset signal at power on. ≥ V The reset signal is released when the supply voltage exceeds the detection voltage (V SPOR •...
  • Page 370 R7F0C80112ESP, R7F0C80212ESP CHAPTER 15 SELECTABLE POWER-ON-RESET CIRCUIT 15.2 Configuration of Selectable Power-on-reset Circuit The block diagram of the selectable power-on-reset circuit is shown in Figure 15-1. Figure 15-1. Block Diagram of Selectable Power-on-reset Circuit <R> − Internal reset signal Option byte (000C1H)
  • Page 371 R7F0C80112ESP, R7F0C80212ESP CHAPTER 15 SELECTABLE POWER-ON-RESET CIRCUIT <R> 15.3 Operation of Selectable Power-on-reset Circuit Specify the voltage detection level by using the option byte 000C1H. The internal reset signal is generated at power on. The internal reset status is retained until the supply voltage (V ) exceeds the voltage detection level (V ).
  • Page 372 R7F0C80112ESP, R7F0C80212ESP CHAPTER 15 SELECTABLE POWER-ON-RESET CIRCUIT <R> 15.4 Cautions for Selectable Power-on-reset Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the SPOR detection voltage ), the system may be repeatedly reset and released from the reset status. In this case, the time from release...
  • Page 373 CHAPTER 16 OPTION BYTE 16.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory of the R7F0C80112ESP, R7F0C80212ESP form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).
  • Page 374 R7F0C80112ESP, R7F0C80212ESP CHAPTER 16 OPTION BYTE 16.2 Format of User Option Byte The format of user option byte is shown below. Figure 16-1. Format of User Option Byte (000C0H) Address: 000C0H WDTON WDCS2 WDCS1 WDCS0 WDSTBYON WDTON Operation control of watchdog timer counter...
  • Page 375 R7F0C80112ESP, R7F0C80212ESP CHAPTER 16 OPTION BYTE Figure 16-2. Format of User Option Byte (000C1H) Address: 000C1H PORTSELB SPORS1 SPORS0 • Setting of SPOR detection voltage Detection voltage Option byte setting value SPORS1 SPORS0 SPOR SPDR Rising edge Falling edge 4.28 V 4.00 V...
  • Page 376 R7F0C80112ESP, R7F0C80212ESP CHAPTER 16 OPTION BYTE 16.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 16-4. Format of On-chip Debug Option Byte (000C3H) Address: 000C3H OCDENSET OCDENSET Control of on-chip debug operation Disables on-chip debug operation.
  • Page 377 R7F0C80112ESP, R7F0C80212ESP CHAPTER 16 OPTION BYTE 16.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the link option in addition to describing to the source. When doing so, the contents set by using the link option take precedence, even if descriptions exist in the source, as mentioned below.
  • Page 378 R7F0C80112ESP, R7F0C80212ESP CHAPTER 17 FLASH MEMORY CHAPTER 17 FLASH MEMORY The RL78 microcontroller incorporates the flash memory to which a program can be written, erased, and overwritten. FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 8 bytes...
  • Page 379 Remark FL-PR5 and FA series are products of Naito Densei Machida Mfg. Co., Ltd. Table 17-1. Wiring Between R7F0C80112ESP, R7F0C80212ESP and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Programmer Pin Name Pin No.
  • Page 380 R7F0C80112ESP, R7F0C80212ESP CHAPTER 17 FLASH MEMORY 17.1.1 Programming environment The environment required for writing a program to the flash memory of the RL78 microcontroller is illustrated below. Figure 17-1. Environment for Writing Program to Flash Memory PG-FP5, FL-PR5 RS-232C RESET...
  • Page 381 R7F0C80112ESP, R7F0C80212ESP CHAPTER 17 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the RL78 microcontroller. See the manuals of PG-FP5, FL-PR5, or E1 on-chip debugging emulator for details. Table 17-2. Pin Connection Dedicated Flash Memory Programmer...
  • Page 382 R7F0C80112ESP, R7F0C80212ESP CHAPTER 17 FLASH MEMORY <R> 17.2 Writing to Flash Memory by Using External Device (that Incorporates UART) On-board data writing to the internal flash memory is possible by using the RL78 microcontroller and an external device (a microcontroller or ASIC) connected to a UART.
  • Page 383 R7F0C80112ESP, R7F0C80212ESP CHAPTER 17 FLASH MEMORY 17.3 Connection of Pins on Board To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
  • Page 384 R7F0C80112ESP, R7F0C80212ESP CHAPTER 17 FLASH MEMORY 17.3.3 Port pins In the flash memory programming mode, all the pins not used for flash memory programming enter the same status as that immediately after reset. If an external device connected to the ports does not recognize the port status immediately...
  • Page 385 R7F0C80112ESP, R7F0C80212ESP CHAPTER 17 FLASH MEMORY 17.4 Serial Programming Method 17.4.1 Serial programming procedure The following figure illustrates the procedure to rewrite the contents of the code flash memory by serial programming. Figure 17-6. Code Flash Memory Manipulation Procedure Start...
  • Page 386 R7F0C80112ESP, R7F0C80212ESP CHAPTER 17 FLASH MEMORY <R> 17.4.2 Flash memory programming mode To rewrite the contents of the code flash memory by serial programming, the flash memory programming mode must be entered. <When performing serial programming by using the dedicated flash memory programmer>...
  • Page 387 R7F0C80112ESP, R7F0C80212ESP CHAPTER 17 FLASH MEMORY 17.4.3 Communication mode Communication mode of the RL78 microcontroller is as follows. Table 17-5. Communication Mode Note 1 Communication Standard Setting Pin Used Mode Note 2 Port Speed Frequency Multiply Rate − − 1-line mode...
  • Page 388 Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
  • Page 389 For the target system which uses the multi-use feature of RESET pin, its connection to an external circuit should be isolated. <R> Figure 18-2. Connection Example of E1 On-chip Debugging Emulator and R7F0C80112ESP, R7F0C80212ESP (When using to the alternative function of RESET pin) Target connector...
  • Page 390 To perform communication between the RL78 microcontroller and E1 on-chip debugging emulator, as well as each debug function, the securing of memory space must be done beforehand. If Renesas Electronics assembler or compiler is used, the items can be set by using linker options. (1) Securement of memory space The shaded portions in Figure 18-3 are the areas reserved for placing the debug monitor program, so user programs or data cannot be allocated in these spaces.
  • Page 391 R7F0C80112ESP, R7F0C80212ESP CHAPTER 18 ON-CHIP DEBUG FUNCTION <R> Figure 18-3. Memory Spaces Where Debug Monitor Programs Are Allocated Code flash memory Internal RAM Use prohibited SFR area Note 1 FFEDFH 4 bytes Note 3 FFEDCH 000D8H Stack area for debugging...
  • Page 392 R7F0C80112ESP, R7F0C80212ESP CHAPTER 19 BCD CORRECTION CIRCUIT CHAPTER 19 BCD CORRECTION CIRCUIT 19.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/subtracting the BCD correction result register (BCDADJ).
  • Page 393 R7F0C80112ESP, R7F0C80212ESP CHAPTER 19 BCD CORRECTION CIRCUIT 19.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1>...
  • Page 394 R7F0C80112ESP, R7F0C80212ESP CHAPTER 19 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register.
  • Page 395 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET CHAPTER 20 INSTRUCTION SET This chapter lists the instructions for the RL78-S1 core of the RL78 microcontroller. For details of each operation and operation code, refer to the separate document RL78 Microcontrollers User’s Manual: software (R01US0015).
  • Page 396 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET 20.1 Conventions Used in Operation List 20.1.1 Operand identifiers and specification methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them.
  • Page 397 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET 20.1.2 Description of operation column The operation when the instruction is executed is shown in the “Operation” column using the following symbols. Table 20-2. Symbols in “Operation” Column Symbol Function A register; 8-bit accumulator...
  • Page 398 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET 20.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols. Table 20-3. Symbols in “Flag” Column Symbol...
  • Page 399 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET 20.2 Operation List Table 20-5. Operation List (1/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − r ← byte 8-bit data r, #byte transfer − PSW ← byte ×...
  • Page 400 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (2/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY A ← sfr − 8-bit data A, sfr transfer − sfr ← A sfr, A A ←...
  • Page 401 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (3/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY A ← (HL + B) 8-bit data A, [HL+B] transfer − (HL + B) ← A [HL+B], A A ←...
  • Page 402 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET <R> Table 20-5. Operation List (4/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY A ←→ (HL+B) − 8-bit data A, [HL+B] transfer − A ←→ ((ES, HL)+B) A, ES:[HL+B] −...
  • Page 403 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (5/17) <R> Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY AX ← (DE) 16-bit MOVW AX, [DE] data (DE) ← AX − [DE], AX transfer AX ←...
  • Page 404 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET <R> Table 20-5. Operation List (6/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY BC ← (addr16) 16-bit MOVW BC, !addr16 data BC ← (ES, addr16) BC, ES:!addr16 transfer DE ←...
  • Page 405 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (7/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY A, CY ← A+byte+CY − 8-bit ADDC A, #byte × × × operation − (saddr), CY ← (saddr) +byte+CY saddr, #byte ×...
  • Page 406 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (8/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY A, CY ← A – byte – CY − 8-bit SUBC A, #byte × ×...
  • Page 407 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (9/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY A ← A∨byte − 8-bit A, #byte × operation − (saddr) ← (saddr)∨byte saddr, #byte ×...
  • Page 408 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (10/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − 8-bit A, #byte A – byte × × × operation !addr16, #byte (addr16) – byte ×...
  • Page 409 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (11/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY AX, CY ← AX+word − 16-bit ADDW AX, #word × × × operation − AX, CY ← AX+AX AX, AX ×...
  • Page 410 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (12/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY r ← r+1 − Increment/ × × decrement − (addr16) ← (addr16)+1 !addr16 × ×...
  • Page 411 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (13/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY ← A ← A − Rotate A, 1 (CY, A )×1 × − ← A ←...
  • Page 412 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (14/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY CY ← CY ∨ A.bit − XOR1 CY, A.bit × manipulate − CY ← CY ∨ PSW.bit CY, PSW.bit...
  • Page 413 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (15/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY (SP – 2) ← (PC+2) , (SP – 3) ← (PC+2) CALL − Call/ (SP – 4) ← (PC+2) , PC ←...
  • Page 414 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (16/17) Instruction Mnemon Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY (SP − 1) ← PSW, (SP − 2) ← 00H, − Stack PUSH manipulate SP ← SP−2 −...
  • Page 415 R7F0C80112ESP, R7F0C80212ESP CHAPTER 20 INSTRUCTION SET Table 20-5. Operation List (17/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY PC ← PC + 4 + jdisp8 if (saddr).bit = 0 − Note3 Condition saddr.bit, $addr20 al branch −...
  • Page 416 Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. Use this product within the voltage range from 2.57 to 5.5 V because the detection voltage (V ) of <R>...
  • Page 417 CHAPTER 21 ELECTRICAL SPECIFICATIONS 21.1 Absolute Maximum Ratings = 25°C) Parameter Symbols Conditions Ratings Unit −0.5 to +6.5 Supply Voltage −0.3 to V Note Input Voltage + 0.3 −0.3 to V Output Voltage + 0.3 −40 Output current, high Per pin −40 Total of all pins −140 mA...
  • Page 418 CHAPTER 21 ELECTRICAL SPECIFICATIONS 21.2 Oscillator Characteristics 21.2.1 On-chip oscillator characteristics = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit <R> High-speed on-chip oscillator 1.25 Note 1, 2 oscillation frequency = −40 to +85°C −3...
  • Page 419 CHAPTER 21 ELECTRICAL SPECIFICATIONS 21.3 DC Characteristics 21.3.1 Pin characteristics = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit −10.0 Note 1 Note 3 Output current, high , P01, P02 to Per pin P04, P40...
  • Page 420 CHAPTER 21 ELECTRICAL SPECIFICATIONS Notes 1. This pin does not output a high level in N-ch open-drain (V tolerant) mode. 2. This is the output current value under conditions where the duty factor ≤ 70%. The output current value when the duty factor > 70% can be calculated with the following expression (when changing the duty factor to n%).
  • Page 421 CHAPTER 21 ELECTRICAL SPECIFICATIONS 21.3.2 Supply current characteristics = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1 Supply current Operatin Basic = 20 MHz = 3.0 V, 5.0 V 0.91 g mode operation...
  • Page 422 CHAPTER 21 ELECTRICAL SPECIFICATIONS 21.4 AC Characteristics = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit 2.7 V ≤ V ≤ 5.5 V μ Instruction cycle (minimum Main system clock (f 0.05 MAIN...
  • Page 423 CHAPTER 21 ELECTRICAL SPECIFICATIONS Interrupt Request Input Timing INTL INTH INTP0, INTP1 RESET Input Timing RESET R01UH0400EJ0100 Rev. 1.00 Sep. 20, 2013...
  • Page 424 MAX. Unit Transfer rate Theoretical value of the Mbps maximum transfer rate = 20 MHz UART mode connection diagram TxD0 R7F0C80112ESP, User's device R7F0C80212ESP RxD0 UART mode bit width (reference) 1/transfer rate High-/low-bit width Baud rate error tolerance TxD0 RxD0 Caution Select the normal output mode for the TxD0 pin by using port output mode register 0 (POM0).
  • Page 425 CHAPTER 21 ELECTRICAL SPECIFICATIONS (2) CSI mode (master mode, SCKp...internal clock output) = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.7 V ≤ V ≤ 5.5 V Note 1 SCKp cycle time KCY1...
  • Page 426 CHAPTER 21 ELECTRICAL SPECIFICATIONS (3) CSI mode (slave mode, SCKp…external clock input) = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.7 V ≤ V ≤ 5.5 V SCKp cycle time = 20 MHz KCY2...
  • Page 427 CHAPTER 21 ELECTRICAL SPECIFICATIONS CSI mode connection diagram SCK00 R7F0C80112ESP, SI00 SO User’s device R7F0C80212ESP SO00 CSI mode serial transfer timing (When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1.) KCY1, 2 KL1, 2...
  • Page 428 CHAPTER 21 ELECTRICAL SPECIFICATIONS 21.6 Analog Characteristics 21.6.1 A/D converter characteristics (Target ANI pin : ANI0 to ANI3) = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution ±1.7 ±3.1...
  • Page 429 CHAPTER 21 ELECTRICAL SPECIFICATIONS 21.6.3 SPOR circuit characteristics = −40 to +85°C, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection supply voltage Power supply rise time 4.28 SPOR0 Power supply fall time 4.00 Power supply rise time 2.90 SPOR1 Power supply fall time...
  • Page 430 When using flash memory programmer. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. <R> 21.8 Dedicated Flash Memory Programmer Communication (UART) = - 40 to + 85 °C, 2.4 V ≤ V ≤...
  • Page 431 CHAPTER 21 ELECTRICAL SPECIFICATIONS <R> 21.9 Timing of Entry to Flash Memory Programming Modes Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the SPOR reset must be released before the SUINIT communication for the initial setting external reset is released. after the external reset is released μ...
  • Page 432 4.40 0.10 condition. ± 1.00 0.20 0.08 0.17 − 0.07 0.50 0.13 0.10 ° + ° ° − 0.25 (T.P.) ± 0.60 0.15 0.25 MAX. 0.15 MAX. 2012 Renesas Electronics Corporation. All rights reserved. R01UH0400EJ0100 Rev. 1.00 Sep. 20, 2013...
  • Page 433 CHAPTER 3 CPU ARCHITECTURE p. 10 Modification of CHAPTER 3 CPU ARCHITECTURE. p. 11 Addition of Note to Figure 3-1. Memory Map for the R7F0C80112ESP. p. 12 Addition of Note to Figure 3-2. Memory Map for the R7F0C80212ESP. p. 17 Modification of Figure 3-3.
  • Page 434 R7F0C80112ESP, R7F0C80212ESP APPENDIX A REVISION HISTORY (2/3) Page Description Classification p. 106 Modification of Figure 6-24. Operation Timing (In Interval Timer Mode). p. 108 Modification of Figure 6-26. Operation Timing (In Capture Mode: Input Pulse Interval Measurement). p. 109 Modification of Figure 6-27. Operation Timing (In One-count Mode).
  • Page 435 R7F0C80112ESP, R7F0C80212ESP. p. 375 Modification of Figure 18-2. Connection Example of E1 On-chip Debugging Emulator and R7F0C80112ESP, R7F0C80212ESP (When using to the alternative function of RESET pin). p. 377 Modification of Figure 18-3. Memory Spaces Where Debug Monitor Programs Are Allocated.
  • Page 436 R7F0C80112ESP, R7F0C80212ESP User’s Manual: Hardware Publication Date: Rev.0.90 Jan 30, 2013 Rev.1.00 Sep 20, 2013 Published by: Renesas Electronics Corporation...
  • Page 437 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada...
  • Page 438 R7F0C80112ESP, R7F0C80212ESP R01UH0400EJ0100...

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