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Abov A96L414 User Manual

Cmos single-chip 8-bit mcu with 10-bit adc and operational amplifier
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Introduction
This user's manual contains complete information for application developers who use
A96L414/A96L416 for their specific needs.
A96L414/A96L416 is an advanced 8-bit CMOS MCU with 8/16Kbytes of Flash. Offering the
convenience of Flash multi-programming features, this device can provide fire alarm and single type
smoke detectors systems with a simple, robust, and cost effective solution as a complete set of
semiconductor product to implement the smart alarm systems.
Reference documents
A96L414/A96L416 Datasheet: It includes information on mechanical characteristics,
development methods, and ordering information. It is available at ABOV website,
https://www.abovsemi.com.
SDK 51 User's guide (System Design Kit): It was released by Intel in 1982. It contains all of
components of a single board computer based on Intel's 8051 single chip microcomputer.
Information on Mentor Graphics 8051 microcontroller: This technical document is provided at
Mentor® website,
CMOS Single-chip 8-bit MCU with 10-bit ADC

Figure 1. A96L414/A96L416 Block Diagram

https://www.mentor.com/products/ip/peripheral/microcontroller/
Global Top Smart MCU Innovator
www.abovsemi.com
A96L414/A96L416
User's Manual
and Operational Amplifier
User's Manual Version 1.01

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  • Page 1: Figure 1. A96L414/A96L416 Block Diagram

    This user’s manual contains complete information for application developers who use A96L414/A96L416 for their specific needs. A96L414/A96L416 is an advanced 8-bit CMOS MCU with 8/16Kbytes of Flash. Offering the convenience of Flash multi-programming features, this device can provide fire alarm and single type smoke detectors systems with a simple, robust, and cost effective solution as a complete set of semiconductor product to implement the smart alarm systems.

  • Page 2: Table Of Contents

    Contents A96L414/A96L416 User’s manual Contents Device overview ........................ 14 Block diagram ........................16 Pinouts ..........................17 Pin description ........................18 GPIO port structure ......................21 External interrupt I/O port structure ................... 22 Program memory....................... 23 Internal data memory ......................24 Extended SFR and data memory area ................
  • Page 3 A96L414/A96L416 User’s manual Contents Multi interrupt ........................55 Interrupt enable accept timing ................... 56 Interrupt Service Routine address ..................56 Saving/ restore general-purpose registers ................ 57 Interrupt timing ........................58 Interrupt register ........................ 59 6.11.1 Interrupt Enable registers (IE, IE1, IE2, IE3) ............59 6.11.2 Interrupt Priority registers (IP, IP1) ...............
  • Page 4 Contents A96L414/A96L416 User’s manual UART transmitter....................... 99 13.8.1 Sending Tx data ....................99 13.8.2 Transmitter flag and interrupt ................99 13.8.3 Parity generator ....................100 13.8.4 Disabling transmitter ................... 100 UART receiver ......................... 101 13.9.1 Receiving Rx data ....................101 13.9.2 Receiver flag and interrupt .................
  • Page 5 A96L414/A96L416 User’s manual Contents External RESETB input ....................149 Brown out detector processor ..................150 18.5.1 Block diagram ..................... 150 18.5.2 Internal reset and BOD reset in timing diagram ..........150 Register map ........................151 Register description ......................152 Flash program ROM structure ..................155 Register map ........................
  • Page 6 Contents A96L414/A96L416 User’s manual 16 SOPN package information ..................199 Compiler .......................... 201 OCD (On-Chip Debugger) emulator and debugger ............201 Programmer ........................202 24.3.1 E-PGM+ ......................202 24.3.2 OCD emulator ..................... 202 24.3.3 Gang programmer ....................203 MTP programming......................204 24.4.1 On-board programming ..................
  • Page 7 A96L414/A96L416 User’s manual List of figures List of figures Figure 1. A96L414/A96L416 Block Diagram ................... 1 Figure 2. A96L414/A96L416 Block Diagram ..................16 Figure 3. A96L414FR/A96L416FR 20 TSSOP Pinouts ................ 17 Figure 4. A96L414AE/A96L416AE 16 SOPN Pinouts ................17 Figure 5. General Purpose I/O Port Structure ..................21 Figure 6.
  • Page 8 List of figures A96L414/A96L416 User’s manual Figure 49. Start Bit Sampling ......................102 Figure 50. Data and Parity Bit Sampling ..................... 103 Figure 51. Stop Bit Sampling and Next Stop Bit Sampling ..............103 Figure 52. SPI Block Diagram ......................105 Figure 53.
  • Page 9 Figure 114. 20 TSSOP Package Outline ..................... 198 Figure 115. 16 SOPN Package Outline ....................199 Figure 116. A96L414/ A96L416 Device Numbering Nomenclature ............ 200 Figure 117. OCD and Pin Descriptions ....................201 Figure 118. E-PGM+ (Single Writer) and Pin Descriptions ..............202 Figure 119.
  • Page 10 List of figures A96L414/A96L416 User’s manual ..225 Figure 132. Example circuit using IR LED and Blue LED(16 SOPN) ..........225 Figure 133. Example circuit using only IR LED(20 TSSOP) ............... 226...
  • Page 11 A96L414/A96L416 User’s manual List of figures Figure 134. Example circuit using IR LED and Blue LED (20 TSSOP) ..........227...
  • Page 12 Table 28. Reset Operation Register Map .................... 151 Table 29. Flash Memory Register Map ....................156 Table 30. Protection Area Size and its Relative Information on A96L414 ........... 158 Table 31. Protection Area Size and its Relative Information on A96L416 ........... 158 Table 32.
  • Page 13 Table 51. Internal Data Flash Characteristics ..................193 Table 52. I/O Capacitance Characteristics ..................193 Table 53. A96L414/A96L416 Device Ordering Information ..............200 Table 54. Specification of E-Gang4 and E-Gang6 ................203 Table 55. Pins for MTP Programming ....................204 Table 56.

  • Page 14: Device Overview

    A96L414/A96L416 User’s manual Description A96L414/A96L416 is an advanced CMOS 8-bit microcontroller with 8/16Kbytes of FLASH. This is a powerful microcontroller which provides low power consumption and cost effective solution to smoke detector applications. A96L414/A96L416 supports power down modes to reduce power consumption.
  • Page 15 A96L414/A96L416 User’s manual 1. Description Table 1. A96L414/A96L416 Device Features and Peripheral Counts (continued) Peripheral A96L414/A96L416 Constant sink current generator 2-ch  16-steps selectable  Max. 274mA sink current  USART UART + SPI 8-bit UART x 1-ch  8-bit SPI x 1-ch ...

  • Page 16: Block Diagram

    1. Description A96L414/A96L416 User’s manual Block diagram Figure 2 describes A96L414/A96L416 in a block diagram. Flash 8/16KB IRAM + XRAM CORE 256B + 256/768B M8051 Data Flash 256B On-chip debug In-system programming General purpose I/O 18 ports normal I/O Power control...

  • Page 17: Pinouts And Pin Descriptions

    A96L414/A96L416 User’s manual 2. Pinouts and pin descriptions Pinouts and pin descriptions In this chapter, A96L414/A96L416 pinouts and pin descriptions are introduced. Pinouts NOTE: For the On-Chip Debugging, ISP assigns P1[2:3] pins for DSCL and DSDA respectively. Figure 3. A96L414FR/A96L416FR 20 TSSOP Pinouts NOTES: For the On-Chip Debugging, ISP assigns P1[2:3] pins for DSCL and DSDA respectively.

  • Page 18: Pin Description

    2. Pinouts and pin descriptions A96L414/A96L416 User’s manual Pin description Table 2. 20 TSSOP Pin Description Pin name Function @reset Shared with The port 0 is a bit-programmable Input AN0/OP1OUT/EINT0 I/O port which can be configured AN1/OP1N/EINT1 as an input (P00/P01/P06/P07:...
  • Page 19 A96L414/A96L416 User’s manual 2. Pinouts and pin descriptions Table 2. 20 TSSOP Pin Description (continued) Pin name Function @reset Shared with Timer 2 interval output P20/PWM2O/SDA/EINT12 PWM0O Timer 0 pulse output P11/T0O/EINT10 PWM1O Timer 1 pulse output P14/T1O/SCL/EINT11 PWM2O Timer 2 pulse output...
  • Page 20 2. Pinouts and pin descriptions A96L414/A96L416 User’s manual Table 2. 20 TSSOP Pin Description (continued) Pin name Function @reset Shared with I2C clock input/output Input P14/T1O/PWM1O/SCL (P21/EC2/SCK) I2C data input/output Input P20/T2O/PWM2O/SDA (P15/AN6/LDO23/SS) RESETB System reset pin with a pull-up...

  • Page 21: Gpio Port Structure

    A96L414/A96L416 User’s manual 3. Port structures Port structures GPIO port structure Level Shift (VDC to ExtVDD) Level Shift (ExtVDD to VDC) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER CMOS or Schmitt Level...

  • Page 22: External Interrupt I/O Port Structure

    3. Port structures A96L414/A96L416 User’s manual External interrupt I/O port structure Level Shift (VDC to ExtVDD) Level Shift (ExtVDD to VDC) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER EXTERNAL INTERRUPT POLARITY REG.

  • Page 23: Memory Organization

    (XRAM) is 256/768 bytes. Program memory A 16-bit program counter is capable of addressing up to 64 Kbytes, but A96L414/A96L416 has only 8/16 Kbytes program memory space. After reset, CPU begins execution from location 0000H. Each interrupt is assigned to a fixed location of the program memory. The interrupt causes the CPU to jump to that location, where it commences an execution of a service routine.

  • Page 24: Internal Data Memory

    4. Memory organization A96L414/A96L416 User’s manual FFFFH 3FFFH 16K Bytes NOTE: 16 Kbytes memory includes Interrupt Vector Region. 0000H Figure 7. Program Memory More detailed description of program memory is introduced in chapter 19. Flash memory later part in this document.

  • Page 25: Figure 8. Internal Data Memory Map

    A96L414/A96L416 User’s manual 4. Memory organization Figure 8. Internal Data Memory Map The lower 128 bytes of RAM are present in all 8051 devices as mapped in Figure 9. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7.

  • Page 26: Figure 9. Lower 128 Bytes Internal Ram

    4. Memory organization A96L414/A96L416 User’s manual 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58...

  • Page 27: Extended Sfr And Data Memory Area

    4. Memory organization Extended SFR and data memory area A96L414/A96L416 has 256/768 bytes XRAM and XSFR registers. Extended SFR area has no relation with RAM nor FLASH. This area can be read or written to by using SFR in 8-bit unit.

  • Page 28: Sfr Map

    4. Memory organization A96L414/A96L416 User’s manual SFR map In this section, information of SFR map and map summaries are introduced through Table 3, Table 4, Table 5, and Table 6. 4.5.1 SFR map summary Table 3. SFR Map Summary –...

  • Page 29: Sfr Map

    A96L414/A96L416 User’s manual 4. Memory organization 4.5.3 SFR map Table 5. SFR Map Address Function Symbol @ Reset P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1...
  • Page 30 4. Memory organization A96L414/A96L416 User’s manual Table 5. SFR Map (continued) Address Function Symbol @ Reset Internal RC Trim Register IRCTRM Reserved – – – P1 Direction Register P1IO – – P1 Open-drain Selection Register P1OD – – Pull-up Resistor...
  • Page 31 A96L414/A96L416 User’s manual 4. Memory organization Table 5. SFR Map (continued) Address Function Symbol @ Reset Timer 0 Control High Register T0CRH – – – – Timer 0 A Data Low Register T0ADRL Timer 0 A Data High Register T0ADRH...
  • Page 32 4. Memory organization A96L414/A96L416 User’s manual Table 5. SFR Map (continued) Address Function Symbol @ Reset Pull-up Resistor Selection P2PU – – – – Register Port 2 Function Selection Low P2FSR Register Reserved – – – Reserved – – –...
  • Page 33 A96L414/A96L416 User’s manual 4. Memory organization Table 5. SFR Map (continued) Address Function Symbol @ Reset I2C SCL Low Period Register I2CSCLR I2C SCL High Period Register I2CSCHR B Register I2C Slave Address 1 Register I2CSAR1 Data Flash Sector Address Low DFSADRL –...

  • Page 34: Extended Sfr Map

    4. Memory organization A96L414/A96L416 User’s manual 4.5.4 Extended SFR map Table 6. XSFR Map Address Function Symbol @ Reset 5050H Flash CRC Start Address High FCSARH – – – – – – – Register 5051H Flash CRC End Address High FCEARH –...

  • Page 35: Sfr Map

    A96L414/A96L416 User’s manual 4. Memory organization 4.5.5 SFR map ACC (Accumulator Register): E0H Initial value: 00H Accumulator B (B Register): F0H Initial value: 00H B Register SP (Stack Pointer): 81H Initial value: 07H Stack Pointer DPL (Data Pointer Register Low): 82H...
  • Page 36 4. Memory organization A96L414/A96L416 User’s manual DPH1 (Data Pointer Register High 1): 85H DPH1 Initial value: 00H DPH1 Data Pointer High 1 PSW (Program Status Word Register): D0H Initial value: 00H Carry Flag Auxiliary Carry Flag General Purpose User-Definable Flag...

  • Page 37: I/O Ports

    Ports I/O ports A96L414/A96L416 has three groups of I/O ports, P0, P1 and P2. Each port can be easily configured as an input pin, an output, or an internal pull up and open-drain pin by software. The port configuration pursues to meet various system configurations and design requirements. P0, P1 and P2 have a function generating interrupts in accordance with a change of state of the pin.

  • Page 38: Port Function Selection Register (P0Fsrh, P0Fsrl, P1Fsrh, P1Fsrl, P2Fsr)

    5. Ports A96L414/A96L416 User’s manual 5.2.6 Port function selection register (P0FSRH, P0FSRL, P1FSRH, P1FSRL, P2FSR) Port function selection registers define alternative functions of ports. Please remember that these registers must be set properly for alternative port functions. A reset clears the P0FSRH, P0FSRL, P1FSRH, P1FSRL and P2FSR register to ‘00H’, which makes all pins to normal I/O ports.

  • Page 39: Port P0

    A96L414/A96L416 User’s manual 5. Ports Port P0 5.3.1 Port description of P0 As an 8-bit I/O port, P0 controls the following registers: P0 data register (P0)  P0 direction register (P0IO)  P0 debounce enable register (P0DB)  P0 pull-up resistor selection register (P0PU) ...
  • Page 40 5. Ports A96L414/A96L416 User’s manual P0OD (P0 Open-drain Selection Register): 92H P07OD P06OD P05OD P04OD P03OD P02OD P01OD P00OD Initial value: 00H P0OD[7:0] Configure Open-drain of P0 Port Push-pull output Open-drain output P0DB (P0 Debounce Enable Register): 96H – –...
  • Page 41 A96L414/A96L416 User’s manual 5. Ports P0FSRH (Port 0 Function Selection High Register): 95H – – – – P0FSRH6 P0FSRH4 P0FSRH2 P0FSRH0 – – – – Initial value: 00H P0FSRH6 P07 Function select P0FSRH6 Description I/O Port (EINT3 function possible when input)
  • Page 42 5. Ports A96L414/A96L416 User’s manual P0FSRL (Port 0 Function Selection Low Register): 94H P0FSRL7 P0FSRL6 P0FSRL5 P0FSRL4 P0FSRL3 P0FSRL2 P0FSRL1 P0FSRL0 Initial value: 00H P0FSRL[7:6] P03 Function select P0FSRL7 P0FSRL6 Description I/O Port OP0OUT Function AN3 Function Not used P0FSRL[5:4]...

  • Page 43: Port P1

    A96L414/A96L416 User’s manual 5. Ports Port P1 5.4.1 Port description of P1 As a 6-bit I/O port, P1 controls the following registers: P1 data register (P1)  P1 direction register (P1IO)  P1 pull-up resistor selection register (P1PU)  P1/P2 debounce enable register (P12DB) ...
  • Page 44 5. Ports A96L414/A96L416 User’s manual P1OD (P1 Open-drain Selection Register): 9AH – – P15OD P14OD P13OD P12OD P11OD P10OD – – Initial value: 00H P1OD[5:0] Configure Open-drain of P1 Port Push-pull output Open-drain output P12DB (P1/P2 Debounce Enable Register): 9EH –...
  • Page 45 A96L414/A96L416 User’s manual 5. Ports P1FSRH (Port 1 Function Selection High Register): 9DH – – – – P1FSRH3 P1FSRH2 P1FSRH1 P1FSRH0 – – – – Initial value: 00H P1FSRH[3:2] P15 Function select P1FSRH3 P1FSRH2 Description I/O Port(SS function possible when input)

  • Page 46: Port P2

    5. Ports A96L414/A96L416 User’s manual Port P2 5.5.1 Port description of P2 As a 4-bit I/O port, P2 controls the following registers: P2 data register (P2)  P2 direction register (P2IO)  P2 pull-up resistor selection register (P2PU)  P2 open-drain selection register (P2OD) ...
  • Page 47 A96L414/A96L416 User’s manual 5. Ports P2OD (P2 Open-drain Selection Register): D2H – – – – P23OD P22OD P21OD P20OD – – – – Initial value: 00H P2OD[3:0] Configure Open-drain of P2 Port Push-pull output Open-drain output P2FSR (Port 2 Function Selection Register): D4H...

  • Page 48: Interrupt Controller

    A96L414/A96L416 User’s manual Interrupt controller Up to 16 interrupt sources are available in the A96L414/A96L416. Allowing software control, each interrupt source can be enabled by defining separate enable register bit associated with it. It can also have four levels of priority assigned. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt sources, and is not controllable by software.

  • Page 49: External Interrupt

    A96L414/A96L416 User’s manual 6. Interrupt controller Highest Lowest Interrupt Group 0 (Bit0) Interrupt 0 Interrupt 6 Interrupt 12 Interrupt 18 Highest 1 (Bit1) Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 2 (Bit2) Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20...

  • Page 50: Interrupt Controller Block Diagram

    6. Interrupt controller A96L414/A96L416 User’s manual Interrupt controller block diagram EIPOL0/1 EIFLAG.0 EINT0 FLAG0 Priority High EIFLAG.1 EINT1 FLAG1 EIFLAG.2 EINT2 FLAG2 EIFLAG.3 EINT3 FLAG3 EIFLAG.4 EINT10 FLAG10 EIFLAG.5 EINT11 FLAG11 ADCIFR I2CIFR Reserved Reserved Reserved EIFLAG.6 EINT12 FLAG12 Level 0...

  • Page 51: Interrupt Vector Table

    A96L414/A96L416 User’s manual 6. Interrupt controller In Figure 14, release signal for STOP and IDLE mode can be generated by all interrupt sources which are enabled without reference to priority level. An interrupt request will be delayed while data is written to one of the registers IE, IE1, IE2, IE3, IP, IP1, and PCON.

  • Page 52: Interrupt Sequence

    6. Interrupt controller A96L414/A96L416 User’s manual To execute the maskable interrupts, both EA bit and a corresponding bit of IEx associated with a specific interrupt source must be set to ‘1’. When an interrupt request is received, a particular interrupt request flag is set to ‘1’...

  • Page 53: Figure 15. Interrupt Sequence Flow

    A96L414/A96L416 User’s manual 6. Interrupt controller Figure 15 shows a flow diagram of an ISR process. Figure 15. Interrupt Sequence Flow...

  • Page 54: Effective Timing After Controlling Interrupt Bit

    6. Interrupt controller A96L414/A96L416 User’s manual Effective timing after controlling interrupt bit Case A in Figure 16 shows an effective time of Control Interrupt Enable Register (IE, IE1, IE2, and IE3). Figure 16. Case A: Effective Timing of Interrupt Enable Register Case B in Figure 17 shows an effective time of Interrupt Flag Register.

  • Page 55: Multi Interrupt

    A96L414/A96L416 User’s manual 6. Interrupt controller Multi interrupt If two requests of different priority levels are received simultaneously, the request with higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. However, for special features, multi-interrupt processing can be executed by software.

  • Page 56: Interrupt Enable Accept Timing

    6. Interrupt controller A96L414/A96L416 User’s manual Interrupt enable accept timing Figure 19 implies that some period of time is required to response to the latched interrupt signal. In this figure, 4 machine cycles will be taken for the processes of LCALL and LJMP.

  • Page 57: Saving/ Restore General-Purpose Registers

    A96L414/A96L416 User’s manual 6. Interrupt controller Saving/ restore general-purpose registers Let’s assume there occurs an urgent condition. CPU needs to pause from its current task (Main Task in Figure 21) for some time to execute something else (Interrupt Service Task in Figure 21). After finishing the something else, CPU will return to the current task (Main Task).

  • Page 58: Interrupt Timing

    6. Interrupt controller A96L414/A96L416 User’s manual Interrupt timing As seen in Figure 22 below, an interrupt source is sampled at the last cycle of a command. Upon the sampling, low 8-bit of interrupt vector is decided. M8051W core makes the interrupt acknowledge at the first cycle of a command, executes LCALL instruction to jump interrupt routine at the address referenced by INT_VEC.

  • Page 59: Interrupt Register

    A96L414/A96L416 User’s manual 6. Interrupt controller Interrupt register Interrupt registers are memory space used to control interrupt functions. As shown in Table 10, the interrupt registers consist of Interrupt Enable Registers, Interrupt Priority Registers, External Interrupt Flag Registers, and External Interrupt Polarity Register.

  • Page 60: Register Map

    6. Interrupt controller A96L414/A96L416 User’s manual 6.11.5 Register map Table 10. Interrupt Register Map Name Address Direction Default Description Interrupt Enable Register Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Priority Register Interrupt Priority Register 1...
  • Page 61 A96L414/A96L416 User’s manual 6. Interrupt controller IE1 (Interrupt Enable Register 1): A9H –- – INT11E – –- – INT7E INT6E – – – – – Initial value: 00H INT11E Enable or Disable External Interrupt 12 (EINT12) Disable Enable INT7E Enable or Disable I2C Interrupt...
  • Page 62 6. Interrupt controller A96L414/A96L416 User’s manual IP (Interrupt Priority Register): B8H – – – – Initial value: 00H IP1 (Interrupt Priority Register 1): F8H – – IP15 IP14 IP13 IP12 IP11 IP10 – – Initial value: 00H IP[5:0], IP1[5:0] Select Interrupt Group Priority...
  • Page 63 A96L414/A96L416 User’s manual 6. Interrupt controller EIPOL1 (External Interrupt Polarity 1 Register): A5H –- – POL12 POL11 POL10 – – Initial value: 00H EIPOL1[5:0] External interrupt (EINT10, EINT11 and EINT12) polarity selection POLn[1:0] Description No interrupt at any edge Interrupt on rising edge...

  • Page 64: Block Diagram

    A default system clock is a 1MHz HF INT-RC oscillator and default division rate is four. To stabilize system internally, it is used 1MHz HF INT-RC oscillator on POR. A96L414/A96L416 incorporates three types of oscillators: Calibrated HF Internal RC Oscillator (4MHz) ...

  • Page 65: Register Map

    A96L414/A96L416 User’s manual 7. Clock generator Register map Table 11. Clock Generator Register Map Name Address Direction Default Description SCCR System and Clock Control Register OSCCR Oscillator Control Register IRCTCR Internal RC Trim Control Register IRCTRM Internal RC Trim Register...

  • Page 66: Figure 24. Irctrm Value Vs. Irc Frequency Graph

    7. Clock generator A96L414/A96L416 User’s manual IRCIDR (Internal RC Trim Identification Register): 9FH IRCID7 IRCID6 IRCID5 IRCID4 IRCID3 IRCID2 IRCID1 IRCID0 Initial value: 00H IRCID[7:0] Internal RC Trim Identification. Others No identification value 01000110b Identification value for IRC Trim (These bits are automatically cleared to logic ‘00H’ immediately after one time operation.)
  • Page 67 A96L414/A96L416 User’s manual 7. Clock generator IRCTCR (Internal RC Trim Control Register): 8FH ITCR7 ITCR6 ITCR5 ITCR4 ITCR3 ITCR2 ITCR1 ITCR0 Initial value: 00H ITCR[7:0] Internal RC Trim Control Register. Others No effect 10110011b IRCTRM register is used for IRC frequency.

  • Page 68: Block Diagram

    A96L414/A96L416 User’s manual Basic Interval Timer (BIT) A96L414/A96L416 has a free running 8-bit Basic Interval Timer (BIT). This BIT generates the time base for Watchdog Timer counting, and provides a basic interval timer interrupt (BITIFR). The BIT of A96L414/A96L416 features the followings: During Power On, BIT gives a stable clock generation time ...

  • Page 69: Register Description

    A96L414/A96L416 User’s manual 8. Basic Interval Timer (BIT) Register description BITCNT (Basic Interval Timer Counter Register): 8CH BITCNT7 BITCNT6 BITCNT5 BITCNT4 BITCNT3 BITCNT2 BITCNT1 BITCNT0 Initial value: 00H BITCNT[7:0] BIT Counter BITCR (Basic Interval Timer Control Register): 8BH BITIFR BITCK1 BITCK0 –...

  • Page 70: Block Diagram

    9. Watchdog Timer (WDT) A96L414/A96L416 User’s manual Watchdog Timer (WDT) Watchdog Timer (WDT) is used to rapidly detect the CPU malfunctions such as endless looping caused by noise. In addition, it is used to resume the CPU in a normal state. A watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.

  • Page 71: Wdt Interrupt Timing Waveform

    A96L414/A96L416 User’s manual 9. Watchdog Timer (WDT) WDT interrupt timing waveform Figure 27 shows a timing diagram when a Watchdog Timer generates system reset signal and an interrupt signal. Figure 27. Watchdog Timer Interrupt Timing Waveform Register map Name Address...

  • Page 72: Register Description

    9. Watchdog Timer (WDT) A96L414/A96L416 User’s manual Register description WDTCNT (Watchdog Timer Counter Register: Read Case): 8EH WDTCNT 7 WDTCNT 6 WDTCNT 5 WDTCNT 4 WDTCNT3 WDTCNT 2 WDTCNT 1 WDTCNT 0 Initial value: 00H WDTCNT[7:0] WDT Counter WDTDR (Watchdog Timer Data Register: Write Case): 8EH...

  • Page 73: Table 13. Timer 0/1/2 Operating Modes

    A96L414/A96L416 User’s manual 10. TIMER 0/1/2 TIMER 0/1/2 A 16-bit timer 0/1/2 incorporates a multiplexer and six registers such as timer 0/1/2A data register high/low, timer 0/1/2B data register high/low, and timer 0/1/2 control register high/low (TnADRH, TnADRL, TnBDRH, TnBDRL, TnCRH, TnCRL).

  • Page 74: 16-Bit Timer/ Counter Mode

    10. TIMER 0/1/2 A96L414/A96L416 User’s manual 16-bit timer/ counter mode 16-bit timer/counter mode is selected by control register as shown in Figure 28. This figure shows that a 16-bit timer has a counter and data registers. Counter registers have increasing values by internal or external clock input.

  • Page 75: Figure 29. 16-Bit Timer/ Counter 0/1/2 Interrupt Example

    A96L414/A96L416 User’s manual 10. TIMER 0/1/2 Match with TnADRH/L TnCNTH/L Value Count Pulse Period Up-count TIME Interrupt Period x (n+1) Timer n (TnIFR) Occur Occur Occur Interrupt Interrupt Interrupt Interrupt Figure 29. 16-bit Timer/ Counter 0/1/2 Interrupt Example...

  • Page 76: 16-Bit Capture Mode

    10. TIMER 0/1/2 A96L414/A96L416 User’s manual 16-bit capture mode 16-bit timer 0/1/2 capture mode is set by configuring TnMS[1:0] as ‘01’. It uses an internal/external clock as a clock source. Basically, the 16-bit timer 0/1/2 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when TnCNTH/TnCNTL is equal to TnADRH/TnADRL.

  • Page 77: Figure 31. Input Capture Mode Operation Of Timer 0/1/2

    A96L414/A96L416 User’s manual 10. TIMER 0/1/2 TnBDRH/L Load TnCNTH/L Value Count Pulse Period Up-count TIME Ext. EINT1n PIN Interrupt Request (FLAG1n) Interrupt Interval Period Figure 31. Input Capture Mode Operation of TIMER 0/1/2 FFFF FFFF TnCNTH/L Interrupt Request (TnIFR) Ext. EINT1n PIN...

  • Page 78: 16-Bit Ppg Mode

    10. TIMER 0/1/2 A96L414/A96L416 User’s manual 16-bit PPG mode TIMER 0/1/2 has a PPG (Programmable Pulse Generation) function. In PPG mode, TnO/PWMnO pin outputs up to 16-bit resolution PWM output. For this function, TnO/PWMnO pin must be configured as a PWM output by setting P1FSRL[2] to ‘1’(T0), P1FSRH[0] to ‘1’(T1), P2FSR [0] to ‘1’(T2).

  • Page 79: Figure 34. 16-Bit Ppg Mode Timing Chart Of Timer 0/1/2

    A96L414/A96L416 User’s manual 10. TIMER 0/1/2 Repeat Mode(TnMS = 11b) and "Start High"(TnPOLA = 0b). Clear and Start Set TnEN Timer n clock Counter TnADRH/L Tn Interrupt 1. TnBDRH/L(5) < TnADRH/L PWMnO B Match A Match 2. TnBDRH/L >= TnADRH/L...

  • Page 80: Block Diagram

    10. TIMER 0/1/2 A96L414/A96L416 User’s manual Block diagram 16-bit A Data Register TnADRH/TnADRL A Match Reload TnCC TnEN RLDnEN TnECE TnCK[2:0] INT_ACK Buffer Register A To other block Clear Edge Detector A Match To interrupt TnIFR block fx/1 TnEN Comparator...

  • Page 81: Timer/Counter 0/1/2 Register Description

    A96L414/A96L416 User’s manual 10. TIMER 0/1/2 Timer/counter 0/1/2 register description TnADRH (Timer n A data High Register): B5H/BDH/C5H, Where n = 0, 1, and 2 TnADRH7 TnADRH6 TnADRH5 TnADRH4 TnADRH3 TnADRH2 TnADRH1 TnADRH0 Initial value: FFH TnADRH[7:0] Tn A Data High Byte...
  • Page 82 10. TIMER 0/1/2 A96L414/A96L416 User’s manual TnCRL (Timer n Control Low Register): B2H/BAH/C2H, Where n = 0, 1, and 2 TnCK2 TnCK1 TnCK0 TnIFR RLDnEN TnPOL TnECE TnCNTR Initial value: 00H TnCK[2:0] Select Timer n clock source. fx is main system clock frequency...

  • Page 83: Bit A/D Converter

    A96L414/A96L416 User’s manual 11. 10-bit A/D Converter 10-bit A/D Converter Analog-to-digital (A/D) converter allows conversion of an analog input signal to a corresponding 10-bit digital output. The A/D module has 9 analog inputs, and the output of the multiplexer becomes the input into the converter, which generates a result via successive approximation.

  • Page 84: Block Diagram

    11. 10-bit A/D Converter A96L414/A96L416 User’s manual Block diagram 0.5MHz LDOEN LDO23 1MHz Block ADCCK HFIRC 2MHz (4MHz) Scaler 4MHz Reference REFSEL Voltage STOP (Power Down) STBY CKSEL[1:0] AVREF Sample To OP-Amp block To interrupt 10-bit SAR ADCIFR block Hold...

  • Page 85: Adc Operation

    A96L414/A96L416 User’s manual 11. 10-bit A/D Converter ADC operation In this section, ADC operation is described through figures 39 to 41. As shown in Figure 39, ADC conversion starts after configuring ADC Control High/ Low registers. By checking AFLAG, it is defined whether the conversion is completed or not.

  • Page 86: Figure 40. Adc Operation For Align Bit

    11. 10-bit A/D Converter A96L414/A96L416 User’s manual Align bit set “0” ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCDRH7 ADCDRH6 ADCDRH5 ADCDRH4 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRH[7:0] ADCDRL[7:6] ADCDRL[5:0] bits are “0” Align bit set “1”...

  • Page 87: Register Map

    A96L414/A96L416 User’s manual 11. 10-bit A/D Converter Register map Table 15. 10-bit ADC Register Map Name Address Direction Default Description ADCCRH A/D Converter Control High Register ADCCRL A/D Converter Control Low Register ADCDRH A/D Converter Data High Register ADCDRL A/D Converter Data Low Register...
  • Page 88 11. 10-bit A/D Converter A96L414/A96L416 User’s manual ADCCRH (A/D Converter Control High Register): CBH ADCIFR – – – TRIG ALIGN CKSEL1 CKSEL0 – – – Initial value: 00H When ADC Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ADCIFR ‘0’...
  • Page 89 A96L414/A96L416 User’s manual 11. 10-bit A/D Converter ADCCRL (A/D Converter Control Low Register): CAH STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value: 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable...

  • Page 90: Operational Amplifier

    12. Operational amplifier A96L414/A96L416 User’s manual Operational amplifier A96L414/A96L416 offers two channels of an operational amplifier (OP-Amp). OP-Amp consists of three registers such as OP-AMP control register 0 (AMPCR0), OP-AMP control register 1 (AMPCR1), and Chopper control register (CHPCR). Block diagram...

  • Page 91: Figure 43. Recommend Circuit For Internal Gain

    A96L414/A96L416 User’s manual 12. Operational amplifier AMP0 AMP1 C3, 200N C4, 100N 7.5k 100P C1, 150P C2, 56P 470k Figure 43. Recommend Circuit for Internal Gain. AMP0 AMP1 C3, 200N C4, 100N 7.5k C1, 150P C2, 56P R2 200k R7 620k...

  • Page 92: Register Map

    12. Operational amplifier A96L414/A96L416 User’s manual Register map Table 16. OP Amp Register Map Name Address Direction Default Description CHPCR Chopper Control Register AMPCR0 OP-AMP Control Register 0 AMPCR1 OP-AMP Control Register 1 Register description AMPCR0 (Operational Amplifier Control Register 0): AEH –...
  • Page 93 A96L414/A96L416 User’s manual 12. Operational amplifier AMPCR1 (Operational Amplifier Control Register 1): AFH AMP1EN GAIN12 GAIN11 GAIN10 AMP0EN – GAIN01 GAIN00 – Initial value: 00H AMP1EN Control operation of OP-AMP1 Block, This bit is automatically cleared by A/DC convert signal when the AUTOD1 bit is “1”.

  • Page 94: Usart Uart Mode

    USART USART (Universal Synchronous/Asynchronous Receiver/Transmitter) is a microchip that facilitates communication through a computer’s serial port using RS-232C protocol. A96L414/A96L416 incorporates a USART function block inside. The USART function block consists of USART control register1/2/3/4, USART status register, USART baud-rate generation register and USART data register.

  • Page 95: Uart Block Diagram

    A96L414/A96L416 User’s manual 13. USART UART block diagram Master Control USTMS[1:0] SCLK USTBD (fx: System clock) To interrupt block Baud Rate Generator DBLS WAKEIE RXCIE Clock Sync Logic At Stop mode WAKE Low level detector Clock Recovery Control USTS[2:0] LOOPS...

  • Page 96: Clock Generator

    13. USART A96L414/A96L416 User’s manual Clock generator A clock generation logic generates a base clock for the transmitter and the receiver. The USART supports four modes of clock operation such as normal asynchronous mode, double speed asynchronous mode, master synchronous mode and slave synchronous mode.

  • Page 97: External Clock (Sck)

    A96L414/A96L416 User’s manual 13. USART External clock (SCK) External clocking is used in the synchronous mode of operation. External clock input from the SCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and the receiver.

  • Page 98: Data Format

    13. USART A96L414/A96L416 User’s manual Data format A serial frame is defined as a single character of data bits that consist of synchronization bits (start and stop bits), and optionally a parity bit for error detection. The UART supports 30 combinations of the followings as valid frame formats.

  • Page 99: Parity Bit

    A96L414/A96L416 User’s manual 13. USART Parity bit The parity bit is calculated by doing XOR of all data bits. If odd parity is used, result of the XOR is inverted. The parity bit is located between the MSB and the first stop bit of a serial frame.

  • Page 100: Parity Generator

    13. USART A96L414/A96L416 User’s manual The transmit complete (TXC) flag bit is set when the entire frame in the transmit shift register has been shifted out and there is no more data in the transmit buffer. The TXC flag is automatically cleared when the transmit complete interrupt service routine is executed, or it can be cleared by writing ‘0’...

  • Page 101: Uart Receiver

    A96L414/A96L416 User’s manual 13. USART UART receiver UART receiver is enabled by setting RXE bit in USTCR2 register. When the receiver is enabled, the RXD pin must be set to RXD function for the serial input pin of UART. This can be done by configuring by P2FSR [5:4].

  • Page 102: Parity Checker

    13. USART A96L414/A96L416 User’s manual The data overrun (DOR) flag indicates data loss due to a receive buffer full condition. DOR occurs when the receive buffer is full, and another new data is present in the receive shift register which are to be stored into the receive buffer.

  • Page 103: Figure 50. Data And Parity Bit Sampling

    A96L414/A96L416 User’s manual 13. USART After detecting high to low transition on RXD line, the clock recovery logic uses samples 8, 9, and 10 for normal mode, and samples 4, 5, and 6 for double speed mode to decide if a valid start bit is received.

  • Page 104: Usart Spi Mode

    13. USART A96L414/A96L416 User’s manual USART SPI mode USART can be configured to operate in industrial standard SPI compliant mode. The SPI mode has the following features. Full Duplex, Three-wire synchronous data transfer  Mater and Slave Operation  Supports all four SPI modes of operation (mode 0, 1, 2, and 3) ...

  • Page 105: Spi Block Diagram

    A96L414/A96L416 User’s manual 13. USART SPI block diagram USTBD Control SCLK Baud Rate Generator (fx: System clock) MASTER USTSSEN Edge Detector Control Controller FXCH CPOL CPHA MISO Data Receive Shift Register Rx Control Recovery (RXSR) RXCIE DOR Checker USTDR[0], (Rx)

  • Page 106: Figure 53. Spi Clock Formats When Cpha=0

    13. USART A96L414/A96L416 User’s manual Table 18 introduces four combinations of CPOL and CPHA for SPI mode 0, 1, 2 and 3. Table 18. CPOL Functionality SPI Mode CPOL CPHA Leading Edge Trailing Edge Sample (Rising) Setup (Falling) Setup (Rising)

  • Page 107: Figure 54. Spi Clock Formats When Cpha=1

    A96L414/A96L416 User’s manual 13. USART Figure 54. SPI Clock Formats when CPHA=1 When CPHA=1, the slave begins to drive its MISO output when SS goes active low, but the data is not defined until the first SCK edge. The first SCK edge shifts the first bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave.

  • Page 108: Register Map

    13. USART A96L414/A96L416 User’s manual Register map Table 19. USART Register Map Name Address Direction Default Description USTCR1 USART Control Register 1 USTCR2 USART Control Register 2 USTCR3 USART Control Register 3 USTST USART Status Register USTBD USART Baud Rate Generation Register...
  • Page 109 A96L414/A96L416 User’s manual 13. USART USTCR1 (USART Control Register 1): DAH USTS1 USTS0 USTMS1 USTMS0 USTP1 USTP0 USTS2 CPOL CPHA Initial value: 00H USTMS[1:0] Selects Operation Mode of USART USTMS1 USTMS0 Operation mode Asynchronous Mode (UART) Synchronous Mode Reserved SPI mode...
  • Page 110 13. USART A96L414/A96L416 User’s manual USTCR2 (USART Control Register 2): DBH DRIE TXCIE RXCIE WAKEIE USTEN DBLS Initial value: 00H DRIE Interrupt enable bit for Data Register Interrupt from DRE is inhibited (use polling) When DRE is set, request an interrupt...
  • Page 111 A96L414/A96L416 User’s manual 13. USART USTCR3 (USART Control Register 3): DCH MASTER LOOPS DISSCK USTSSEN FXCH USTSB USTTX8 USTRX8 Initial value: 00H MASTER Selects master or slave in SPI or Synchronous mode operation and controls the direction of SCK pin.
  • Page 112 13. USART A96L414/A96L416 User’s manual USTST (USART Status Register): DDH WAKE USTRST Initial value: 80H The DRE flag indicates if the transmit buffer (USTDR) is ready to receive new data. If DRE is ‘1’, the buffer is empty and ready to be written.

  • Page 113: Inter Integrated Circuit (I2C)

    A96L414/A96L416 User’s manual 14. Inter Integrated Circuit (I2C) Inter Integrated Circuit (I2C) Inter Integrated Circuit (I2C) is one of industrial standard serial communication protocols. It uses two bus lines such as Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL lines are open-drain output, each line needs pull-up resistor.

  • Page 114: I2C Bit Transfer

    14. Inter Integrated Circuit (I2C) A96L414/A96L416 User’s manual I2C bit transfer The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW state of the data line can only change when the clock signal in the SCL line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high.

  • Page 115: Data Transfer

    A96L414/A96L416 User’s manual 14. Inter Integrated Circuit (I2C) Data transfer Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first.

  • Page 116: I2C Acknowledge

    14. Inter Integrated Circuit (I2C) A96L414/A96L416 User’s manual I2C acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.

  • Page 117: Synchronization/ Arbitration

    A96L414/A96L416 User’s manual 14. Inter Integrated Circuit (I2C) Synchronization/ arbitration Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state is reached.

  • Page 118: Operation

    14. Inter Integrated Circuit (I2C) A96L414/A96L416 User’s manual Operation The I2C operates in byte units and is based on interrupts. The interrupts are issued after all bus events except for a transmission of a START condition. Because the I2C is interrupt based, the application software is free to carry on other operations during an I2C byte transfer.
  • Page 119 A96L414/A96L416 User’s manual 14. Inter Integrated Circuit (I2C) To operate as a slave when the MLOST bit in I2CSR is set, the ACKEN bit in I2CCR must be set and the received 7-bit address must equal to the SLA bits in I2CSAR. In this case I2C operates as a slave transmitter or a slave receiver (go to appropriate section).

  • Page 120: Master Receiver

    14. Inter Integrated Circuit (I2C) A96L414/A96L416 User’s manual After doing one of the actions above, clear to “0b” all interrupt source bits in I2CSR to release SCL line. In case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt.
  • Page 121 A96L414/A96L416 User’s manual 14. Inter Integrated Circuit (I2C) I2C (Master) can choose one of the following cases according to the reception of ACK signal from slave. Master receives ACK signal from slave, so continues data transfer because slave can prepare and transmit more data to master. Configure ACKEN bit in I2CCR to decide whether I2C Acknowledges the next data to be received or not.

  • Page 122: Slave Transmitter

    14. Inter Integrated Circuit (I2C) A96L414/A96L416 User’s manual Slave transmitter To operate I2C in slave transmitter, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDHR to make SDA change within one system clock period from the falling edge of SCL.

  • Page 123: Slave Receiver

    A96L414/A96L416 User’s manual 14. Inter Integrated Circuit (I2C) Slave receiver To operate I2C in slave receiver, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDHR to make SDA change within one system clock period from the falling edge of SCL.

  • Page 124: Register Map

    14. Inter Integrated Circuit (I2C) A96L414/A96L416 User’s manual Register map Table 20. I2C Register Map Name Address Direction Default Description I2CCR I2C Control Register I2CSR I2C Status Register I2CSAR0 I2C Slave Address 0 Register I2CSAR1 I2C Slave Address 1 Register...
  • Page 125 A96L414/A96L416 User’s manual 14. Inter Integrated Circuit (I2C) I2CSCHR (I2C SCL High Period Register): EFH I2CSCHR7 I2CSCHR6 I2CSCHR5 I2CSCHR4 I2CSCHR3 I2CSCHR2 I2CSCHR1 I2CSCHR0 Initial value: 3FH I2CDR[7:0] This register defines the high period of SCL in master mode. The transmit data buffer is the destination for data written to the I2CDR register.
  • Page 126 14. Inter Integrated Circuit (I2C) A96L414/A96L416 User’s manual I2CCR (I2C Control Register): E9H ACKEN IMASTER STOPC STARTC IICRST IICEN TXDLYENB IICIE Initial value: 00H IICRST Initialize Internal Registers of I2C. No effect Initialize I2C, auto cleared IICEN Activate I2C Function Block by Supplying...
  • Page 127 A96L414/A96L416 User’s manual 14. Inter Integrated Circuit (I2C) I2CSR (I2C Status Register): EAH MLOST BUSY TMODE RXACK GCALLn TEND STOPD SSEL Initial value: 00H note) GCALL This bit has different meaning depending on whether I2C is master or slave. When I2C is a master, this bit represents whether it received...

  • Page 128: Block Diagram

    15. Constant sink current generator A96L414/A96L416 User’s manual Constant sink current generator Constant sink current generator supplies constant current regardless of variable I voltage ranging from 2.0V to 3.6V. The constant current value is controlled by registers ICSDR0 and ICSDR1, and the sink current ranges from 49mA to 274mA.

  • Page 129: Register Description

    A96L414/A96L416 User’s manual 15. Constant sink current generator Register description ICSCR (Constant Sink Current Control Register): E2H – – – – ICSEN3 ICSEN2 ICSEN1 ICSEN0 – – – – Initial value: 00H ICSEN[3:0] Constant Sink Current Enable bits 0101b Enable for the ICS0 pin and disable for the ICS1 pin...

  • Page 130: Block Diagram

    A96L414/A96L416 User’s manual Flash CRC and Checksum generator Flash CRC (Cyclic Redundancy Check) generator of A96L414/A96L416 generates 16-bit CRC code bits from Flash and a generator polynomial. The CRC code for each input data frame is appended to the frame.

  • Page 131: Operation Procedure And Example Code Of Crc And Checksum

    A96L414/A96L416 User’s manual 16. Flash CRC and Checksum generator Operation procedure and example code of CRC and Checksum The CRC operation procedure in Auto CRC/Checksum mode is introduced in the following list, and Figure 66 shows example program tip: Global interrupt Disable (EA = 0)

  • Page 132: Figure 66. Program Tip For Crc Operation In Auto Crc/ Checksum Mode

    16. Flash CRC and Checksum generator A96L414/A96L416 User’s manual //**** Global interrupt Disable EA = 0; //**** Flash CRC Auto CRC/Checksum Mode and CRC FCCR &= _0101_1111; OSCCR &= _1111_1011; // IRC Enable FCCR &= _1111_0001; // CRC clk = fIRC/1 //**** CRC start address set FCSARH = 0x00;...

  • Page 133: Figure 67. Program Tip For Crc Operation In User Crc/ Checksum Mode

    A96L414/A96L416 User’s manual 16. Flash CRC and Checksum generator The CRC operation procedure in User CRC/Checksum mode is introduced in the following list, and Figure 67 shows example program tip: Select User CRC/Checksum Mode and CRC Clear Flash CRC data register (FCDRH/FCDRL)
  • Page 134 16. Flash CRC and Checksum generator A96L414/A96L416 User’s manual The Checksum operation procedure in Auto CRC/Checksum mode is introduced in the following list, and Figure 68 shows example program tip: Global interrupt Disable (EA = 0) Select Auto CRC/Checksum Mode and Checksum...

  • Page 135: Figure 68. Program Tip For Checksum Operation In Auto Crc/ Checksum Mode

    A96L414/A96L416 User’s manual 16. Flash CRC and Checksum generator //**** Global interrupt Disable EA = 0; //**** Flash CRC Auto CRC/Checksum Mode and Checksum FCCR &= _0111_1111; FCCR |= _0010_0000; // Checksum mode OSCCR &= _1111_1011; // IRC Enable FCCR &= _1111_0001;...

  • Page 136: Register Map

    16. Flash CRC and Checksum generator A96L414/A96L416 User’s manual The Checksum operation procedure in User CRC/Checksum mode is introduced in the following list, and Figure 69 shows example program tip: Select User CRC/Checksum Mode and Checksum Clear Flash CRC data register (FCDRH/FCDRL)

  • Page 137: Register Description

    A96L414/A96L416 User’s manual 16. Flash CRC and Checksum generator Register description FCSARH (Flash CRC Start Address High Register): 5050H – – – – – – – FCSARH0 – – – – – – – Initial value: 00H FCSARH0 Flash CRC Start Address High NOTE: Used only to Auto CRC Mode.
  • Page 138 16. Flash CRC and Checksum generator A96L414/A96L416 User’s manual FCEARL (Flash CRC End Address Low Register): 5055H FCEARL7 FCEARL6 FCEARL5 FCEARL4 FCEARL3 FCEARL2 FCEARL1 FCEARL0 – – – – Initial value: 0FH FCEARL[7:4] Flash CRC End Address Low NOTE: Used only to Auto CRC Mode.
  • Page 139 A96L414/A96L416 User’s manual 16. Flash CRC and Checksum generator FCCR (Flash CRC Control Register): 5056H – CRCMOD CDCL MDSEL CKSEL2 CKSEL1 CKSEL0 CRCRUN – Initial value: 00H CRCMOD Select CRC/Checksum Mode Auto CRC/Checksum Mode User CRC/Checksum Mode CDCL Flash CRC Data Register Clear...

  • Page 140: Power Down Operation

    17. Power down operation A96L414/A96L416 User’s manual Power down operation A96L414/A96L416 offers two power-down modes to minimize power consumption of itself. Programs under the two power saving modes IDLE and STOP, are stopped and power consumption is reduced considerably. Peripheral operation in IDLE/STOP mode Peripheral’s operations during IDLE/STOP mode is introduced in Table 23.

  • Page 141: Idle Mode

    A96L414/A96L416 User’s manual 17. Power down operation IDLE mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt.

  • Page 142: Stop Mode

    17. Power down operation A96L414/A96L416 User’s manual STOP mode The power control register is set to ‘03H’ to enter the STOP Mode. In the stop mode, the selected oscillator, system clock and peripheral clock is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.

  • Page 143: Release Operation Of Stop Mode

    A96L414/A96L416 User’s manual 17. Power down operation Release operation of STOP mode After STOP mode is released, the operation begins according to content of related interrupt register just before STOP mode start (Refer to Figure 72). If the global interrupt Enable Flag (IE.EA) is set to `1`, the STOP mode is released by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine.

  • Page 144: Register Map

    17. Power down operation A96L414/A96L416 User’s manual Register map Table 24. Power-down Operation Register Map Name Address Direction Default Description PCON Power control register Register description PCON (Power Control Register): 87H – – – – – – PCON1 PCON0 –...

  • Page 145: Reset Block Diagram

    Accumulator Stack Pointer (SP) Peripheral clock Control register Refer to peripheral registers. A96L414/A96L416 has 5 types of reset sources as listed in the followings: External RESETB  Power On RESET (POR)  WDT overflow reset (in a case of WDTEN=’1’) ...

  • Page 146: Reset Noise Canceller

    18. Reset A96L414/A96L416 User’s manual Reset noise canceller Figure 74 is a noise canceller timing diagram for noise cancellation of RESET. It has the noise cancellation value of about 2us (@VDD=5V) to the low input of system reset. Figure 74. Reset Noise Canceller Timing Diagram Power on Reset When device power is increasing, POR (Power on Reset) executes a function to reset the device.

  • Page 147: Figure 76. Internal Reset Release Timing On Power-Up

    A96L414/A96L416 User’s manual 18. Reset Figure 76. Internal Reset Release Timing on Power-Up Counting for config read start after POR is released Internal nPOR PAD RESETB “H” LVR_RESETB .. 27 28 BIT (for Config) 00 01 02 03 BIT (for Reset)

  • Page 148: Figure 78. Boot Process Waveform

    18. Reset A96L414/A96L416 User’s manual Relationship between VDD input and internal oscillator is described in Figure 78 and Table 27. Figure 78. Boot Process Waveform Table 27. Boot Process Description Process Description Remark ① No operation ② 1st POR level detection About 1.4V...

  • Page 149: External Resetb Input

    A96L414/A96L416 User’s manual 18. Reset External RESETB input External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized.

  • Page 150: Brown Out Detector Processor

    A96L414/A96L416 User’s manual Brown out detector processor A96L414/A96L416 has an On-chip brown-out detection circuit (BOD) to monitor VDD level during its operation. It compares VDD level to a fixed trigger level which can be selected to be one of 1.60V, 2.20V, 2.40V, and 2.70V by LVRVS[1:0] bits.

  • Page 151: Register Map

    A96L414/A96L416 User’s manual 18. Reset “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB BIT (for Config) ..27 28 00 01 02 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms...

  • Page 152: Register Description

    18. Reset A96L414/A96L416 User’s manual Register description RSTFR (Reset Flag Register): E8H – – – PORF EXTRF WDTRF OCDRF LVRF – – – Initial value: 80H Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit.
  • Page 153 A96L414/A96L416 User’s manual 18. Reset LVRCR (Low Voltage Reset Control Register): D8H – – – – LVRST LVRVS1 LVRVS0 LVREN – – – – Initial value: 00H LVRST LVR Enable when Stop Release Not effect at stop release LVR enable at stop release NOTES: When this bit is ‘1’, the LVREN bit is cleared to ‘0’...
  • Page 154 A96L414/A96L416 User’s manual Flash memory A96L414/A96L416 incorporates Flash memory inside. Program can be written, erased, and overwritten on the Flash memory while it is mounted on a board. The Flash memory can be read by ‘MOVC’ instruction and programmed in OCD, serial ISP mode or user program mode. Followings are features summary of Flash memory.

  • Page 155: Flash Program Rom Structure

    A96L414/A96L416 User’s manual 19. Flash memory Flash program ROM structure 03FFFH Sector 511 03FE0H 03FE0H 03FDFH Sector 510 03FC0H 03FC0H 03FBFH Sector 509 03FA0H 03FA0H 03F9FH Sector 508 Flash Sector Address Address Sector 2 00040H 00040H 0003FH Sector 1 00020H...

  • Page 156: Register Map

    19. Flash memory A96L414/A96L416 User’s manual Register map Table 29. Flash Memory Register Map Name Address Direction Default Description FSADRH Flash Sector Address High Register FSADRM Flash Sector Address Middle Register FSADRL Flash Sector Address Low Register FIDR Flash Identification Register...

  • Page 157: Serial In-System Program (Isp) Mode

    A96L414/A96L416 User’s manual 19. Flash memory FMCR (Flash Mode Control Register): FEH FMBUSY – – – – FMCR2 FMCR1 FMCR0 – – – – Initial value: 00H FMBUSY Flash Mode Busy Bit. This bit will be used for only debugger.

  • Page 158: Protection Area (User Program Mode)

    A96L414/A96L416 User’s manual Protection area (User Program mode) A user can program Flash memory (protection area) of A96L414/A96L416. The protection area cannot be erased or programmed if any protection area is enabled by the configure option 2. If the protection area is disabled (PAEN =’0’), this area can be erased or programmed.

  • Page 159: Erase Mode

    A96L414/A96L416 User’s manual 19. Flash memory Erase mode The sector erase program procedure in user program mode: Page buffer clear (FMCR=0x01). Write ‘0’ to the page buffer. Set Flash sector address register (FSADRH/FSADRM/FSADRL). Set Flash identification register (FIDR). Check User ID to prevent invalid work NOTE Set Flash mode control register (FMCR).

  • Page 160: Figure 85. Program Tip: Sector Erase

    19. Flash memory A96L414/A96L416 User’s manual Figure 85 shows example program tip regarding sector erase. FMCR,#0x01 ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed.

  • Page 161: Write Mode

    A96L414/A96L416 User’s manual 19. Flash memory Write mode The sector Write program procedure in user program mode: Page buffer clear (FMCR=0x01) Write data to page buffer Set Flash sector address register (FSADRH/FSADRM/FSADRL). Set Flash identification register (FIDR). Check the UserID for to prevent the invalid work NOTE1 Set Flash mode control register (FMCR).

  • Page 162: Figure 86. Program Tip: Sector Write

    19. Flash memory A96L414/A96L416 User’s manual Figure 86 shows example program tip regarding sector write. FMCR,#0x01 ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed.
  • Page 163 A96L414/A96L416 User’s manual 19. Flash memory The Byte Write program procedure in user program mode: Page buffer clear (FMCR=0x01) Write data to page buffer Set Flash sector address register (FSADRH/FSADRM/FSADRL). Set Flash identification register (FIDR). Check the UserID for to prevent the invalid work NOTE1 Set Flash mode control register (FMCR).

  • Page 164: Figure 87. Program Tip: Byte Write

    19. Flash memory A96L414/A96L416 User’s manual Figure 87 shows example program tip regarding byte write. FMCR,#0x01 ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed.

  • Page 165: Protection For Invalid Erase/ Write

    A96L414/A96L416 User’s manual 19. Flash memory Protection for invalid erase/ write It needs to be careful when programming Flash erase/write operation in code. In addition, it needs preparations for invalid jump to the Flash erase/write code occurred by malfunction, noise, and power off.

  • Page 166: Figure 89. Example Code Regarding The Recommendation

    19. Flash memory A96L414/A96L416 User’s manual It is important the location where the UserID1/2/3 will be written. The invalid Flash erase/write problem will remain if the UserID1/2/3 is written at the above line of the instruction “MOV FIDR,#10100101B”. Therefore, it is recommended to write the UserID1/2/3 in different routine after returning.

  • Page 167: Figure 90. Overview Of Main

    A96L414/A96L416 User’s manual 19. Flash memory Overview of main CALL Work1 CALL Decide_ErWt CALL Work2 CALL ID_write CALL Work3 CALL Flash_erase CALL Flash_write ID_wire: A,#38H CJNE A,Flash_flag1,No_write_ID A,#75H CJNE A,Flash_flag2,No_write_ID UserID1,#ID_DATA_1 ;Write Uiser ID1 A,#38H CJNE A,Flash_flag1,No_write_ID A,#75H CJNE A,Flash_flag2,No_write_ID UserID2,#ID_DATA_2 ;Write Uiser ID2...

  • Page 168: Protection Flow Of Invalid Erase/ Write

    19. Flash memory A96L414/A96L416 User’s manual 19.8.1 Protection flow of invalid erase/ write Figure 91. Protection Flow of Invalid Erase/ Write...

  • Page 169: Read Mode

    A96L414/A96L416 User’s manual 19. Flash memory Read mode The Reading program procedure in user program mode is shown in the followings: Load received data from Flash memory on MOVC instruction by indirectly addressing mode.  A,#0 DPH,#0x0F DPL,#0xA0 ;Flash memory address...

  • Page 170: Data Flash Memory

    20. Data Flash memory A96L414/A96L416 User’s manual Data Flash memory The A96L414/A96L416 includes Data Flash memory of 256bytes. It can be written, erased, and overwritten. The Data Flash memory can be read by ‘MOVX’ instruction. Data Flash Size: 256bytes ...

  • Page 171: Figure 94. Data Flash Structure

    A96L414/A96L416 User’s manual 20. Data Flash memory Figure 94 describes the relationship between Data Flash page buffer, Data Flash controller, and Data Flash sector addresses. Sector 7 30E0H Sector 6 30C0H Data Flash Sector Address 3080H Sector 3 3060H Sector 2...

  • Page 172: Register Map

    20. Data Flash memory A96L414/A96L416 User’s manual Register map Table 32. Data Flash Register Map Name Address Direction Default Description DFSADRH Data Flash Sector Address High Register DFSADRL Data Flash Sector Address Low Register DFIDR Data Flash Identification Register DFMCR...
  • Page 173 A96L414/A96L416 User’s manual 20. Data Flash memory DFMCR (Data Flash Mode Control Register): F5H – – – – DFMBUSY DFMCR2 DFMCR1 DFMCR0 – – – – Initial value: 00H DFMBUSY Data Flash busy bit. No effect when “1” is written...

  • Page 174: Erase Mode

    20. Data Flash memory A96L414/A96L416 User’s manual Erase mode The sector erase program procedure in user program mode: Page buffer clear (DFMCR=0x01) Write ‘0’ to page buffer Set Data Flash sector address register (DFSADRH/DFSADRL). Set Data Flash identification register (DFIDR).

  • Page 175: Figure 95. Program Tip: Sector Erase

    A96L414/A96L416 User’s manual 20. Data Flash memory EO,#0xF8 ;Set DPTR0 DFMCR,#0x01 ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. A,#0 R0,#DF_SectorSize ;Sector size of Data Flash DPH,#0x70 ;Page Buffer Address is 7000H...

  • Page 176: Write Mode

    20. Data Flash memory A96L414/A96L416 User’s manual Write mode The sector Write program procedure in user program mode Page buffer clear (DFMCR=0x01) Write data to page buffer Set Data Flash sector address register (DFSADRH/DFSADRL). Set Data Flash identification register (DFIDR).

  • Page 177: Figure 96. Program Tip: Sector Write

    A96L414/A96L416 User’s manual 20. Data Flash memory EO,#0xF8 ;Set DPTR0 DFMCR,#0x01 ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. A,#0 R0,#DF_SectorSize ;Sector size of DATA FLASH DPH,#0x70 ;Page Buffer Address is 7000H...
  • Page 178 20. Data Flash memory A96L414/A96L416 User’s manual The Byte Write program procedure in user program mode Page buffer clear (DFMCR=0x01) Write data to page buffer Set Data Flash sector address register (DFSADRH/DFSADRL). Set Data Flash identification register (DFIDR). Check the UserID for to prevent the invalid work NOTE Set Data Flash mode control register (DFMCR).

  • Page 179: Figure 97. Program Tip: Byte Write

    A96L414/A96L416 User’s manual 20. Data Flash memory EO,#0xF8 ;Set DPTR0 DFMCR,#0x01 ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. A,#5 DPH,#0x70 DPL,#0 MOVX @DPTR,A ;Write data to page buffer...

  • Page 180: Read Mode

    20. Data Flash memory A96L414/A96L416 User’s manual Read mode The Reading program procedure in user program mode Load the received data from Data Flash memory on MOVX instruction by indirectly addressing  mode. DPH,#0x30 DPL,#0x10 ;Data Flash memory address MOVX A,@DPTR ;read data from Data Flash memory...

  • Page 181: Electrical Characteristics

    A96L414/A96L416 User’s manual 21. Electrical characteristics Electrical characteristics Absolute maximum ratings Table 33. Absolute Maximum Ratings Parameter Symbol Rating Unit Remark Supply voltage -0.3 ~ +4.0 – Normal voltage -0.3 ~ VDD+0.3 Voltage on any pin with respect to -0.3 ~ VDD+0.3...

  • Page 182: Adc Characteristics

    21. Electrical characteristics A96L414/A96L416 User’s manual ADC characteristics Table 35. ADC Characteristics =-40℃ to +85℃, VDD=2.0V to 3.6V, VSS=0V) Parameter Symbol Conditions Min. Typ. Max. Unit Resolution ― ― ― ― Integral linear error AVREF= 2.2V to 3.6V ― ―...

  • Page 183: Power On Reset

    A96L414/A96L416 User’s manual 21. Electrical characteristics Power on Reset Table 37. Power on Reset Characteristics =-40℃ to +85℃, VDD=2.0V to 3.6V, VSS=0V Parameter Symbol Conditions Min. Typ. Max. Unit RESET release level – – – VDD voltage rising time 0.2V to 2.0V 0.05...

  • Page 184: Operational Amplifier 0/1 Characteristics

    21. Electrical characteristics A96L414/A96L416 User’s manual Operational amplifier 0/1 characteristics Table 39. Operational Amplifier 0/1 Characteristic =-40℃ to +85℃, VDD=2.2V to 3.6V, VSS=0V) Parameter Symbol Conditions Min. Typ. Max. Unit Input offset voltage VDD=3.0V ― ±10 ±100 Input offset current VDD=3.0V, VCM=0V...

  • Page 185: High Frequency Internal Rc Oscillator Characteristics

    A96L414/A96L416 User’s manual 21. Electrical characteristics High frequency internal RC oscillator characteristics Table 40. High Frequency Internal RC Oscillator Characteristics =-40℃ to +85℃, VDD=2.0V to 3.6V, VSS=0V) Parameter Symbol Conditions Min. Typ. Max. Unit Frequency VDD=3.0V ― ― HFIRC Tolerance ―...

  • Page 186: Dc Characteristics

    21. Electrical characteristics A96L414/A96L416 User’s manual DC characteristics Table 43. DC Characteristics =-40℃ to +85℃, VDD=2.0V to 3.6V, VSS=0V, f =4MHz) HFIRC Parameter Symbol Conditions Min. Typ. Max. Unit Input high voltage All input pins except VIH2, 0.8VDD ― RESETB P02–P05...

  • Page 187: Constant Sink Current Electrical Characteristics

    A96L414/A96L416 User’s manual 21. Electrical characteristics Constant sink current electrical characteristics Table 44. Constant Sink Current Electrical Characteristics =-40℃ to +85℃, VDD=2.2V to 3.6V, VSS=0V) Parameter Symbol Conditions Min. Typ. Max. Unit Constant VDD=3V ICSDR[3:0] = 0 sink current =1.5V ICSDR[3:0] = 1 =25℃...

  • Page 188: Ac Characteristics

    21. Electrical characteristics A96L414/A96L416 User’s manual AC characteristics Table 45. AC Characteristics =-40℃ to +85℃, VDD=2.0V to 3.6V) Parameter Symbol Conditions Min. Typ. Max. Unit RESETB input VDD = 3V ― ― low width Interrupt input All interrupt, VDD = 3V ―...

  • Page 189: Spi Characteristics

    A96L414/A96L416 User’s manual 21. Electrical characteristics SPI characteristics Table 46. SPI Characteristics =-40℃ to +85℃, VDD=2.0V to 3.6V) Parameter Symbol Conditions Min. Typ. Max. Unit Output clock pulse Internal SCK source 1000 ― ― period Input clock pulse period External SCK source 1000 ―...

  • Page 190: Uart Timing Characteristics

    21. Electrical characteristics A96L414/A96L416 User’s manual UART timing characteristics Table 47. UART Timing Characteristics =-40℃ to +85℃, VDD=2.0V to 3.6V, fx=1MHz) Parameter Symbol Min. Typ. Max. Unit Serial port clock cycle time 13.92 x 16 18.08 Output data setup to clock rising edge x 13 ―...

  • Page 191: I2C Characteristics

    A96L414/A96L416 User’s manual 21. Electrical characteristics I2C characteristics Table 48. I2C Characteristics =-40℃ to +85℃, VDD=2.0V to 3.6V) Parameter Symbol Standard Mode High-speed Mode Unit Min. Max. Min. Max. Clock frequency Clock high pulse width ― ― SCLH Clock low pulse width ―...

  • Page 192: Data Retention Voltage In Stop Mode

    21. Electrical characteristics A96L414/A96L416 User’s manual Data retention voltage in STOP mode Table 49. Data Retention Voltage in STOP Mode =-40℃ to +85℃, VDD=2.0V to 3.6V) Parameter Symbol Conditions Min. Typ. Max. Unit Data retention supply voltage ― ― DDDR Data retention supply current VDDR = 2.0V...

  • Page 193: Internal Flash Characteristics

    A96L414/A96L416 User’s manual 21. Electrical characteristics Internal Flash characteristics Table 50. Internal Flash Characteristics = +25℃, VDD=2.0V to 3.6V) Parameter Symbol Conditions Min. Typ. Max. Unit Sector write time ― ― Sector erase time ― ― Code write protection time ―...

  • Page 194: Recommended Circuit And Layout

    21. Electrical characteristics A96L414/A96L416 User’s manual Recommended circuit and layout This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the VDD VCC PCB layout. DC Power 0.1uF 0.1uF The MCU power line (VDD and VSS)

  • Page 195: Typical Characteristics

    A96L414/A96L416 User’s manual 21. Electrical characteristics Typical characteristics Figures and tables introduced in this chapter can be used only for design guidance, and are not tested or guaranteed. In graphs or tables some data may exceed specified operating range, and can be only for information.

  • Page 196: Figure 110. Idle (Idd2) Current

    21. Electrical characteristics A96L414/A96L416 User’s manual 140.0 120.0 HFIRC 4MHz -40℃ 100.0 HFIRC 4MHz +25℃ 80.0 HFIRC 4MHz +85℃ HFIRC 2MHz -40℃ 60.0 HFIRC 2MHz +25℃ 40.0 HFIRC 2MHz +85℃ 20.0 2.0V 2.5V 3.0V 3.5V 4.0V Figure 110. IDLE (IDD2) Current 80.0...

  • Page 197: Figure 112. Idle (Idd4) Current

    A96L414/A96L416 User’s manual 21. Electrical characteristics LFIRC 32kHz -40℃ LFIRC 32kHz +25℃ LFIRC 32kHz +85℃ 2.0V 2.5V 3.0V 3.5V 4.0V Figure 112. IDLE (IDD4) Current Stop+LFIRC on -40℃ Stop+LFIRC on +25℃ Stop+LFIRC on +85℃ Stop -40℃ Stop +25℃ Stop +85℃...

  • Page 198: 20 Tssop Package Information

    22. Package information A96L414/A96L416 User’s manual Package information 20 TSSOP package information Figure 114. 20 TSSOP Package Outline...

  • Page 199: 16 Sopn Package Information

    A96L414/A96L416 User’s manual 22. Package information 16 SOPN package information Figure 115. 16 SOPN Package Outline...

  • Page 200: Figure 116. A96L414/ A96L416 Device Numbering Nomenclature

    For available options or further information on the device with an “*” mark, please contact the ABOV sales office. NOTE For more information on any aspect of this device, please contact your nearest distributor or ABOV sales office. Figure 116. A96L414/ A96L416 Device Numbering Nomenclature...

  • Page 201: Development Tools

    ABOV semiconductor does not provide any compiler for A96L414/A96L416. However, since A96L414/A96L416 has Mentor 8051 as its CPU core, you can use all kinds of third party's standard 8051 compiler such as Keil C Compiler. These compilers' output debug information can be integrated with our OCD emulator and debugger.

  • Page 202: Programmer

    A96L414/A96L416 User’s manual Programmer 24.3.1 E-PGM+ E-PGM+ is a single programmer, and allows a user to program on the device directly. Support ABOV / ADAM devices  2~5 times faster than S-PGM+  Main controller : 32-bit MCU @ 72MHz ...

  • Page 203: Gang Programmer

    A96L414/A96L416 User’s manual 24. Development tools 24.3.3 Gang programmer E-Gang4 and E-Gang6 allows a user to program on multiple devices at a time. They run not only in PC controlled mode but also in standalone mode without PC control. USB interface is available and it is easy to connect to the handler.

  • Page 204: Mtp Programming

    A96L414/A96L416 User’s manual MTP programming Program memory of A96L414/A96L416 is an MTP Type. This Flash is accessed through four pins such as DSCL, DSDA, VDD, and VSS in serial data format. Table 55 introduces each pin and corresponding I/O status.

  • Page 205: Circuit Design Guide

    A96L414/A96L416 User’s manual 24. Development tools Circuit design guide When programming Flash memory, the programming tool needs 4 signal lines, DSCL, DSDA, VDD, and VSS. When you design a PCB circuit, you should consider the usage of these 4 signal lines for the on-board programming.

  • Page 206: On-Chip Debug System

    24. Development tools A96L414/A96L416 User’s manual 24.5.1 On-Chip Debug system Detail descriptions for programming via the OCD interface can be found in the following figures. Table 56 introduces features of OCD and Figure 121 shows a block diagram of the OCD interface and the On-chip Debug system.

  • Page 207: Two-Pin External Interface

    A96L414/A96L416 User’s manual 24. Development tools 24.5.2 Two-pin external interface Basic transmission packet 10-bit packet transmission using two-pin interface.  1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge.  Parity is even of ‘1’ for 8-bit data in transmitter.

  • Page 208: Figure 123. Data Transfer On Twin Bus

    24. Development tools A96L414/A96L416 User’s manual Packet transmission timing Figure 123. Data Transfer on Twin Bus Figure 124. Bit Transfer on Serial Bus Figure 125. Start and Stop Condition...

  • Page 209: Figure 126. Acknowledge On Serial Bus

    A96L414/A96L416 User’s manual 24. Development tools Figure 126. Acknowledge on Serial Bus Figure 127. Clock Synchronization during Wait Procedure...

  • Page 210: Connection Of Transmission

    24. Development tools A96L414/A96L416 User’s manual 24.5.3 Connection of transmission Two-pin interface connection uses open-drain (wire-AND bidirectional I/O). Figure 128. Connection of Transmission...

  • Page 211: Configure Option

    A96L414/A96L416 User’s manual Appendix Appendix A. Configure option Register description: configure option control CONFIGURE OPTION 1: ROM Address 001FH – VAPEN – – – RSTS Initial value: 00H Code Read Protection Disable Enable Code Write Protection Disable Enable Vector Area (00H – FFH) Write Protection...
  • Page 212 Appendix A96L414/A96L416 User’s manual CONFIGURE OPTION 2 for 8-kBytes Flash memory: ROM Address 001EH – – – – PAEN PASS2 PASS1 PASS0 Initial value: 00H PAEN Enable Specific Area Write Protection Disable (Erasable by instruction) Enable (Not erasable by instruction)

  • Page 213: Instruction Table

    A96L414/A96L416 User’s manual Appendix B. Instruction table Instructions are either 1, 2 or 3 bytes long as listed in the ‘Bytes’ column in tables shown below.  Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following ...

  • Page 214: Table 58. Instruction Table: Logical

    Appendix A96L414/A96L416 User’s manual Table 58. Instruction Table: Logical Logical Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data...

  • Page 215: Table 59. Instruction Table: Data Transfer

    A96L414/A96L416 User’s manual Appendix Table 59. Instruction Table: Data Transfer Data transfer Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7...

  • Page 216: Table 60. Instruction Table: Boolean

    Appendix A96L414/A96L416 User’s manual Table 60. Instruction Table: Boolean Boolean Mnemonic Description Bytes Cycles Hex code CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit...

  • Page 217: Table 61. Instruction Table: Branching

    A96L414/A96L416 User’s manual Appendix Table 61. Instruction Table: Branching Branching Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...
  • Page 218 Appendix A96L414/A96L416 User’s manual In the above table, an entry such as E8-EF indicates a continuous block of hex opcodes used for 8 different registers, and the register numbers of which are defined by the lowest three bits of the corresponding code.

  • Page 219: Flash Protection For Invalid Erase/ Write

    A96L414/A96L416 User’s manual Appendix C. Flash protection for invalid erase/ write Appendix C shows example code to prevent code or data from being changed by abnormal operations such as noise, unstable power, and malfunction. Figure 129. Flash Protection against Abnormal Operations How to protect the Flash Divide into decision and execution to Erase/Write in Flash.

  • Page 220: Protection Flow Description

    Appendix A96L414/A96L416 User’s manual — Even if invalid Erase/Write occurred, it will be Erase/Write in dummy address in Flash. Use the LVR/LVI  — Unstable or low powers give an adverse effect on MCU. So use the LVR/LVI Protection flow description...
  • Page 221 — Set Flash Sector Address to Dummy Address Sample Source  — Refer to the ABOV website (www.abovsemi.com). — It is created based on the MC97F2664. — Each product should be modified according to the Page Buffer Size and Flash Size...

  • Page 222: Figure 130. Flowchart Of Flash Protection

    Appendix A96L414/A96L416 User’s manual Start Initial ① Set LVR/LVI more than 2.0V Start Main Loop Working ③ Write Flash? Set User_ID1 ② Working Check User_ID1? Set User_ID2 ③ Working Check User_ID2? Set User_ID3 ③ Working Write Flash Set FSADDRH/M/L ④...

  • Page 223: Other Protection By The Configure Options

    A96L414/A96L416 User’s manual Appendix Other protection by the configure options Protection by Configure option  — Set Flash protection by MCU Write Tool (OCD, PGM+, etc.) Vector Area: ▪ 00H~FFH Specific Area (A96L414): ▪ 0.7KBytes (Address 0100H – 03FFH) 1.7KBytes (Address 0100H – 07FFH) 2.7KBytes (Address 0100H –...

  • Page 224: Example Circuit

    Appendix A96L414/A96L416 User’s manual D. Example circuit Figure 131. Example circuit using only IR LED(16 SOPN)
  • Page 225 A96L414/A96L416 User’s manual Appendix Figure 132. Example circuit using IR LED and Blue LED(16 SOPN)
  • Page 226 Appendix A96L414/A96L416 User’s manual Figure 133. Example circuit using only IR LED(20 TSSOP)
  • Page 227 A96L414/A96L416 User’s manual Appendix Figure 134. Example circuit using IR LED and Blue LED (20 TSSOP)

  • Page 228: Revision History

    Revision history A96L414/A96L416 User’s manual Revision history Date Version Description July.3, 2020 1.00 First creation Sep.15. 2020 1.01 Updated example schematics...
  • Page 229 ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders.

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