Abov A96L414 Manuals

Manuals and User Guides for Abov A96L414. We have 1 Abov A96L414 manual available for free PDF download: User Manual

Abov A96L414 User Manual (229 pages)

CMOS Single-chip 8-bit MCU with 10-bit ADC and Operational Amplifier

Brand: Abov | Category: Microcontrollers | Size: 3 MB

Figure 1. A96L414/A96L416 Block Diagram
1
Table of Contents
2
Device Overview
14
Table 1. A96L414/A96L416 Device Features and Peripheral Counts
14
Block Diagram
16
Figure 2. A96L414/A96L416 Block Diagram
16
Pinouts and Pin Descriptions
17
Pinouts
17
Figure 3. A96L414FR/A96L416FR 20 TSSOP Pinouts
17
Figure 4. A96L414AE/A96L416AE 16 SOPN Pinouts
17
Pin Description
18
Table 2. 20 TSSOP Pin Description
18
GPIO Port Structure
21
Figure 5. General Purpose I/O Port Structure
21
External Interrupt I/O Port Structure
22
Figure 6. External Interrupt I/O Port Structure
22
Memory Organization
23
Program Memory
23
Internal Data Memory
24
Figure 7. Program Memory
24
Figure 8. Internal Data Memory Map
25
Figure 9. Lower 128 Bytes Internal RAM
26
Extended SFR and Data Memory Area
27
Data Flash Area
27
Figure 10. Extended SFR (XSFR) Area
27
Figure 11. Data Flash Area
27
SFR Map
28
SFR Map Summary
28
Extended SFR Map Summary
28
Table 3. SFR Map Summary
28
Table 4. XSFR Map Summary
28
SFR Map
29
Table 5. SFR Map
29
Extended SFR Map
34
Table 6. XSFR Map
34
SFR Map
35
I/O Ports
37
Port Registers
37
Data Register (Px)
37
Direction Register (Pxio)
37
Pull-Up Register Selection Register (Pxpu)
37
Open-Drain Selection Register (Pxod)
37
Debounce Enable Register (P0DB, P12DB)
37
Port Function Selection Register (P0FSRH, P0FSRL, P1FSRH, P1FSRL, P2FSR)
38
Register Map
38
Table 7. Port Register Map
38
Port P0
39
Port Description of P0
39
Register Description of P0
39
Port P1
43
Port Description of P1
43
Register Description of P1
43
Port P2
46
Port Description of P2
46
Register Description of P2
46
Interrupt Controller
48
External Interrupt
49
Figure 12. Interrupt Group Priority Level
49
Figure 13. External Interrupt Description
49
Interrupt Controller Block Diagram
50
Figure 14. Interrupt Controller Block Diagram
50
Interrupt Vector Table
51
Table 8. Interrupt Vector Address Table
51
Interrupt Sequence
52
Table 9. LJMP Description and Example Code
52
Figure 15. Interrupt Sequence Flow
53
Effective Timing after Controlling Interrupt Bit
54
Figure 16. Case A: Effective Timing of Interrupt Enable Register
54
Figure 17. Case B: Effective Timing of Interrupt Flag Register
54
Multi Interrupt
55
Figure 18. Effective Timing of Multi Interrupt
55
Interrupt Enable Accept Timing
56
Interrupt Service Routine Address
56
Figure 19. Interrupt Response Timing Diagram
56
Figure 20. Correspondence between Vector Table Address and ISR Entry Address
56
Saving/ Restore General-Purpose Registers
57
Figure 21. Saving and Restore Process Diagram and Example Code
57
Interrupt Timing
58
Figure 22. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
58
Interrupt Register
59
Interrupt Enable Registers (IE, IE1, IE2, IE3)
59
Interrupt Priority Registers (IP, IP1)
59
External Interrupt Flag Register (EIFLAG)
59
External Interrupt Polarity Registers (EIPOL0, EIPOL1)
59
Register Map
60
Interrupt Register Description
60
Table 10. Interrupt Register Map
60
Block Diagram
64
Figure 23. Clock Generator in Block Diagram
64
Register Map
65
Register Description
65
Table 11. Clock Generator Register Map
65
Figure 24. IRCTRM Value Vs. IRC Frequency Graph
66
Block Diagram
68
Register Map
68
Figure 25. Basic Interval Timer in Block Diagram
68
Table 12. Basic Interval Timer Register Map
68
Register Description
69
Block Diagram
70
Figure 26. Watchdog Timer in Block Diagram
70
WDT Interrupt Timing Waveform
71
Register Map
71
Figure 27. Watchdog Timer Interrupt Timing Waveform
71
Register Description
72
Table 13. TIMER 0/1/2 Operating Modes
73
16-Bit Timer/ Counter Mode
74
Figure 28. 16-Bit Timer/ Counter Mode of TIMER 0/1/2
74
Figure 29. 16-Bit Timer/ Counter 0/1/2 Interrupt Example
75
16-Bit Capture Mode
76
Figure 30. 16-Bit Capture Mode of TIMER 0/1/2 (Where N=0, 1, and 2, M=4, 5, and 6)
76
Figure 31. Input Capture Mode Operation of TIMER 0/1/2
77
Figure 32. Express Timer Overflow in Capture Mode
77
16-Bit PPG Mode
78
Figure 33. 16-Bit PPG Mode of TIMER 0/1/2
78
Figure 34. 16-Bit PPG Mode Timing Chart of TIMER 0/1/2
79
Block Diagram
80
Register Map
80
Figure 35. 16-Bit Timer N in Block Diagram (Where N = 0, 1, and 2, M=4, 5, and 6)
80
Table 14. TIMER N Register Map (Where N = 0, 1, and 2)
80
Timer/Counter 0/1/2 Register Description
81
Bit A/D Converter
83
Conversion Timing
83
Block Diagram
84
Figure 36. 10-Bit ADC Block Diagram
84
Figure 37. AD Analog Input Pin with Capacitor
84
Figure 38. LDO23 Pin with Capacitor
84
ADC Operation
85
Figure 39. ADC Operation Flow
85
Figure 40. ADC Operation for Align Bit
86
Figure 41. ADC Timing Chart
86
Register Map
87
Register Description
87
Table 15. 10-Bit ADC Register Map
87
Operational Amplifier
90
Block Diagram
90
Figure 42. OP Amp Block Diagram
90
Figure 43. Recommend Circuit for Internal Gain
91
Figure 44. Recommend Circuit for External Gain
91
Register Map
92
Register Description
92
Table 16. OP Amp Register Map
92
USART UART Mode
94
UART Block Diagram
95
Figure 45. UART Block Diagram
95
Clock Generator
96
Figure 46. Clock Generator Block Diagram
96
Table 17. Equations for Baud Rate Register Settings
96
External Clock (SCK)
97
Synchronous Mode Operation
97
Figure 47. Synchronous Mode SCK Timing (USART)
97
Data Format
98
Figure 48. Frame Format Diagram
98
Parity Bit
99
UART Transmitter
99
Sending Tx Data
99
Transmitter Flag and Interrupt
99
Parity Generator
100
Disabling Transmitter
100
UART Receiver
101
Receiving Rx Data
101
Receiver Flag and Interrupt
101
Parity Checker
102
Disabling Receiver
102
Asynchronous Data Reception
102
Figure 49. Start Bit Sampling
102
Figure 50. Data and Parity Bit Sampling
103
Figure 51. Stop Bit Sampling and Next Stop Bit Sampling
103
USART SPI Mode
104
SPI Block Diagram
105
SPI Clock Formats and Timing
105
Figure 52. SPI Block Diagram
105
Figure 53. SPI Clock Formats When CPHA=0
106
Table 18. CPOL Functionality
106
Figure 54. SPI Clock Formats When CPHA=1
107
Register Map
108
Register Description
108
Table 19. USART Register Map
108
Inter Integrated Circuit (I2C)
113
Block Diagram
113
Figure 55. I2C Block Diagram
113
I2C Bit Transfer
114
Start/ Repeated Start/ Stop
114
Figure 56. Bit Transfer in the I2C-Bus
114
Figure 57. START and STOP Condition
114
Data Transfer
115
Figure 58. Data Transfer on the I2C-Bus
115
I2C Acknowledge
116
Figure 59. Acknowledge on the I2C-Bus
116
Synchronization/ Arbitration
117
Figure 60. Clock Synchronization During Arbitration Procedure
117
Figure 61. Arbitration Procedure of Two Masters
117
Operation
118
Master Transmitter
118
Master Receiver
120
Slave Transmitter
122
Slave Receiver
123
Register Map
124
Register Description
124
Table 20. I2C Register Map
124
Block Diagram
128
Register Map
128
Figure 62. Constant Sink Current Generator Block Diagram (N=0 and 1)
128
Figure 63. Constant Sink Current Generator Pin with Capacitor
128
Table 21. Constant Sink Current Generator Register Map
128
Register Description
129
Block Diagram
130
Figure 64. CRC-16 Polynomial Structure
130
Figure 65. Flash CRC/ Checksum Generator Block Diagram
130
Operation Procedure and Example Code of CRC and Checksum
131
Figure 66. Program Tip for CRC Operation in Auto CRC/ Checksum Mode
132
Figure 67. Program Tip for CRC Operation in User CRC/ Checksum Mode
133
Figure 68. Program Tip for Checksum Operation in Auto CRC/ Checksum Mode
135
Register Map
136
Figure 69. Program Tip for Checksum Operation in User CRC/ Checksum Mode
136
Table 22. Flash Crc/Checksum Generator Register Map
136
Register Description
137
Power down Operation
140
Peripheral Operation in IDLE/STOP Mode
140
Table 23. Peripheral Operation During Power-Down Mode
140
IDLE Mode
141
Figure 70. IDLE Mode Release Timing by External Interrupt
141
STOP Mode
142
Figure 71. STOP Mode Release Timing by External Interrupt
142
Release Operation of STOP Mode
143
Figure 72. STOP Mode Release Flow
143
Register Map
144
Register Description
144
Table 24. Power-Down Operation Register Map
144
Table 25. Example Code with 3 or more NOP Instructions
144
Reset Block Diagram
145
Figure 73. Reset Block Diagram
145
Table 26. Reset Value and the Relevant on Chip Hardware
145
Reset Noise Canceller
146
Power on Reset
146
Figure 74. Reset Noise Canceller Timing Diagram
146
Figure 75. Fast VDD Rising Time
146
Figure 76. Internal Reset Release Timing on Power-Up
147
Figure 77. Configuration Timing When Power-On
147
Figure 78. Boot Process Waveform
148
Table 27. Boot Process Description
148
External RESETB Input
149
Figure 79. Timing Diagram after RESET
149
Figure 80. Oscillator Generating Waveform Example
149
Brown out Detector Processor
150
Block Diagram
150
Internal Reset and BOD Reset in Timing Diagram
150
Figure 81. BOD Block Diagram
150
Figure 82. Internal Reset at Power Fail Situation
150
Register Map
151
Figure 83. Configuration Timing When BOD Reset
151
Table 28. Reset Operation Register Map
151
Register Description
152
Flash Program ROM Structure
155
Figure 84. Flash Program ROM Structure
155
Register Map
156
Register Description
156
Table 29. Flash Memory Register Map
156
Serial In-System Program (ISP) Mode
157
Protection Area (User Program Mode)
158
Table 30. Protection Area Size and Its Relative Information on A96L414
158
Appendix A. Configure
158
Table 31. Protection Area Size and Its Relative Information on A96L416
158
Erase Mode
159
Figure 85. Program Tip: Sector Erase
160
Write Mode
161
Figure 86. Program Tip: Sector Write
162
Figure 87. Program Tip: Byte Write
164
Protection for Invalid Erase/ Write
165
Figure 88. User ID Check Routine for Flash Erase/ Write Code
165
Figure 89. Example Code Regarding the Recommendation
166
Figure 90. Overview of Main
167
Protection Flow of Invalid Erase/ Write
168
Figure 91. Protection Flow of Invalid Erase/ Write
168
Read Mode
169
Code Write Protection Mode
169
Figure 92. Program Tip: Reading
169
Figure 93. Program Tip: Code Write Protection
169
Data Flash Memory
170
Figure 94. Data Flash Structure
171
Register Map
172
Register Description: Data Flash Control and Status
172
Table 32. Data Flash Register Map
172
Erase Mode
174
Figure 95. Program Tip: Sector Erase
175
Write Mode
176
Figure 96. Program Tip: Sector Write
177
Figure 97. Program Tip: Byte Write
179
Read Mode
180
Figure 98. Program Tip: Reading
180
Electrical Characteristics
181
Absolute Maximum Ratings
181
Table 33. Absolute Maximum Ratings
181
Operating Conditions
181
Table 34. Recommended Operating Conditions
181
ADC Characteristics
182
LDO Characteristics
182
Table 35. ADC Characteristics
182
Table 36. LDO Characteristics
182
Power on Reset
183
Low Voltage Reset Characteristics
183
Figure 99. Power-On Reset Timing
183
Table 37. Power on Reset Characteristics
183
Table 38. LVR Characteristics
183
Operational Amplifier 0/1 Characteristics
184
Table 39. Operational Amplifier 0/1 Characteristic
184
High Frequency Internal RC Oscillator Characteristics
185
Low Frequency Internal RC Oscillator Characteristics
185
Internal Watchdog Timer RC Oscillator Characteristics
185
Table 40. High Frequency Internal RC Oscillator Characteristics
185
Table 41. Low Frequency Internal RC Oscillator Characteristics
185
Table 42. Internal WDTRC Oscillator Characteristics
185
DC Characteristics
186
Table 43. DC Characteristics
186
Constant Sink Current Electrical Characteristics
187
Table 44. Constant Sink Current Electrical Characteristics
187
AC Characteristics
188
Figure 100. AC Timing
188
Table 45. AC Characteristics
188
SPI Characteristics
189
Figure 101. SPI Timing
189
Table 46. SPI Characteristics
189
UART Timing Characteristics
190
Figure 102. UART Timing Characteristics
190
Figure 103. Timing Waveform of UART Module
190
Table 47. UART Timing Characteristics
190
I2C Characteristics
191
Figure 104. Timing Waveform of I2C
191
Table 48. I2C Characteristics
191
Data Retention Voltage in STOP Mode
192
Figure 105. STOP Mode Release Timing When Initiated by an Interrupt
192
Figure 106. STOP Mode Release Timing When Initiated by RESETB
192
Table 49. Data Retention Voltage in STOP Mode
192
Internal Flash Characteristics
193
Internal Data Flash Characteristics
193
Input/Output Capacitance Characteristics
193
Table 50. Internal Flash Characteristics
193
Table 51. Internal Data Flash Characteristics
193
Table 52. I/O Capacitance Characteristics
193
Recommended Circuit and Layout
194
Recommended Circuit and Layout with SMPS Power
194
Figure 107. Recommended Circuit and Layout
194
Figure 108. Recommended Circuit and Layout with SMPS Power
194
Typical Characteristics
195
Figure 109. RUN (IDD1) Current
195
Figure 110. IDLE (IDD2) Current
196
Figure 111. RUN (IDD3) Current
196
Figure 112. IDLE (IDD4) Current
197
Figure 113. STOP (IDD5) Current
197
20 TSSOP Package Information
198
Figure 114. 20 TSSOP Package Outline
198
16 SOPN Package Information
199
Figure 115. 16 SOPN Package Outline
199
Figure 116. A96L414/ A96L416 Device Numbering Nomenclature
200
Table 53. A96L414/A96L416 Device Ordering Information
200
Development Tools
201
Compiler
201
OCD (On-Chip Debugger) Emulator and Debugger
201
Figure 117. OCD and Pin Descriptions
201
Programmer
202
OCD Emulator
202
Figure 118. E-PGM+ (Single Writer) and Pin Descriptions
202
Gang Programmer
203
Figure 119. E-Gang4 and E-Gang6 (for Mass Production)
203
Table 54. Specification of E-Gang4 and E-Gang6
203
MTP Programming
204
On-Board Programming
204
Table 55. Pins for MTP Programming
204
Circuit Design Guide
205
Figure 120. PCB Design Guide for On-Board Programming
205
On-Chip Debug System
206
Figure 121. On-Chip Debugging System in Block Diagram
206
Table 56. Features of OCD
206
Two-Pin External Interface
207
Figure 122. 10-Bit Transmission Packet
207
Figure 123. Data Transfer on Twin Bus
208
Figure 124. Bit Transfer on Serial Bus
208
Figure 125. Start and Stop Condition
208
Figure 126. Acknowledge on Serial Bus
209
Figure 127. Clock Synchronization During Wait Procedure
209
Connection of Transmission
210
Figure 128. Connection of Transmission
210
Configure Option
211
Register Description: Configure Option Control
211
Instruction Table
213
Table 57. Instruction Table: Arithmetic
213
Table 58. Instruction Table: Logical
214
Table 59. Instruction Table: Data Transfer
215
Table 60. Instruction Table: Boolean
216
Table 61. Instruction Table: Branching
217
Table 62. Instruction Table: Miscellaneous
217
Table 63. Instruction Table: Additional Instructions
217
Flash Protection for Invalid Erase/ Write
219
How to Protect the Flash
219
Figure 129. Flash Protection against Abnormal Operations
219
Protection Flow Description
220
Figure 130. Flowchart of Flash Protection
222
Other Protection by the Configure Options
223
Example Circuit
224
Figure 131. Example Circuit Using Only IR LED(16 SOPN)
224
Revision History
228

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Abov A96L414 User Manual (229 pages)

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