1. Manuals
  2. Brands
  3. Abov Manuals
  4. Microcontrollers
  5. A96G150
  6. User manual

Abov A96G150 User Manual

16 mhz 8-bit
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
64 Kbyte Flash memory, 2Kbyte EEPROM, 12-bit ADC,

Introduction

This user's manual targets application developers who use A96G150 for their specific needs. It provides
complete information of how to use A96G150 device. Standard functions and blocks including
corresponding register information of A96G150 are introduced in each chapter, while instruction set is
in Appendix.
A96G150 is based on M8051 core and provides standard features of 8051 such as 8-bit ALU, PC, 8-bit
registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit data bus and 2x16-
bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost-effective solutions:
64Kbytes of FLASH, 256bytes of IRAM, 2304bytes of XRAM, 2Kbytes of Data EEPROM, general
purpose I/O, basic interval timer, watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM
output, 16-bit PWM output, watch timer, buzzer driving port, USI, 12-bit A/D converter, on-chip POR,
LVR, LVI, on-chip oscillator and clock circuitry.
As a field proven best seller, A96G150 has been sold more than 3 billion units up to now, and introduces
rich features such as excellent noise immunity, code optimization, cost effectiveness, and so on.

Reference document

A96G150 programming tools and manuals released by ABOV: They are available at ABOV
website, www.abovsemi.com.
SDK-51 User's guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel's 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentor website:
16 MHz 8-bit A96G150 Microcontroller
6 Timers, USART, USI, High Current Port
https://www.mentor.com/products/ip/peripheral/microcontroller/
Global Top Smart MCU Innovator, ABOV Semiconductor
www.abovsemi.com
A96G150
User's Manual
Version 1.00

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the A96G150 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Abov A96G150

Summary of Contents for Abov A96G150

  • Page 1: Introduction

    LVR, LVI, on-chip oscillator and clock circuitry. As a field proven best seller, A96G150 has been sold more than 3 billion units up to now, and introduces rich features such as excellent noise immunity, code optimization, cost effectiveness, and so on.

  • Page 2: Table Of Contents

    Contents Introduction.............................. 1 Reference document ..........................1 Description ........................... 14 Device overview ........................ 14 A96G150 block diagram ....................17 Pinouts and pin description ......................18 Pinouts ..........................18 Pin description ........................19 Port structures ..........................25 Central Processing Unit (CPU) ....................27 Architecture and registers ....................
  • Page 3 A96G150 User's manual Contents Interrupt controller ........................69 External interrupt ....................... 71 Block diagram ........................72 Interrupt vector table ......................73 Interrupt sequence ......................74 Effective timing after controlling interrupt bit ..............75 Multi-interrupt ........................76 Interrupt enable accept timing ................... 77 Interrupt service routine address ..................
  • Page 4 Contents A96G150 User's manual 12.3 Timer 2 ..........................124 12.3.1 16-bit timer/counter mode................... 125 12.3.2 16-bit capture mode .................... 127 12.3.3 16-bit PPG mode ....................129 12.3.4 16-bit timer 2 block diagram ................131 12.3.5 Register map ...................... 131 12.3.6 Register description .................... 132 12.4...
  • Page 5 A96G150 User's manual Contents 15.8.4 USIn UART disabling transmitter ............... 184 15.9 USIn UART receiver ......................185 15.9.1 USIn UART receiver RX data ................185 15.9.2 USIn UART receiver flag and interrupt ............... 185 15.9.3 USIn UART parity checker ................. 186 15.9.4 USIn UART disabling receiver ................
  • Page 6 Contents A96G150 User's manual LCD Driver ..........................246 17.1 LCD Display RAM organization ..................247 17.2 LCD Signal waveform ..................... 248 17.3 Internal resistor bias connection ..................251 17.4 External resistor bias connection ..................252 17.5 LCD Automatic bias control timing .................. 253 17.6...
  • Page 7 A96G150 User's manual Contents 22.3 OCD (On-chip debugger) emulator and debugger ............313 22.3.1 On-chip debug system ..................315 22.3.2 Entering debug mode ..................316 22.3.3 Two-wire communication protocol ..............317 22.4 Programmers ........................321 22.4.1 E-PGM+ ......................321 22.4.2 OCD emulator ..................... 321 22.4.3 Gang programmer ....................
  • Page 8 A96G150 User's manual List of figures Figure 1. A96G150 Block Diagram ....................... 17 Figure 2. A96G150 44LQFP-1010 Pin Assignment ................18 Figure 3. General Purpose I/O Port ...................... 25 Figure 4. External Interrupt I/O Port ...................... 26 Figure 5. M8051EW Architecture ......................27 Figure 6.
  • Page 9 A96G150 User's manual List of figures Figure 49. 16-bit Timer 2 Block Diagram .................... 131 Figure 50. 16-bit Timer/Counter Mode of Timer 3 ................135 Figure 51. 16-bit Timer/Counter Mode Operation Example ..............136 Figure 52. 16-bit Capture Mode of Timer 3 ..................137 Figure 53.
  • Page 10 List of figures A96G150 User's manual Figure 99. Synchronous Mode XCK Timing ..................223 Figure 100. A Frame Format ....................... 224 Figure 101. Start Bit Sampling ......................230 Figure 102. Sampling of Data and Parity Bit ..................231 Figure 103. Stop Bit Sampling and Next Start Bit Sampling ............... 231 Figure 104.
  • Page 11 A96G150 User's manual List of figures Figure 149. Acknowledge on Serial Bus ..................... 320 Figure 150. Clock Synchronization during Wait Procedure ..............320 Figure 151. E-PGM+ (Single Writer) and Pinouts ................321 Figure 152. E-Gang4 and E-Gang6 (for Mass Production) ..............322 Figure 153.
  • Page 12 List of tables A96G150 User's manual List of tables Table 1. A96G150 Device Features and Peripheral Counts ..............14 Table 2. Normal Pin Description ......................19 Table 3. SFR Map Summary ......................... 37 Table 4. XSFR Map Summary ......................38 Table 5.
  • Page 13 A96G150 User's manual List of tables Table 49. Operation Mode ........................299 Table 50. Mode Entrance Method for ISP ................... 303 Table 51. Security Policy using Lock Bits .................... 304 Table 52. Core and Debug Information ....................308 Table 53. Core and Debug Interface by Series ................... 308 Table 54.

  • Page 14: Description

    1. Description A96G150 User's manual Description A96G150 is an advanced CMOS 8-bit microcontroller with 64Kbytes of FLASH. This is a powerful microcontroller which provides a highly flexible and cost-effective solution to many embedded control applications. Device overview In this section, features of A96G150 and peripheral counts are introduced.
  • Page 15 A96G150 User's manual 1. Description Table 1. A96G150 Device Features and Peripheral Counts (continued) Peripherals Description General Purpose I/O (GPIO) Normal I/O: 42 ports  High sink current port: 8 ports P3[7:0]  Reset Power on Reset release level: 1.2 V...
  • Page 16 1. Description A96G150 User's manual Table 1. A96G150 Device Features and Peripheral Counts (continued) Peripherals Description Internal RC oscillator HSI 32MHz ±2.0% (T =-40~ +85°C)  HSI 32MHz ±3.0% (T =-40~ +105°C)  LSI 128kHz ±20% (T = -40~ +85°C) ...

  • Page 17: A96G150 Block Diagram

    A96G150 User's manual 1. Description A96G150 block diagram In this section, A96G150 device with peripherals are described in a block diagram. Flash 64KB XRAM CORE 2304B M8051 IRAM 256B EEPROM General purpose I/O 42 ports normal I/O In-system programming Power control...

  • Page 18: Pinouts And Pin Description

    2. Pinouts and pin description A96G150 User's manual Pinouts and pin description In this chapter, A96G150 device pinouts and pin descriptions are introduced. Pinouts A96G150SN 44-LQFP NOTE: The programmer (E-PGM+, E-Gang4/6) uses P1[3], P1[1] pin as DSCL, DSDA. Figure 2. A96G150 44LQFP-1010 Pin Assignment...

  • Page 19: Pin Description

    A96G150 User's manual 2. Pinouts and pin description Pin description Table 2. Normal Pin Description Pin no. Pin name Description Remark P00* IOUS Port 0 bit 0 Input/output LCD_S16 LCD Segment Signal 16 Output Timer 3 interval output PWM3O Timer 3 PWM output...
  • Page 20 2. Pinouts and pin description A96G150 User's manual Table 2. Normal Pin Description (continued) Pin no. Pin name Description Remark P10* IOUS Port 1 bit 0 Input/output LCD_S0 LCD Segment Signal 0 Output EINT44 External interrupt input ch-44 AN13 ADC input ch-13...
  • Page 21 A96G150 User's manual 2. Pinouts and pin description Table 2. Normal Pin Description (continued) Pin no. Pin name Description Remark P20* IOUS Port 2 bit 0 Input/output LCD_S8 LCD Segment Signal 8 Output RXD0 USART0 data receive SCL0 I2C0 clock signal...
  • Page 22 2. Pinouts and pin description A96G150 User's manual Table 2. Normal Pin Description (continued) Pin no. Pin name Description Remark P30* IOUS Port 3 bit 0 Input /output LED_C0 High sink current ports LCD_C0 LCD Common Signal 0 Output AN12...
  • Page 23 A96G150 User's manual 2. Pinouts and pin description Table 2. Normal Pin Description (continued) Pin no. Pin name Description Remark P40* IOUS Port 4 bit 0 Input/output EINT40 External interrupt input ch-40 ADC input ch-4 VLC0 External LCD Voltage bias 0...
  • Page 24 2. Pinouts and pin description A96G150 User's manual Table 2. Normal Pin Description (continued) Pin no. Pin name Description Remark P50* IOUS Port 5 bit 0 Input/output XIN2 Main Oscillator Input ch-2 SXIN Sub Oscillator Input P51* IOUS Port 5 bit 1 Input/output...

  • Page 25: Port Structures

    A96G150 User's manual 3. Port structures Port structures In this chapter, two port structures are introduced in Figure 3 and Figure 4 regarding general purpose I/O port and external interrupt I/O port respectively. Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V)

  • Page 26: Figure 4. External Interrupt I/O Port

    3. Port structures A96G150 User's manual LevelShift (1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE DIRECTION REGISTER SUB-FUNC DIRECTION R(400Ω) EXTERNAL INTERRUPT POLARITY INTERRUPT ENABLE EDGE FLAG CLEAR PORTx INPUT...

  • Page 27: Central Processing Unit (Cpu)

    A96G150 User's manual 4. Central Processing Unit (CPU) Central Processing Unit (CPU) This is based on Mentor Graphics M8051EW core, and it improves code efficiency and performance. Architecture and registers Figure 5. M8051EW Architecture Two clocks per machine cycle architecture: ...
  • Page 28 4. Central Processing Unit (CPU) A96G150 User's manual Separate program and external data memory interfaces or a single multiplexed interface  ━ Up to 1 Mbyte of external Data Memory, accessible by a choice of interfaces ━ Up to 256 bytes of Internal Data Memory ━...

  • Page 29: Addressing

    A96G150 User's manual 4. Central Processing Unit (CPU) Addressing 6 addressing modes  Direct addressing  ━ In Direct Addressing, the operand is specified by an 8-bit address field. Only internal data and SFRs may be accessed using this mode.

  • Page 30: Instruction Set

    4. Central Processing Unit (CPU) A96G150 User's manual Instruction set If you need an Instruction table, please refer to Appendix. Instructions are either 1, 2 or 3 bytes long as listed in the ‘Bytes’  Each instruction takes either 1, 2 or 4 machine cycles to execute.
  • Page 31 A96G150 User's manual 4. Central Processing Unit (CPU) Subroutine calls and returns :  There are only two sorts of subroutine call, ACALL and LCALL, which are Absolute and Long. Two return instructions are provided, RET and RETI. The latter is for interrupt service routines.

  • Page 32: Memory Organization

    (XRAM) is 2304bytes and internal EEPROM is 2Kbytes. Program memory A 16-bit program counter is capable of addressing up to 64Kbytes, and A96G150 has just 64Kbytes program memory space. Figure 6 shows a map of the lower part of the program memory.

  • Page 33: Figure 6. Program Memory Map

    A96G150 User's manual 5. Memory organization FFFFH 64KB FLASH 7FFFH 32KB FLASH 0000H NOTE: The 64Kbytes includes the Interrupt Vector Region. Figure 6. Program Memory Map...

  • Page 34: Data Memory

    5. Memory organization A96G150 User's manual Data memory Internal data memory space is divided into three blocks, which are generally referred to as lower 128bytes, upper 128bytes, and SFR space. Internal data memory addresses are always one byte wide, which implies an address space of 256bytes. In fact, the addressing modes for the internal data memory can accommodate up to 384bytes by using a simple trick.

  • Page 35: Figure 8. Lower 128Bytes Of Ram

    A96G150 User's manual 5. Memory organization 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58...

  • Page 36: Eeprom Data Memory And External Data Memory

    A96G150 User's manual EEPROM data memory and external data memory A96G150 has 2048bytes of EEPROM, 2304bytes of XRAM and XSFR. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. FFFFH...

  • Page 37: Sfr Map

    A96G150 User's manual 5. Memory organization SFR map 5.4.1 SFR map summary Table 3. SFR Map Summary ― Reserved M8051 compatible 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 0F8H P4FSRL P4FSRH – UBAUD UDATA – P5FSR 0F0H USI1ST1 USI1ST2...

  • Page 38: Table 4. Xsfr Map Summary

    5. Memory organization A96G150 User's manual Table 4. XSFR Map Summary 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 1078H CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ ― ― START_H START_M START_L END_H END_M END_L 1070H ― ― ― CRC_CON CRC_H...

  • Page 39: Sfr Map

    A96G150 User's manual 5. Memory organization 5.4.2 SFR map Table 5. SFR Map Address Function Symbol @Reset P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1...
  • Page 40 5. Memory organization A96G150 User's manual Table 5. SFR Map (continued) Address Function Symbol @Reset P4 Data Register P0 Direction Register P0IO Extended Operation Register – – – – P4 Pull-up Resistor Selection Register P4PU External Interrupt Polarity 0 Low Register...
  • Page 41 A96G150 User's manual 5. Memory organization Table 5. SFR Map (continued) Address Function Symbol @Reset External Interrupt Flag 0 Register EIFLAG0 P3 Direction Register P3IO Timer 2 Control Low Register T2CRL – – Timer 2 Control High Register T2CRH –...
  • Page 42 5. Memory organization A96G150 User's manual Table 5. SFR Map (continued) Address Function Symbol @Reset Accumulator Register USI0 Status Register 1 USI0ST1 – USI0 Status Register 2 USI0ST2 USI0 Baud Rate Generation Register USI0BD USI0 SDA Hold Time Register USI0SHDR...

  • Page 43: Table 6. Xsfr Map

    A96G150 User's manual 5. Memory organization Table 6. XSFR Map Address Function Symbol @Reset 1000H Timer 3 Control High Register T3CRH – – – – 1001H Timer 3 Control Low Register T3CRL – 1002H Timer 3 A Data High Register...
  • Page 44 5. Memory organization A96G150 User's manual Table 6. XSFR Map (continued) Address Function Symbol @Reset 1048H LCD Driver Control Register LCDCR 1049H LCD Automatic Bias and Contrast Control LCDBCCR – – High Register 104AH LCD Automatic Bias and Contrast Control LCDBCCR –...
  • Page 45 A96G150 User's manual 5. Memory organization Table 6. XSFR Map (continued) Address Function Symbol @Reset 1070H CRC Control Register CRC_CON 1072H CRC High Register CRC_H 1073H CRC Low Register CRC_L 1074H CRC Monitor High Register CRC_MNT_H 1075H CRC Monitor Low Register...

  • Page 46: Compiler Compatible Sfr

    5. Memory organization A96G150 User's manual 5.4.3 Compiler compatible SFR ACC (Accumulator Register): E0H Initial value: 00H Accumulator B (B Register): F0H Initial value: 00H B Register SP (Stack Pointer): 81H Initial value: 07H Stack Pointer DPL (Data Pointer Register Low): 82H...
  • Page 47 A96G150 User's manual 5. Memory organization DPH1 (Data Pointer Register High 1): 85H DPH1 Initial value: 00H DPH1 Data Pointer High 1 PSW (Program Status Word Register): D0H Initial value: 00H Carry Flag Auxiliary Carry Flag General Purpose User-Definable Flag...

  • Page 48: O Ports

    A96G150 User's manual I/O ports A96G150 has ten groups of I/O ports (P0 ~ P5). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements.

  • Page 49: Register Map

    A96G150 User's manual 6. I/O ports 6.1.7 Register map Table 7. Port Register Map Name Address Direction Default Description P0 Data Register P0IO P0 Direction Register P0PU P0 Pull-up Resistor Selection Register P0OD P0 Open-drain Selection Register P0DB P0 De-bounce Enable Register...

  • Page 50: P0 Port

    6. I/O ports A96G150 User's manual P0 port 6.2.1 P0 port description P0 is an 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register (P0OD).
  • Page 51 A96G150 User's manual 6. I/O ports P0DB (P0 De-bounce Enable Register): DEH DBCLK1 DBCLK0 P07DB P06DB P05DB P04DB Initial value: 00H DBCLK[1:0] Configure De-bounce Clock of Port DBCLK1 DBCLK0 Description fx/1 fx/4 fx/4096 LSIRC (128KHz) P07DB Configure De-bounce of P07 Port...
  • Page 52 6. I/O ports A96G150 User's manual P0FSRH (Port 0 Function Selection High Register): D3H P0FSRH7 P0FSRH6 P0FSRH5 P0FSRH4 P0FSRH3 P0FSRH2 P0FSRH1 P0FSRH0 Initial value: 00H P0FSRH[7:6] P07 Function Select P0FSRH7 P0FSRH6 Description I/O Port (EINT3 function possible when input) XIN1 Function...
  • Page 53 A96G150 User's manual 6. I/O ports P0FSRL (Port 0 Function Selection Low Register): D2H P0FSRL7 P0FSRL6 P0FSRL5 P0FSRL4 P0FSRL3 P0FSRL2 P0FSRL1 P0FSRL0 Initial value: 00H P0FSRL[7:6] P03 Function Select P0FSRL7 P0FSRL6 Description I/O Port reserved T0O/PWM0O Function reserved P0FSRL[5:4] P02 Function Select...

  • Page 54: P1 Port

    6. I/O ports A96G150 User's manual P1 port 6.3.1 P1 port description P1 is an 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P14DB), P1 pull-up resistor selection register (P1PU), andP1 open-drain selection register (P1OD).
  • Page 55 A96G150 User's manual 6. I/O ports P14DB (P1/P4 De-bounce Enable Register): DFH P43DB P42DB P41DB P40DB P13DB P12DB P11DB P10DB Initial value: 00H P43DB Configure De-bounce of P43 Port Disable Enable P42DB Configure De-bounce of P42 Port Disable Enable P41DB...
  • Page 56 6. I/O ports A96G150 User's manual P1FSRH (Port 1 Function Selection High Register): D5H P1FSRH7 P1FSRH6 P1FSRH5 P1FSRH4 P1FSRH3 P1FSRH2 P1FSRH1 P1FSRH0 Initial value: 00H P1FSRH[7:6] P17 Function Select P1FSRH7 P1FSRH6 Description I/O Port LCD_S7 Function reserved SCK0 Function P1FSRH[5:4]...
  • Page 57 A96G150 User's manual 6. I/O ports P1FSRL (Port 1 Function Selection Low Register): D4H P1FSRL7 P1FSRL6 P1FSRL5 P1FSRL4 P1FSRL3 P1FSRL2 P1FSRL1 P1FSRL0 Initial value: 00H P1FSRL[7:6] P13 Function Select P1FSRL7 P1FSRL6 Description I/O Port (EINT47 function possible when input) LCD_S3 Function...

  • Page 58: P2 Port

    6. I/O ports A96G150 User's manual P2 port 6.4.1 P2 port description P2 is an 8-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU) andP2 open-drain selection register (P2OD). Refer to the port function selection registers for the P2 function selection.
  • Page 59 A96G150 User's manual 6. I/O ports P2FSRH (Port 2 Function Selection High Register): D7H P2FSRH7 P2FSRH6 P2FSRH5 P2FSRH4 P2FSRH3 P2FSRH2 P2FSRH1 P2FSRH0 Initial value: 00H P2FSRH[7:6] P27 Function Select P2FSRH7 P2FSRH6 Description I/O Port LCD_S15 Function T4O/PWM4O Function reserved P2FSRH[5:4]...
  • Page 60 6. I/O ports A96G150 User's manual P2FSRL (Port 2 Function Selection Low Register): D6H P2FSRL7 P2FSRL6 P2FSRL5 P2FSRL4 P2FSRL3 P2FSRL2 P2FSRL1 P2FSRL0 Initial value: 00H P2FSRL[7:6] P23 Function Select P2FSRL7 P2FSRL6 Description I/O Port LCD_S11 Function reserved TXD1/SDA1/MOSI1 Function P2FSRL[5:4]...

  • Page 61: P3 Port

    A96G150 User's manual 6. I/O ports P3 port 6.5.1 P3 port description P3 is an 8-bit I/O port. P3 control registers consist of P3 data register (P3), P3 direction register (P3IO) and P3 pull-up resistor selection register (P3PU). Refer to the port function selection registers for the P3 function selection.
  • Page 62 6. I/O ports A96G150 User's manual P3FSRH (Port 3 Function Selection High Register): EFH P3FSRH7 P3FSRH6 P3FSRH5 P3FSRH4 P3FSRH3 P3FSRH2 P3FSRH1 P3FSRH0 Initial value: 00H P3FSRH[7:6] P37 Function Select P3FSRH7 P3FSRH6 Description I/O Port LCD_C7/LCD_S20 Function AN5 Function LED_C7 Function...
  • Page 63 A96G150 User's manual 6. I/O ports P3FSRL (Port 3 Function Selection Low Register): EEH P3FSRL7 P3FSRL6 P3FSRL5 P3FSRL4 P3FSRL3 P3FSRL2 P3FSRL1 P3FSRL0 Initial value: 00H P3FSRL[7:6] P33 Function Select P3FSRL7 P3FSRL6 Description I/O Port LCD_C3 Function AN9 Function LED_C3 Function...

  • Page 64: P4 Port

    6. I/O ports A96G150 User's manual P4 port 6.6.1 P4 port description P4 is a 6-bit I/O port. P4 control registers consist of P4 data register (P4), P4 direction register (P4IO), P4 pull-up resistor selection register (P4PU) andP4 open-drain selection register (P4OD). Refer to the port function selection registers for the P4 function selection.
  • Page 65 A96G150 User's manual 6. I/O ports P4FSRH (Port 4 Function Selection High Register): FAH P4FSRH3 P4FSRH2 P4FSRH1 P4FSRH0 Initial value: 00H P4FSRH[3:2] P45 Function Select P4FSRH3 P4FSRH2 Description I/O Port LCD_S19 Function T3O/PWM3O Function RXD2/MISO2 Function P4FSRH[1:0] P44 Function Select...
  • Page 66 6. I/O ports A96G150 User's manual P4FSRL (Port 4 Function Selection Low Register): F9H P4FSRL7 P4FSRL6 P4FSRL5 P4FSRL4 P4FSRL3 P4FSRL2 P4FSRL1 P4FSRL0 Initial value: 00H P4FSRL[7:6] P43 Function Select P4FSRL7 P4FSRL6 Description I/O Port (EINT43 function possible when input) VLC3 Function...

  • Page 67: P5 Port

    A96G150 User's manual 6. I/O ports P5 port 6.7.1 P5 port description P5 is a 4-bit I/O port. P5 control registers consist of P5 data register (P5), P5 direction register (P5IO) and P5 pull-up resistor selection register (P5PU). Refer to the port function selection registers for the P5 function selection.
  • Page 68 6. I/O ports A96G150 User's manual P5FSR (Port 5 Function Selection Register): FFH P5FSR7 P5FSR6 P5FSR5 P5FSR4 P5FSR3 P5FSR2 P5FSR1 P5FSR0 Initial value: 00H P5FSR[7:6] P53 Function Select P5FSR7 P5FSR6 Description I/O Port reserved reserved BUZ0 Function P5FSR[5:4] P52 Function Select...

  • Page 69: Interrupt Controller

    The EA bit is always cleared to ‘0’ jumping to an interrupt service vector and set to ‘1’ executing the [RETI] instruction. The A96G150 supports a four-level priority scheme. Each maskable interrupt is individually assigned to one of four...

  • Page 70: Figure 10. Interrupt Group Priority Level

    7. Interrupt controller A96G150 User's manual Default interrupt mode is level-trigger mode basically, but if needed, it is possible to change to edge- trigger mode. Figure 10 shows the Interrupt Group Priority Level that is available for sharing interrupt priority. Priority of a group is set by two bits of interrupt priority registers (one bit from IP, another one from IP1).

  • Page 71: External Interrupt

    A96G150 User's manual 7. Interrupt controller External interrupt External interrupts on INT0, INT1, INT5, INT6 and INT11 pins receive various interrupt requests depending on the external interrupt polarity 0 high/low register (EIPOL0H/L) and external interrupt polarity 1 register (EIPOL1) as shown in Figure 11.

  • Page 72: Block Diagram

    7. Interrupt controller A96G150 User's manual Block diagram EIPOL1 EI FLAG1.1 EINT1 FLAG1 EI FLAG1.2 EINT2 Priority High FLAG2 I2C1IFR USI1 I2C USI1 Rx USI1 Tx EIPOL0H/L EI FLAG0.0 EINT40 FLAG40 EI FLAG0.1 EINT41 FLAG41 EI FLAG0.2 EINT42 FLAG42 EI FLAG0.3...

  • Page 73: Interrupt Vector Table

    7. Interrupt controller Interrupt vector table Interrupt controller of A96G150 supports 24 interrupt sources as shown in Table 8. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.

  • Page 74: Interrupt Sequence

    7. Interrupt controller A96G150 User's manual Interrupt sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack.

  • Page 75: Effective Timing After Controlling Interrupt Bit

    A96G150 User's manual 7. Interrupt controller Effective timing after controlling interrupt bit Case A in Figure 14 shows the effective time after controlling Interrupt Enable Registers (IE, IE1, IE2, and IE3). Interrupt Enable Register command After executing IE set/clear, enable register is effective.

  • Page 76: Multi-Interrupt

    7. Interrupt controller A96G150 User's manual Multi-interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. However, for special features, multi-interrupt processing can be executed by software.

  • Page 77: Interrupt Enable Accept Timing

    A96G150 User's manual 7. Interrupt controller Interrupt enable accept timing System Max. 4 Machine Cycle 4 Machine Cycle Clock Interrupt goes Interrupt Interrupt Processing active latched Interrupt Routine : LCALL & LJMP Figure 17. Interrupt Response Timing Diagram...

  • Page 78: Interrupt Service Routine Address

    7. Interrupt controller A96G150 User's manual Interrupt service routine address Basic Interval Timer Basic Interval Timer Service Routine Address Vector Table Address 00B3H 0125H 00B4H 0126H 00B5H Figure 18. Correspondence between Vector Table Address and the Entry Address of ISR...

  • Page 79: Saving/Restore General Purpose Registers

    A96G150 User's manual 7. Interrupt controller Saving/restore general purpose registers Figure 19. Saving/Restore Process Diagram and Sample Source...

  • Page 80: Interrupt Timing

    7. Interrupt controller A96G150 User's manual 7.10 Interrupt timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-bit interrupt Vector INT_VEC PROGA NOTE: Variable x and n of a command cycle CLPx imply the followings: ...

  • Page 81: Interrupt Register Overview

    A96G150 User's manual 7. Interrupt controller 7.11 Interrupt register overview 7.11.1 Interrupt Enable register (IE, IE1, IE2, and IE3) Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control bits. Total 24 peripherals are able to control interrupt.

  • Page 82: Register Map

    7. Interrupt controller A96G150 User's manual 7.11.5 Register map Table 9. Interrupt Register Map Name Address Direction Default Description Interrupt Enable Register Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt PriorityRegister Interrupt PriorityRegister 1 EIFLAG0...

  • Page 83: Interrupt Register Description

    A96G150 User's manual 7. Interrupt controller 7.11.6 Interrupt register description IE (Interrupt Enable Register): A8H – INT5E INT4E INT3E INT2E INT1E INT0E – Initial value: 00H Enable or Disable All Interrupt bits All Interrupt disable All Interrupt enable INT5E Enable or Disable External Interrupt 40 ~ 47 (EINT40 ~ EINT47)
  • Page 84 7. Interrupt controller A96G150 User's manual IE1 (Interrupt Enable Register 1): A9H – – INT11E INT10E INT9E INT8E INT7E INT6E – – Initial value: 00H INT11E Enable or Disable External Interrupt 3 (EINT3) Disable Enable INT10E Enable or Disable USI0Tx Interrupt...
  • Page 85 A96G150 User's manual 7. Interrupt controller IE2 (Interrupt Enable Register 2): AAH –- – INT17E INT16E INT15E INT14E INT13E INT12E – – Initial value: 00H INT17E Enable or Disable Timer 4/5 Match Interrupt Disable Enable INT16E Enable or Disable Timer 3 Match Interrupt...
  • Page 86 7. Interrupt controller A96G150 User's manual IE3 (Interrupt Enable Register 3): ABH – – INT23E INT22E INT21E INT20E INT19E INT18E – – Initial value: 00H INT23E Enable or Disable LVI Interrupt Disable Enable INT22E Enable or Disable BIT Interrupt Disable...
  • Page 87 A96G150 User's manual 7. Interrupt controller EIFLAG0 (External Interrupt Flag0 Register): C0H FLAG47 FLAG46 FLAG45 FLAG44 FLAG43 FLAG42 FLAG41 FLAG40 Initial value: 00H When an External Interrupt 40-47 is occurred, the flag becomes ‘1’. The EIFLAG0[7:0] flag is cleared only by writing ‘0’ to the bit. So, the flag should be cleared by software.
  • Page 88 7. Interrupt controller A96G150 User's manual EIFLAG1 (External Interrupt Flag 1 Register): A6H – – T0OVIFR T0IFR FLAG3 FLAG2 FLAG1 FLAG0 – – Initial value: 00H When T0 overflow interrupt occurs, this bit becomes ‘1’. For clearing bit, T0OVIFR write ‘0’ to this bit or automatically clear by INT_ACK signal. Writing “1”...

  • Page 89: Clock Generator

    A96G150 User's manual 8. Clock generator Clock generator As shown in Figure 21, a clock generator produces basic clock pulses which provide a system clock for CPU and peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock can operate easily by attaching a crystal between the XIN1/XIN2/SXIN and XOUT1/XOUT2/SXOUT pin, respectively.

  • Page 90: Clock Generator Block Diagram

    8. Clock generator A96G150 User's manual Clock generator block diagram In this section, a clock generator of A96G150 is described in a block diagram. XIOSE L XIN1 XOUT1 Main OSC XIN2 XOUT2 IRCS[2:0] STOP Mode System XCLKE SCLK Clock Gen.

  • Page 91: Register Map

    A96G150 User's manual 8. Clock generator Register map Table 10. Clock Generator Register Map Name Address Direction Default Description SCCR System and Clock Control Register OSCCR Oscillator Control Register XTFLSR 1038H Main Crystal OSC Filter Selection Register...

  • Page 92: Register Description

    8. Clock generator A96G150 User's manual Register description SCCR (System and Clock Control Register): 8AH – – – – – – SCLK1 SCLK0 – – – – – – Initial value: 00H SCLK [1:0] System Clock Selection Bit SCLK1 SCLK0 Description...
  • Page 93 A96G150 User's manual 8. Clock generator XTFLSR (Main Crystal OSC Filter Selection Register): 1038H NFSEL1 NFSEL0 MX_FIL_DIS MX_ISEL1 MX_ISEL0 SUB_FIL_DIS SUB_ISEL1 SUB_ISEL0 Initial value: 00H NFSEL[1:0] Noise Filter Selective Option NFSEL1 NFSEL0 Description 18ns (Default, 12MHz) 22ns (12MHz) 26ns (8MHz)

  • Page 94: Basic Interval Timer (Bit)

    A96G150 User's manual Basic Interval Timer (BIT) A96G150 has a free running 8-bit Basic Interval Timer (BIT). BIT generates the time base for watchdog timer counting, and provides a basic interval timer interrupt (BITIFR). BIT of A96G150 features the followings: During Power On, BIT gives a stable clock generation time ...

  • Page 95: Bit Register Map

    A96G150 User's manual 9. Basic Interval Timer (BIT) BIT register map Table 11. Basic Interval Timer Register Map Name Address Direction Default Description BITCNT Basic Interval Timer Counter Register BITCR Basic Interval Timer Control Register...

  • Page 96: Bit Register Description

    9. Basic Interval Timer (BIT) A96G150 User's manual BIT register description BITCNT (Basic Interval Timer Counter Register): 8CH BITCNT7 BITCNT6 BITCNT5 BITCNT4 BITCNT3 BITCNT2 BITCNT1 BITCNT0 Initial value: 00H BITCNT[7:0] BIT Counter BITCR (Basic Interval Timer Control Register): 8BH BITIFR...

  • Page 97: Watchdog Timer (Wdt)

    A96G150 User's manual 10. Watchdog Timer (WDT) Watchdog Timer (WDT) Watchdog timer (WDT) rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. Watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.

  • Page 98: Wdt Block Diagram

    10. Watchdog Timer (WDT) A96G150 User's manual 10.2 WDT block diagram BIT Overflow Watchdog Timer Counter Register Clear To Reset BIT Overflow/8 WDTCNT Circuit WDTEN WDTCK Clear WDTIFR INT_ACK BIT Overflow comparator BIT Overflow/8 WDTIF WDTDR Watchdog Timer Data Register...

  • Page 99: Register Map

    A96G150 User's manual 10. Watchdog Timer (WDT) 10.3 Register map Table 12. Watchdog Timer Register Map Name Address Direction Default Description WDTCNT Watch Dog Timer Counter Register WDTDR Watch Dog Timer Data Register WDTCR Watch Dog Timer Control Register...

  • Page 100: Register Description

    10. Watchdog Timer (WDT) A96G150 User's manual 10.4 Register description WDTCNT (Watch Dog Timer Counter Register: Read Case): 8EH WDTCNT 7 WDTCNT 6 WDTCNT 5 WDTCNT 4 WDTCNT3 WDTCNT 2 WDTCNT 1 WDTCNT 0 Initial value: 00H WDTCNT[7:0] WDT Counter...

  • Page 101: Watch Timer (Wt)

    7-bit counter in order to increase resolution. In WTDR, it can control WT clear and set interval value at write time, and it can read 7-bit WT counter value at read time. 11.1 WT block diagram In this section, watch timer of A96G150 is described in a block diagram. S UB Match Clear...

  • Page 102: Register Map

    11. Watch Timer (WT) A96G150 User's manual 11.2 Register map Table 13. Watch Timer Register Map Name Address Direction Default Description WTCNT Watch Timer Counter Register WTDR Watch Timer Data Register WTCR Watch Timer Control Register...

  • Page 103: Watch Timer Register Description

    A96G150 User's manual 11. Watch Timer (WT) 11.3 Watch Timer register description WTCNT (Watch Timer Counter Register: Read Case): 89H – WTCNT 6 WTCNT 5 WTCNT 4 WTCNT 3 WTCNT 2 WTCNT 1 WTCNT0 – Initial value: 00H WTCNT[6:0] WT Counter...
  • Page 104 11. Watch Timer (WT) A96G150 User's manual WTCR (Watch Timer Control Register): 96H – – WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 – – Initial value: 00H WTEN Control Watch Timer Disable Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’...

  • Page 105: Timer 0/1/2/3/4/5

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 Timer 0/1/2/3/4/5 12.1 Timer 0 An 8-bit timer 0 consists of a multiplexer, a timer 0 counter register, a timer 0 data register, a timer 0 capture data register and a timer 0 control register (T0CNT, T0DR, T0CDR, T0CR).

  • Page 106: Figure 26. 8-Bit Timer/Counter Mode For Timer 0

    12. Timer 0/1/2/3/4/5 A96G150 User's manual External clock (EC0) counts up the timer at the rising edge. If the EC0 is selected as a clock source by T0CK[2:0], EC0 port should be set as an input port by configuring P52IO bit.

  • Page 107: 8-Bit Pwm Mode

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.1.2 8-bit PWM mode Timer 0 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T0O/PWM0O pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting the T0O/PWM0O function by P0FSRL[7:6] bits.

  • Page 108: Figure 29. Pwm Output Waveforms In Pwm Mode For Timer 0

    12. Timer 0/1/2/3/4/5 A96G150 User's manual PWM Mode(T0MS = 01b) Set T0EN Timer 0 clock T0CNT T0DR T0 Overflow Interrupt 1. T0DR = 4AH T0PWM T0 Match Interrupt 2. T0DR = 00H T0PWM T0 Match Interrupt 3. T0DR = FFH...

  • Page 109: 8-Bit Capture Mode

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.1.3 8-bit capture mode Timer 0 capture mode is set by configuring T0MS[1:0] as ‘1x’. Clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode has, and the interrupt occurs when T0CNT equals to T0DR.

  • Page 110: Figure 31. Input Capture Mode Operation For Timer 0

    12. Timer 0/1/2/3/4/5 A96G150 User's manual T0CDR Load T0CNT Value Count Pulse Period Up-count TIME Ext. EINT1 PIN Interrupt Request (FLAG1) Interrupt Interval Period Figure 31. Input Capture Mode Operation for Timer 0 T0CNT Interrupt Request (T0IFR) Ext. EINT1 PIN...

  • Page 111: Timer 0 Block Diagram

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.1.4 Timer 0 block diagram INT_ACK Clear To interrupt T0OVIFR block fx/2 fx/4 8-bit Timer 0 Counter Match signal fx/8 Clear INT_ACK T0CNT (8Bit) fx/32 T0CC Clear fx/128 Clear fx/512 Match To interrupt T0EN...

  • Page 112: Register Description

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.1.6 Register description T0CNT (Timer 0 Counter Register): B3H T0CNT7 T0CNT6 T0CNT5 T0CNT4 T0CNT3 T0CNT2 T0CNT1 T0CNT0 Initial value: 00H T0CNT[7:0] T0 Counter T0DR (Timer 0 Data Register): B4H T0DR7 T0DR6 T0DR5 T0DR4 T0DR3...
  • Page 113 A96G150 User's manual 12. Timer 0/1/2/3/4/5 T0CR (Timer 0 Control Register): B2H – T0EN T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC – Initial value: 00H T0EN Control Timer 0 Timer 0 disable Timer 0 enable T0MS[1:0] Control Timer 0 Operation Mode...

  • Page 114: Timer 1

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.2 Timer 1 A 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register high/low and timer 1 control register high/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH, T1CRL).

  • Page 115: Figure 34. 16-Bit Timer/Counter Mode Of Timer 1

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 ADDRESS:BBH – – – – T1EN T1MS1 T1MS0 T1CC T1CRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR T1CRL INITIAL VALUE : 0000_0000B – 16-bit A Data Register...

  • Page 116: 16-Bit Capture Mode

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.2.2 16-bit capture mode It uses an internal/external clock as a clock source. Basically, the 16-bit timer 1 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T1CNTH/T1CNTL is equal to T1ADRH/T1ADRL.

  • Page 117: Figure 37. 16-Bit Capture Mode Operation Example

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 T1BDRH/L Load T1CNTH/L Value Count Pulse Period Up-count TIME Ext. EINT2 PIN Interrupt Request (FLAG2) Interrupt Interval Period Figure 37. 16-bit Capture Mode Operation Example FFFF FFFF T1CNTH/L Interrupt Request (T1IFR) Ext. EINT2 PIN...

  • Page 118: 16-Bit Ppg Mode

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.2.3 16-bit PPG mode TIMER 1 has a PPG (Programmable Pulse Generation) function. In PPG mode, T1O/PWM1O pin outputs up to 16-bit resolution PWM output. For this function, T1O/PWM1O pin must be configured as a PWM output by setting P0FSRL[5:4] to ‘10’.

  • Page 119: Figure 40. 16-Bit Ppg Mode Operation Example

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 Repeat Mode(T1MS = 11b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock Counter T1ADRH/L T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L PWM1O B Match A Match 2. T1BDRH/L >= T1ADRH/L...

  • Page 120: 16-Bit Timer 1 Block Diagram

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.2.4 16-bit timer 1 block diagram In this section, a 16-bit timer 1 is described in a block diagram. 16-bit A Data Register T1ADRH/T1ADRL A Match Reload T1CC T1EN To Timer 2 T1CK[2:0] block...

  • Page 121: Register Description

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.2.6 Register description T1ADRH (Timer 1 A data High Register): BDH T1ADRH7 T1ADRH6 T1ADRH5 T1ADRH4 T1ADRH3 T1ADRH2 T1ADRH1 T1ADRH0 Initial value: FFH T1ADRH[7:0] T1 A Data High Byte T1ADRL (Timer 1 A Data Low Register): BCH...
  • Page 122 12. Timer 0/1/2/3/4/5 A96G150 User's manual T1CRH (Timer 1 Control High Register): BBH – – – – T1EN T1MS1 T1MS0 T1CC – – – – Initial value: 00H T1EN Control Timer 1 Timer 1 disable Timer 1 enable (Counter clear and start)
  • Page 123 A96G150 User's manual 12. Timer 0/1/2/3/4/5 T1CRL (Timer 1ControlLow Register): BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR – Initial value: 00H T1CK[2:0] Select Timer 1 clock source. fx is main system clock frequency T1CK2 T1CK1 T1CK0 Description fx/2048...

  • Page 124: Timer 2

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.3 Timer 2 A 16-bit timer 2 consists of a multiplexer, timer 2 A data high/low register, timer 2 B data high/low register and timer 2 control high/low register (T2ADRH, T2ADRL, T2BDRH, T2BDRL, T2CRH, and T2CRL).

  • Page 125: 16-Bit Timer/Counter Mode

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.3.1 16-bit timer/counter mode 16-bit timer/counter mode is selected by control registers, and the 16-bit timer/counter has counter registers and data registers as shown in Figure 42. The counter register is increased by internal or timer 1 A match clock input.

  • Page 126: Figure 43. 16-Bit Timer/Counter Mode Operation Example

    12. Timer 0/1/2/3/4/5 A96G150 User's manual Figure 43. 16-bit Timer/Counter Mode Operation Example...

  • Page 127: 16-Bit Capture Mode

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.3.2 16-bit capture mode Timer 2 capture mode is set by configuring T2MS[1:0] as ‘01’. It uses an internal clock as a clock source. Basically, the 16-bit timer 2 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T2CNTH/T2CNTL is equal to T2ADRH/T2ADRL.

  • Page 128: Figure 45. 16-Bit Capture Mode Operation Example

    12. Timer 0/1/2/3/4/5 A96G150 User's manual T2BDRH/L Load T2CNTH/L Value Count Pulse Period Up-count TIME Ext. EINT3 PIN Interrupt Request (FLAG3) Interrupt Interval Period Figure 45. 16-bit Capture Mode Operation Example FFFF FFFF T2CNTH/L Interrupt Request (T2IFR) Ext. EINT3 PIN...

  • Page 129: 16-Bit Ppg Mode

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.3.3 16-bit PPG mode TIMER 2 has a PPG (Programmable Pulse Generation) function. In PPG mode, T2O/PWM2O pin outputs up to 16-bit resolution PWM output. For this function, T2O/PWM2O pin must be configured as a PWM output by setting P0FSRL[3:2] to ‘10’.

  • Page 130: Figure 48. 16-Bit Ppg Mode Operation Example

    12. Timer 0/1/2/3/4/5 A96G150 User's manual Repeat Mode(T2MS = 11b) and "Start High"(T2POL = 0b). Clear and Start Set T2EN Timer 2 clock Counter T2ADRH/L T2 Interrupt 1. T2BDRH/L(5) < T2ADRH/L PWM2O B Match A Match 2. T2BDRH/L >= T2ADRH/L...

  • Page 131: 16-Bit Timer 2 Block Diagram

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.3.4 16-bit timer 2 block diagram In this section, a 16-bit timer 2 is described in a block diagram. 16-bit A Data Register T2ADRH/T2ADRL A Match Reload T2CC T2CK[2:0] T2EN INT_ACK Buffer Register A...

  • Page 132: Register Description

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.3.6 Register description T2ADRH (Timer 2 A data High Register): C5H T2ADRH7 T2ADRH6 T2ADRH5 T2ADRH4 T2ADRH3 T2ADRH2 T2ADRH1 T2ADRH0 Initial value: FFH T2ADRH[7:0] T2 A Data High Byte T2ADRL (Timer 2 A Data Low Register): C4H...
  • Page 133 A96G150 User's manual 12. Timer 0/1/2/3/4/5 T2CRH (Timer 2ControlHigh Register): C3H – – – – T2EN T2MS1 T2MS0 T2CC – – – – Initial value: 00H T2EN Control Timer 2 Timer 2 disable Timer 2 enable (Counter clear and start)

  • Page 134: Timer 3

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.4 Timer 3 A 16-bit timer 3 consists of a multiplexer, timer 3 A data high/low register, timer 3 B data high/low register and timer 3 control high/low register (T3ADRH, T3ADRL, T3BDRH, T3BDRL, T3CRH, and T3CRL).

  • Page 135: 16-Bit Timer/Counter Mode

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.4.1 16-bit timer/counter mode 16-bit timer/counter mode is selected by control registers, and the 16-bit timer/counter has counter registers and data registers as shown in Figure 50. The counter register is increased by internal or external clock input.

  • Page 136: Figure 51. 16-Bit Timer/Counter Mode Operation Example

    12. Timer 0/1/2/3/4/5 A96G150 User's manual Figure 51. 16-bit Timer/Counter Mode Operation Example...

  • Page 137: 16-Bit Capture Mode

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.4.2 16-bit capture mode Timer 3 capture mode is set by configuring T3MS[1:0] as ‘01’. It uses an internal/external clock as a clock source. Basically, the 16-bit timer 3 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T3CNTH/T3CNTL is equal to T3ADRH/T3ADRL.

  • Page 138: Figure 53. 16-Bit Capture Mode Operation Example

    12. Timer 0/1/2/3/4/5 A96G150 User's manual T3BDRH/L Load T3CNTH/L Value Count Pulse Period Up-count TIME Ext. EINT43 PIN Interrupt Request (FLAG43) Interrupt Interval Period Figure 53. 16-bit Capture Mode Operation Example FFFF FFFF T3CNTH/L Interrupt Request (T3IFR) Ext. EINT43 PIN...

  • Page 139: 16-Bit Ppg Mode

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.4.3 16-bit PPG mode TIMER 3 has a PPG (Programmable Pulse Generation) function. In PPG mode, T3O/PWM3O pin outputs up to 16-bit resolution PWM output. For this function, T3O/PWM3O pin must be configured as a PWM output by setting P0FSRL[1:0] to ‘10’...

  • Page 140: Figure 56. 16-Bit Ppg Mode Operation Example

    12. Timer 0/1/2/3/4/5 A96G150 User's manual Repeat Mode(T3MS = 11b) and "Start High"(T3POL = 0b). Clear and Start Set T3EN Timer 3 clock Counter T3ADRH/L T3 Interrupt 1. T3BDRH/L(5) < T3ADRH/L PWM3O B Match A Match 2. T3BDRH/L >= T3ADRH/L...

  • Page 141: 16-Bit Timer 3 Block Diagram

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.4.4 16-bit timer 3 block diagram In this section, a 16-bit timer 3 is described in a block diagram. 16-bit A Data Register T3ADRH/T3ADRL A Match Reload T3CC T3EN To Timer 4 T3CK[2:0] block...

  • Page 142: Register Description

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.4.6 Register description T3ADRH (Timer 3 A data High Register): 1002H T3ADRH7 T3ADRH6 T3ADRH5 T3ADRH4 T3ADRH3 T3ADRH2 T3ADRH1 T3ADRH0 Initial value: FFH T3ADRH[7:0] T3 A Data High Byte T3ADRL (Timer 3 A Data Low Register): 1003H...
  • Page 143 A96G150 User's manual 12. Timer 0/1/2/3/4/5 T3CRH (Timer 3 Control High Register): 1000H – – – – T3EN T3MS1 T3MS0 T3CC – – – – Initial value: 00H T3EN Control Timer 3 Timer 3 disable Timer 3 enable (Counter clear and start)
  • Page 144 12. Timer 0/1/2/3/4/5 A96G150 User's manual T3CRL (Timer 3 Control Low Register): 1001H – T3CK2 T3CK1 T3CK0 T3IFR T3POL T3ECE T3CNTR – Initial value: 00H T3CK[2:0] Select Timer 3 clock source. fx is main system clock frequency T3CK2 T3CK1 T3CK0 Description...

  • Page 145: Timer 4

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.5 Timer 4 A 16-bit timer 4 consists of a multiplexer, timer 4 A data high/low register, timer 4 B data high/low register and timer 4 control high/low register (T4ADRH, T4ADRL, T4BDRH, T4BDRL, T4CRH, and T4CRL).

  • Page 146: 16-Bit Timer/Counter Mode

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.5.1 16-bit timer/counter mode 16-bit timer/counter mode is selected by control registers, and the 16-bit timer/counter has counter registers and data registers as shown in Figure 58. The counter register is increased by internal or timer 4 A match clock input.

  • Page 147: Figure 59. 16-Bit Timer/Counter Mode Operation Example

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 Figure 59. 16-bit Timer/Counter Mode Operation Example...

  • Page 148: 16-Bit Capture Mode

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.5.2 16-bit capture mode Timer 4 capture mode is set by configuring T4MS[1:0] as ‘01’. It uses an internal clock as a clock source. Basically, the 16-bit timer 4 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T4CNTH/T4CNTL is equal to T4ADRH/T4ADRL.

  • Page 149: Figure 61. 16-Bit Capture Mode Operation Example

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 T4BDRH/L Load T4CNTH/L Value Count Pulse Period Up-count TIME Ext. EINT44 PIN Interrupt Request (FLAG44) Interrupt Interval Period Figure 61. 16-bit Capture Mode Operation Example FFFF FFFF T4CNTH/L Interrupt Request (T4IFR) Ext. EINT44 PIN...

  • Page 150: 16-Bit Ppg Mode

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.5.3 16-bit PPG mode TIMER 4 has a PPG (Programmable Pulse Generation) function. In PPG mode, T4O/PWM4O pin outputs up to 16-bit resolution PWM output. For this function, T4O/PWM4O pin must be configured as a PWM output by setting P2FSRH[7:6] to ‘10’.

  • Page 151: Figure 64. 16-Bit Ppg Mode Operation Example

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 Repeat Mode(T4MS = 11b) and "Start High"(T4POL = 0b). Clear and Start Set T4EN Timer 4 clock Counter T4ADRH/L T4 Interrupt 1. T4BDRH/L(5) < T4ADRH/L PWM4O B Match A Match 2. T4BDRH/L >= T4ADRH/L...

  • Page 152: 16-Bit Timer 4 Block Diagram

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.5.4 16-bit timer 4 block diagram In this section, a 16-bit timer 4 is described in a block diagram. 16-bit A Data Register T4ADRH/T4ADRL A Match Reload T4CC T4CK[2:0] T4EN Buffer Register A Clear...

  • Page 153: Register Description

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.5.6 Register description T4ADRH (Timer 4 A data High Register): 100AH T4ADRH7 T4ADRH6 T4ADRH5 T4ADRH4 T4ADRH3 T4ADRH2 T4ADRH1 T4ADRH0 Initial value: FFH T4ADRH[7:0] T4 A Data High Byte T4ADRL (Timer 4 A Data Low Register): 100BH...
  • Page 154 12. Timer 0/1/2/3/4/5 A96G150 User's manual T4CRH (Timer 4 Control High Register): 1008H – – – – T4EN T4MS1 T4MS0 T4CC – – – – Initial value: 00H T4EN Control Timer 4 Timer 4 disable Timer 4 enable (Counter clear and start)

  • Page 155: Timer 5

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.6 Timer 5 A 16-bit timer 5 consists of a multiplexer, timer 5 A data high/low register, timer 5 B data high/low register and timer 5 control high/low register (T5ADRH, T5ADRL, T5BDRH, T5BDRL, T5CRH, and T5CRL).

  • Page 156: 16-Bit Timer/Counter Mode

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.6.1 16-bit timer/counter mode 16-bit timer/counter mode is selected by control registers, and the 16-bit timer/counter has counter registers and data registers as shown in Figure 66. The counter register is increased by internal clock input.

  • Page 157: Figure 67. 16-Bit Timer/Counter Mode Operation Example

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 Figure 67. 16-bit Timer/Counter Mode Operation Example...

  • Page 158: 16-Bit Capture Mode

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.6.2 16-bit capture mode Timer 5 capture mode is set by configuring T5MS[1:0] as ‘01’. It uses an internal clock as a clock source. Basically, the 16-bit timer 5 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T5CNTH/T5CNTL is equal to T5ADRH/T5ADRL.

  • Page 159: Figure 69. 16-Bit Capture Mode Operation Example

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 T5BDRH/L Load T5CNTH/L Value Count Pulse Period Up-count TIME Ext. EINT45 PIN Interrupt Request (FLAG45) Interrupt Interval Period Figure 69. 16-bit Capture Mode Operation Example FFFF FFFF T5CNTH/L Interrupt Request (T5IFR) Ext. EINT45 PIN...

  • Page 160: 16-Bit Ppg Mode

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.6.3 16-bit PPG mode TIMER 5 has a PPG (Programmable Pulse Generation) function. In PPG mode, T5O/PWM5O pin outputs up to 16-bit resolution PWM output. For this function, T5O/PWM5O pin must be configured as a PWM output by setting P2FSRH[5:4] to ‘10’.

  • Page 161: Figure 72. 16-Bit Ppg Mode Operation Example

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 Repeat Mode(T5MS = 11b) and "Start High"(T5POL = 0b). Clear and Start Set T5EN Timer 5 clock Counter T5ADRH/L T5 Interrupt 1. T5BDRH/L(5) < T5ADRH/L PWM5O B Match A Match 2. T5BDRH/L >= T5ADRH/L...

  • Page 162: 16-Bit Timer 5 Block Diagram

    12. Timer 0/1/2/3/4/5 A96G150 User's manual 12.6.4 16-bit timer 5 block diagram In this section, a 16-bit timer 5 is described in a block diagram. 16-bit A Data Register T5ADRH/T5ADRL A Match Reload T5CC T5CK[2:0] T5EN Buffer Register A Clear...

  • Page 163: Register Description

    A96G150 User's manual 12. Timer 0/1/2/3/4/5 12.6.6 Register description T5ADRH (Timer 5 A data High Register): 1012H T5ADRH7 T5ADRH6 T5ADRH5 T5ADRH4 T5ADRH3 T5ADRH2 T5ADRH1 T5ADRH0 Initial value: FFH T5ADRH[7:0] T5 A Data High Byte T5ADRL (Timer 5 A Data Low Register): 1013H...
  • Page 164 12. Timer 0/1/2/3/4/5 A96G150 User's manual T5CRH (Timer 5 Control High Register): 1010H – – – – T5EN T5MS1 T5MS0 T5CC – – – – Initial value: 00H T5EN Control Timer 5 Timer 5 disable Timer 5 enable (Counter clear and start)

  • Page 165: Buzzer Driver

    13. Buzzer driver Buzzer driver A buzzer of A96G150 consists of 8-bit counter, a buzzer data register (BUZDR), and a buzzer control register (BUZCR). It outputs square wave (61.035Hz to 125.0KHz @ 8MHz) through P53/BUZO pin, and its buzzer data register (BUZDR) controls the buzzer frequency (refer to the following expression).

  • Page 166: Register Map

    13. Buzzer driver A96G150 User's manual 13.2 Register map Table 27. Buzzer Driver Register Map Name Address Direction Default Description BUZDR Buzzer Data Register BUZCR Buzzer Control Register...

  • Page 167: Register Description

    A96G150 User's manual 13. Buzzer driver 13.3 Register description BUZDR (Buzzer Data Register): 8FH BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 Initial value: FFH BUZDR[7:0] This bits control the Buzzer frequency Its resolution is 00H ~ FFH BUZCR (Buzzer Control Register): 97H –...

  • Page 168: 12-Bit Adc

    A96G150 User's manual 12-bit ADC Analog-to-digital converter (ADC) of A96G150 allows conversion of an analog input signal to corresponding 12-bit digital value. This A/D module has eight analog inputs. Output of the multiplexer becomes input into the converter which generates the result through successive approximation.

  • Page 169: Block Diagram

    A96G150 User's manual 14. 12-bit ADC 14.2 Block diagram In this section, the 12-bit ADC is described in a block diagram, and an analog input pin and a power pin with capacitors respectively are introduced. TRIG[2:0] ADSEL[3:0] (Select one input pin...

  • Page 170: Adc Operation

    14. 12-bit ADC A96G150 User's manual 14.3 ADC operation In this section, control registers and align bits are introduced in Figure 78, and ADC operation flow sequence is introduced in Figure 79. Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8...

  • Page 171: Figure 79. Adc Operation Flow Sequence

    A96G150 User's manual 14. 12-bit ADC Figure 79. ADC Operation Flow Sequence...

  • Page 172: Register Map

    14. 12-bit ADC A96G150 User's manual 14.4 Register map Table 28. ADC Register Map Name Address Direction Default Description ADCDRH A/D Converter Data High Register ADCDRL A/D Converter Data Low Register ADCCRH A/D Converter Control High Register ADCCRL A/D Converter Control Low Register...

  • Page 173: Register Description

    A96G150 User's manual 14. 12-bit ADC 14.5 Register description ADCDRH (A/D Converter Data High Register):9FH ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDM6 ADDM5 ADDM4 ADDL11 ADDL10 ADDL9 ADDL8 Initial value: xxH ADDM[11:4] MSB align, A/D Converter High Data (8-bit) ADDL[11:8] LSB align, A/D Converter High Data (4-bit)
  • Page 174 14. 12-bit ADC A96G150 User's manual ADCCRH (A/D Converter High Register): 9DH ADCIFR IREF TRIG2 TRIG1 TRIG0 ALIGN CKSEL1 CKSEL0 Initial value: 01H When ADC interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ ADCIFR to this bit or auto clear by INT_ACK signal. Writing “1” has no effect.
  • Page 175 A96G150 User's manual 14. 12-bit ADC ADCCRL (A/D Converter Counter Low Register): 9CH STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value: 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable...

  • Page 176: Combination Of Usart, Spi, And I2C (Usi)

    Combination of USART, SPI, and I2C (USI) USI stands for the combination of USART, SPI and I2C. A96G150 has two USI function blocks, USI0 and USI1, which are identical to each other functionally. Each USI block consists of USI control registers...

  • Page 177: Usin Uart Mode

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.1 USIn UART mode Universal synchronous and asynchronous serial receiver and transmitter (USART) are highly flexible serial communication devices. Main features are listed below: Full Duplex Operation (Independent Serial Receive and Transmit Registers) ...

  • Page 178: Usin Uart Block Diagram

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual 15.2 USIn UART block diagram Master SCKn Control USInMS[1:0] SCLK USInBD (fx: System clock) To interrupt block Baud Rate Generator DBLSn WAKEIEn RXCIEn Clock Sync Logic At Stop mode...

  • Page 179: Usin Clock Generation

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.3 USIn clock generation Figure 81. Clock Generation Block Diagram (USIn) Clock generation logic generates base clock signal for the transmitter and the receiver. The USIn supports four modes of clock operation such as normal asynchronous mode, double speed asynchronous mode, master synchronous mode and slave synchronous mode.

  • Page 180: Usin External Clock (Sckn)

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual 15.4 USIn external clock (SCKn) External clocking is used in synchronous mode of operation. External clock input from the SCKn pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.

  • Page 181: Usin Synchronous Mode Operation

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.5 USIn synchronous mode operation When synchronous mode or SPI mode is used, SCKn pin will be used as either clock input (slave) or clock output (master).Data sampling and transmitter are issued on the different edge of SCKn clock respectively.

  • Page 182: Usin Uart Data Format

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual 15.6 USIn UART data format A serial frame is defined to have one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. USART supports 30 combinations of the followings as a...

  • Page 183: Usin Uart Parity Bit

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.7 USIn UART parity bit Parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, result of the exclusive-OR is inverted. The parity bit is located between the MSB and the first stop bit of a serial frame.

  • Page 184: Usin Uart Transmitter Flag And Interrupt

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual 15.8.2 USIn UART transmitter flag and interrupt The USART transmitter has two flags which indicate its state. One is USART data register empty flag (DREn) and the other is transmit completion flag (TXCn). Both flags can be interrupt sources.

  • Page 185: Usin Uart Receiver

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.9 USIn UART receiver The USART receiver is enabled by setting the RXEn bit in the USInCR2 register. When the receiver is enabled, the RXDn pin should be set to RXDn function for the serial input pin of UART by P1FSRH[1:0], P2FSRL[1:0] and P2FSRL[5:4].

  • Page 186: Usin Uart Parity Checker

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual The frame error (FEn) flag indicates the state of the first stop bit. The FEn flag is ‘0’ when the stop bit was correctly detected as “1”, and the FEn flag is “1” when the stop bit was incorrect, i.e. detected as “0”.

  • Page 187: Figure 84. Asynchronous Start Bit Sampling (Usin)

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate is 16 times of the baud-rate in normal mode and 8 times the baud-rate for double speed mode (DBLSn=1).

  • Page 188: Figure 85. Asynchronous Sampling Of Data And Parity Bit (Usin)

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual The data recovery process is then repeated until a complete frame is received including the first stop bit. The decided bit value is stored in the receive shift register in order. Note that the Receiver only uses the first stop bit of a frame.

  • Page 189: 15.10 Usin Spi Mode

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.10 USIn SPI mode The USIn can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. Full duplex, three-wire synchronous data transfer ...

  • Page 190: 15.11 Usin Spi Clock Formats And Timing

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual 15.11 USIn SPI clock formats and timing To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the USIn has a clock polarity bit (CPOLn) and a clock phase control bit (CPHAn) to select one of four clock formats for data transfers.

  • Page 191: Figure 87. Usin Spi Clock Formats When Cphan = 0

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) SCKn (CPOLn=0) SCKn (CPOLn=1) SAMPLE MOSIn MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISOn /SSn OUT (MASTER) /SSn IN (SLAVE) Figure 87.

  • Page 192: Figure 88. Usin Spi Clock Formats When Cphan = 1

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual SCKn (CPOLn=0) SCKn (CPOLn=1) SAMPLE MOSIn MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISOn /SSn OUT (MASTER) /SSn IN (SLAVE) Figure 88.

  • Page 193: 15.12 Usin Spi Block Diagram

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.12 USIn SPI block diagram USInBD Control SCLK Baud Rate Generator (fx: System clock) MASTERn USInSSEN Edge Detector SCKn Control Controller FXCHn RXEn CPOLn CPHAn MISOn Data Receive Shift Register...

  • Page 194: 15.13 Usin I2C Mode

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual 15.13 USIn I2C mode The USIn can be set to operate in industrial standard serial communication protocols mode. The I2C mode uses 2 bus lines serial data line (SDAn) and serial clock line (SCLn) to exchange data. Because both SDAn and SCLn lines are open-drain output, each line needs pull-up resistor.

  • Page 195: 15.14 Usin I2C Bit Transfer

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.14 USIn I2C bit transfer The data on the SDAn line must be stable during HIGH period of the clock, SCLn. The HIGH or LOW state of the data line can only change when the clock signal on the SCLn line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high.

  • Page 196: 15.15 Usin I2C Start/Repeated Start/Stop

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual 15.15 USIn I2C START/repeated START/STOP One master can issue a START (S) condition to notice other devices connected to the SCLn, SDAn lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines so that other devices can use it.

  • Page 197: 15.16 Usin I2C Data Transfer

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.16 USIn I2C data transfer Every byte put on the SDAn line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first.

  • Page 198: 15.17 Usin I2C Acknowledge

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual 15.17 USIn I2C acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDAn line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDAn line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.

  • Page 199: 15.18 Usin I2C Synchronization/Arbitration

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.18 USIn I2C synchronization/arbitration Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCLn line. This means that a HIGH to LOW transition on the SCLn line will cause the devices concerned to start counting off their LOW period and it will hold the SCLn line in that state until the clock HIGH state is reached.

  • Page 200: 15.19 Usin I2C Operation

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual 15.19 USIn I2C operation The I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a transmission of a START condition. Because the I2C is interrupt based, the application software is free to carry on other operations during an I2C byte transfer.
  • Page 201 A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) To operate as a slave when the MLOSTn bit in USInST2 is set, the ACKnEN bit in USInCR4 must be set and the received 7-bit address must equal to the USInSLA[6:0] bits in USInSAR.

  • Page 202: 15.19.2 Usin I2C Master Receiver

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual After doing one of the actions above, write any arbitrary to USInST2 to release SCLn line. For the case 1, move to step 7. For the case 2, move to step 9 to handle STOP interrupt. For the case 3, move to step 6 after transmitting the data in USInDR, and if transfer direction bit is ‘1’...
  • Page 203 A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) To operate as a slave when the MLOSTn bit in USInST2 is set, the ACKnEN bit in USInCR4 must be set and the received 7-bit address must equal to the USInSLA[6:0] bits in USInSAR.

  • Page 204: 15.19.3 Usin I2C Slave Transmitter

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual After doing one of the actions above, write arbitrary value to USInST2 to release SCLn line. For the case 1 and case 2, move to step 7. For the case 3, move to step 9 to handle STOP interrupt.

  • Page 205: 15.19.4 Usin I2C Slave Receiver

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) Case 1: No ACK signal is detected and I2C waits STOP or repeated START condition. Case 2: ACK signal from master is detected. Load data to transmit into USInDR.
  • Page 206 15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual Case 1: No ACK signal is detected (ACKnEN=0) and I2C waits STOP or repeated START condition. Case 2: ACK signal is detected (ACKnEN=1) and I2C can continue to receive data from master.

  • Page 207: 15.20 Usin I2C Block Diagram

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.20 USIn I2C block diagram IICnIFR To interrupt block Slave Address Register USInSAR RXACKn, GCALLn, Interrupt IICnIE TENDn, STOPDn, Generator SSELn, MLOSTn, General Call And USInGCE BUSYn, TMODEn Address Detector...

  • Page 208: 15.21 Register Map

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual 15.21 Register map Table 31. USI Register Map Name Address Direction Default Description USI0BD USI0 Baud Rate Generation Register USI0DR USI0 Data Register USI0SDHR USI0 SDA Hold Time Register...

  • Page 209: 15.22 Usin Register Description

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.22 USIn register description USInBD (USIn Baud- Rate Generation Register: For UART and SPI mode): E3H/F3H, n = 0, 1 USInBD7 USInBD 6 USInBD 5 USInBD 4 USInBD 3...
  • Page 210 15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual USInSCHR (USInSCL High Period Register: For I2C mode): E7H/F7H, n = 0, 1 USInSCHR7 USInSCHR6 USInSCHR5 USInSCHR 4 USInSCHR 3 USInSCHR 2 USInSCHR 1 USInSCHR 0 Initial value: 3FH...
  • Page 211 A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) USInCR1 (USIn Control Register 1: For UART, SPI, and I2C mode): D9H/E9H, n = 0, 1 USInS1 USInS0 USInMS1 USInMS0 USInPM1 USInPM0 USInS2 CPOLn ORDn CPHAn Initial value: 00H...
  • Page 212 15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual USInCR2 (USIn Control Register 2: For UART, SPI, and I2C mode): DAH/EAH, n = 0, 1 DRIEn TXCIEn RXCIEn WAKEIEn TXEn RXEn USInEN DBLSn Initial value: 00H DRIEn Interrupt enable bit for data register empty (only UART and SPI mode).
  • Page 213 A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) USInCR3 (USIn Control Register 3: For UART, SPI, and I2C mode): DBH/EBH, n = 0, 1 MASTERn LOOPSn DISSCKn USInSSEN FXCHn USInSB USInTX8 USInRX8 Initial value: 00H MASTERn Selects master or slave in SPI and synchronous mode operation and controls the direction of SCKn pin Slave mode operation (External clock for SCKn).
  • Page 214 15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual USI0CR4 (USIn Control Register 4: For I2C mode): DCH/ECH, n = 0, 1 – IICnIFR RESETn IICnIE ACKnEN IMASTERn STOPCn STARTCn – Initial value: 00H IICnIFR This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’.
  • Page 215 A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) USInST1 (USIn Status Register 1: For UART and SPI mode): E1H/F1H, n = 0, 1 DREn TXCn RXCn WAKEn USInRST DORn Initial value: 80H DREn The DREn flag indicates if the transmit buffer (USInDR) is ready to receive new data.
  • Page 216 15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual USInST2 (USIn Status Register 2: For I2C mode): E2H/F2H, n = 0, 1 GCALLn TENDn STOPDn SSELn MLOSTn BUSYn TMODEn RXACKn Initial value: 00H NOTE GCALLn This bit has different meaning depending on whether I2C is master or slave.

  • Page 217: Baud Rate Settings (Example)

    A96G150 User's manual 15. Combination of USART, SPI, and I2C (USI) 15.23 Baud rate settings (example) Table 32. Example1 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies Baud rate fx = 1.00MHz fx = 1.8432MHz fx = 2.00MHz (bps)

  • Page 218: Table 33. Example2 Of Usi0Bd And Usi1Bdsettings For Commonly Used Oscillator Frequencies

    15. Combination of USART, SPI, and I2C (USI) A96G150 User's manual Table 33. Example2 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies Baud rate fx = 8.00MHz fx = 11.0592MHz (bps) USI0BD/USI1BD Error USI0BD/USI1BD Error ― ― 2400 0.2% 4800 0.2%...

  • Page 219: Usart2

    A96G150 User's manual 16. USART2 USART2 Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. USART2 of A96G150 features the followings: Full Duplex Operation (Independent Serial Receive and Transmit Registers)  Asynchronous or Synchronous Operation ...

  • Page 220: Block Diagram

    16. USART2 A96G150 User's manual 16.1 Block diagram UBAUD SCLK Baud Rate Generator Master Clock Sync Logic Control UMSEL[1:0] Rx Interrupt RXD2/ MISO2 Clock Control Recovery Data Recovery UMSEL1&UMSEL0 DOR/PE/FE UDATA[0] Master Checker (Rx) UDATA[1] Stop bit UMSEL0 (Rx) Generator...

  • Page 221: Clock Generation

    A96G150 User's manual 16. USART2 16.2 Clock generation Clock generation logic generates a base clock signal for the Transmitter and the Receiver. USART2 supports four modes of clock operation such as Normal Asynchronous mode, Double Speed Asynchronous mode, Master Synchronous mode, and Slave Synchronous mode.

  • Page 222: External Clock (Xck)

    16. USART2 A96G150 User's manual 16.3 External clock (XCK) External clocking is used by the synchronous or SPI slave modes of operation. External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must then pass through an edge detector before it can be used by the Transmitter and Receiver.

  • Page 223: Synchronous Mode Operation

    A96G150 User's manual 16. USART2 16.4 Synchronous mode operation When synchronous mode or SPI mode is used, the XCK pin will be used as either clock input (slave) or clock output (master). The dependency between a clock edge and data sampling or data change is the same.

  • Page 224: Data Format

    16. USART2 A96G150 User's manual 16.5 Data format A serial frame is defined to consist of one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. USART2 supports all 30 combinations of the followings as a valid frame format.

  • Page 225: Parity Bit

    A96G150 User's manual 16. USART2 16.6 Parity bit Parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive-or is inverted. The parity bit is located between St + bits and first stop bit of a serial frame.

  • Page 226: Usart2 Transmitter

    16. USART2 A96G150 User's manual 16.7 USART2 transmitter USART2 Transmitter is enabled by setting the TXE bit in UCTRL1 register. When the Transmitter is enabled, normal port operation of TXD2 pin is overridden by serial output pin of the USART2. Baud rate, operation mode and frame format must be setup once before doing any transmissions.

  • Page 227: Parity Generator

    A96G150 User's manual 16. USART2 16.7.3 Parity generator Parity Generator calculates the parity bit for the sending serial frame data. When parity bit is enabled (UPM[1] = 1), transmitter control logic inserts the parity bit between bits and the first stop bit of the sending frame.

  • Page 228: Usart2 Receiver

    16. USART2 A96G150 User's manual 16.8 USART2 receiver USART2 Receiver is enabled by setting the RXE bit in the UCTRL1 register. When the Receiver is enabled, normal pin operation of RXD2 pin is overridden by the USART2 as the serial input pin of the Receiver.

  • Page 229: Parity Checker

    A96G150 User's manual 16. USART2 Frame Error (FE) flag indicates the state of the first stop bit. The FE flag is set when the stop bit was correctly detected as “1”, and the FE flag is cleared when the stop bit was incorrect, i.e. detected as “0”.

  • Page 230: Figure 101. Start Bit Sampling

    16. USART2 A96G150 User's manual Figure 101 describes sampling process of the start bit of an incoming frame. The sampling rate is 16 times the baud rate for normal mode, and 8 times the baud rate for Double Speed mode (U2X=1). The horizontal arrows show the synchronization variation due to the asynchronous sampling process.

  • Page 231: Figure 102. Sampling Of Data And Parity Bit

    A96G150 User's manual 16. USART2 If more than 2 samples have low levels, the received bit is considered to a logic 0. If more than 2 samples have high levels, the received bit is considered to a logic 1. The data recovery process is then repeated until a complete frame is received including the first stop bit.

  • Page 232: Spi Mode

    16. USART2 A96G150 User's manual 16.9 SPI mode The USART2 can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. Full duplex, three-wire synchronous data transfer  Master or Slave operation ...

  • Page 233: Figure 104. Spi Clock Formats When Ucpha = 0

    A96G150 User's manual 16. USART2 (UCPOL=0) (UCPOL=1) SAMPLE MOSI MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 104. SPI Clock Formats when UCPHA = 0 When UCPHA=0, the slave begins to drive its MISO2 output with the first data bit value when SS goes to active low.

  • Page 234: Figure 105. Spi Clock Formats When Ucpha = 1

    16. USART2 A96G150 User's manual (UCPOL=0) (UCPOL=1) SAMPLE MOSI2 MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISO2 /SS2 OUT (MASTER) /SS2 IN (SLAVE) Figure 105. SPI Clock Formats when UCPHA = 1 When UCPHA=1, the slave begins to drive its MISO2 output when SS2 goes active low, but the data is not defined until the first XCK edge.

  • Page 235: Receiver Time Out (Rto)

    A96G150 User's manual 16. USART2 16.10 Receiver time out (RTO) This USART2 system supports the time out function. This function is occur the interrupts when stop bit are not in RX line during URTOC setting value. RTO count stops in RXD signal live state and RTO clear and start is executed by stop bit recognition.

  • Page 236: 16.11 Register Map

    16. USART2 A96G150 User's manual 16.11 Register map Table 37. USART2 Register Map Name Address Direction Default Description UCTRL1 USART2 Control 1 Register UCTRL2 USART2 Control 2 Register UCTRL3 USART2 Control 3 Register UCTRL4 1018H USART2 Control 4 Register USTAT...

  • Page 237: 16.12 Register Description

    A96G150 User's manual 16. USART2 16.12 Register description UCTRL1 (USART2 Control 1 Register) CBH USIZE1 USIZE0 UMSEL1 UMSEL0 UPM1 UPM0 USIZE2 UCPOL UDORD UCPHA Initial value: 00 UMSEL[1:0] Selects operation mode of USART2 UMSEL1 UMSEL0 Operating Mode Asynchronous Mode (Normal Uart)
  • Page 238 16. USART2 A96G150 User's manual UCTRL2 (USART2 Control 2 Register) CCH UDRIE TXCIE RXCIE WAKEIE USARTEN Initial value: 00 UDRIE Interrupt enable bit for USART2 Data Register Empty. Interrupt from UDRE is inhibited (use polling) When UDRE is set, request an interrupt TXCIE Interrupt enable bit for Transmit Complete.
  • Page 239 A96G150 User's manual 16. USART2 UCTRL3 (USART2 Control 3 Register) CDH MASTER LOOPS DISXCK SPISS USBS Initial value: 00 MASTER Selects master or slave in SPI or Synchronous mode operation and controls the direction of XCK pin. Slave mode operation and XCK is input pin.
  • Page 240 16. USART2 A96G150 User's manual UCTRL4 (USART2 Control 4 Register) 1018H RTOEN RTO_FLAG FPCREN AOVSSEL AOVSEN Initial value: 00 RTOEN Enable receiver time out. Disable Enable RTO_FLAG This bit is set when RTO count overflows. This flag can generate an RTO interrupt.
  • Page 241 A96G150 User's manual 16. USART2 USTAT (USART2 Status Register) CFH UDRE WAKE SOFTRST Initial value: 80 UDRE The UDRE flag indicates if the transmit buffer (UDATA) is ready to be loaded with new data. If UDRE is ‘1’, it means the transmit buffer is empty and can hold one or two new data.
  • Page 242 16. USART2 A96G150 User's manual UBAUD (USART Baud-Rate Generation Register) FCH UBAUD7 UBAUD6 UBAUD5 UBAUD4 UBAUD3 UBAUD2 UBAUD1 UBAUD0 Initial value: FF UBAUD [7:0] The value in this register is used to generate internal baud rate in asynchronous mode or to generate XCK clock in synchronous or SPI mode.
  • Page 243 A96G150 User's manual 16. USART2 RTOCH (Receiver Time Out Counter High Register) 101AH RTOCH7 RTOCH6 RTOCH5 RTOCH4 RTOCH3 RTOCH2 RTOCH1 RTOCH0 Initial value: 00 RTOCL (Receiver Time Out Counter Low Register) 101BH RTOCL7 RTOCL6 RTOCL5 RTOCL4 RTOCL3 RTOCL2 RTOCL1 RTOCL0...

  • Page 244: Baud Rate Settings (Example)

    16. USART2 A96G150 User's manual 16.13 Baud rate settings (example) Table 38. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies Baud fOSC=1.00MHz fOSC=1.8432MHz fOSC=2.00MHz Rate U2X=0 U2X=1 U2X=0 U2X=1 U2X=0 U2X=1 UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR...

  • Page 245: 16.14 0% Error Baud Rate

    16. USART2 16.14 0% Error baud rate USART2 system of A96G150 supports floating point counter logic for 0% error of baud rate. By using 8-bit floating point counter logic, cumulative error to below the decimal point can be removed. Floating point counter value is defined by baud rate error. In the baud rate formula, BAUD is presented in the integer count value.

  • Page 246: Lcd Driver

    17. LCD Driver A96G150 User's manual LCD Driver The LCD driver is controlled by the LCD control register (LCD_CR) and LCD driver bias and contrast control register (LCD_BCCR). The LCLK[1:0] determines the frequency of COM signal scanning of each segment output. A RESET clears the LCD control register LCD_CR and LCD_BCCR values to logic ‘0’.

  • Page 247: Lcd Display Ram Organization

    A96G150 User's manual 17. LCD Driver 17.1 LCD Display RAM organization Display data are stored to the display data area in the external data memory. The display data which stored to the display external data area (address 1050H-1067H) are read automatically and sent to the LCD driver by the hardware.

  • Page 248: Lcd Signal Waveform

    17. LCD Driver A96G150 User's manual 17.2 LCD Signal waveform SEG2 SEG4 SEG3 COM0 1 Frame VLC0 VLC1 COM1 COM0 VLC2 COM2 VLC0 VLC1 COM1 VLC2 VLC0 VLC1 COM2 VLC2 VLC0 VLC1 SEG2 VLC2 VLC0 VLC1 SEG3 VLC2 +VLC0 +VLC1...

  • Page 249: Figure 110. Lcd Signal Waveforms (1/4 Duty, 1/3 Bias)

    A96G150 User's manual 17. LCD Driver SEG4 SEG3 COM0 1 Frame COM1 VLC0 VLC1 COM2 COM0 VLC2 COM3 VLC0 VLC1 COM1 VLC2 VLC0 VLC1 COM2 VLC2 VLC0 VLC1 SEG3 VLC2 VLC0 VLC1 SEG4 VLC2 +VLC0 +VLC1 +VLC2 COM0-SEG3 -VLC2 -VLC1 -VLC0 Figure 110.

  • Page 250: Figure 111. Lcd Signal Waveforms (1/8 Duty, 1/4 Bias)

    17. LCD Driver A96G150 User's manual COM0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 COM1 COM2 COM3 COM4 1 Frame COM5 COM6 VLC0 COM7 VLC1 COM0 VLC2 VLC3 VLC0 VLC1 COM1 VLC2...

  • Page 251: Internal Resistor Bias Connection

    A96G150 User's manual 17. LCD Driver 17.3 Internal resistor bias connection (1/ 2 Bia s ) VLCD VLC0 VLC1 VLC2 VLC3 DIS P LCTEN (1/ 3 BIAS) VLCD VLC0 VLC1 VLC2 VLC3 DIS P LCTEN (1/ 4 BIAS) VLCD VLC0...

  • Page 252: External Resistor Bias Connection

    17. LCD Driver A96G150 User's manual 17.4 External resistor bias connection (1/ 2 Bia s ) VLCD DIS P LCTEN VLC0 VLC1 VLC2 VLC3 (1/ 3 BIAS) VLCD DIS P LCTEN VLC0 VLC1 VLC2 VLC3 (1/ 4 BIAS) VLCD DIS P...

  • Page 253: Lcd Automatic Bias Control Timing

    A96G150 User's manual 17. LCD Driver 17.5 LCD Automatic bias control timing Bias Mode A Bias Mode B Bias Mode A Bias Mode B NOTE: Refer to the below when the LCD automatic bias is on.  “Bias Mode A”: Always RLCD1 (10kΩ).

  • Page 254: Block Diagram

    17. LCD Driver A96G150 User's manual 17.6 Block diagram LCD Display DATA Register Segment SEGx Driver Display Data Select Controller Display Data Buffer Register LCDCLKSEL of LCDBCCRH Register SUB OSC WDTRC Common Driver COMx LCLK Timing Controller LCD_CR Voltage VLCx...

  • Page 255: Register Map

    A96G150 User's manual 17. LCD Driver 17.7 Register map Table 39. LCD Register Map Name Address Direction Default Description LCDCR 1048H LCD Driver Control Register LCDBCCRH 1049H LCD Automatic Bias and Contrast Control High Register LCDBCCRL 104AH LCD Automatic Bias and Contrast...

  • Page 256: Register Description

    17. LCD Driver A96G150 User's manual 17.8 Register description LCDCR (LCD Driver Control Register): 1048H IRSEL[1] IRSEL[0] DBS[2] DBS[1] DBS[0] LCLK[1] LCLK[0] DISP Initial value: 00H IRSEL[1:0] Internal LCD Bias Dividing Resistor Selection bits. IRSEL1 IRSEL0 Description RLCD3, 105/105/80[kΩ] @(1/2)/(1/3)/(1/4) bias.
  • Page 257 A96G150 User's manual 17. LCD Driver LCDBCCRH (LCD Automatic Bias and Contrast Control High Register): 1049H LCDCLKSEL[1] LCDCLKSEL[0] LCDABC BMSEL[2] BMSEL[1] BMSEL[0] Initial value: 00H LCDCLKSEL[1:0] LCD Clock Selection bits. LCDCLK LCDCLK Description SEL1 SEL0 SUB OSC WDTRC Clock fx (system clock frequency)
  • Page 258 17. LCD Driver A96G150 User's manual LCDBCCRL (LCD Automatic Bias and Contrast Control Low Register): 104AH LCTEN VLCD[3] VLCD[2] VLCD[1] VLCD[0] Initial value: 00H LCTEN LCD Driver Contrast Control bit. Disable LCD driver contrast. Enable LCD driver contrast. VLCD[3:0] VLC0 Voltage Control when the contrast is enabled.
  • Page 259 A96G150 User's manual 17. LCD Driver LCDBSSRH (LCD source Selection High Register): 104BH VLE_EN LCDDR LCDEPEN Initial value: 00H VLE_EN LCD External Bias Control bit External Bias Disable External Bias Enable LCDDR LCD Driving Resistor for Bias Select. Internal LCD driving resistors for bias...

  • Page 260: Cyclic Redundancy Check (Crc)

    18. Cyclic Redundancy Check (CRC) A96G150 User's manual Cyclic Redundancy Check (CRC) Using the CRC, it can be monitor the memory of the specified area. This is a one-time operation, and reset is required for continuous operation. In CRC MNT mode, when the CRC read is finished, CRC_FLAG occurs.

  • Page 261: Register Map

    A96G150 User's manual 18. Cyclic Redundancy Check (CRC) 18.2 Register map Table 41. CRC Register Map Name Address Direction Default Description CRC_CON 1070H CRC Control Register CRC_H 1072H CRC High Register CRC_L 1073H CRC Low Register CRC_MNT_H 1074H CRC Monitor High Register...

  • Page 262: Register Description

    18. Cyclic Redundancy Check (CRC) A96G150 User's manual 18.3 Register description CRC_CON (CRC Control Register): 1070H CRC_FLAG CRC_INTEN CRC_ CRC_EN CRC_FAIL CRC_TYPE 2 CRC_TYPE 1 CRC_TYPE 0 RESETEN Initial value: 00H CRC flag. The flag is cleared only by writing a ‘0’ to the bit. So, the flag CRC_FLAG should be cleared by software.
  • Page 263 A96G150 User's manual 18. Cyclic Redundancy Check (CRC) CRC_MNT_H (CRC Monitor High Register): 1074H CRC_ CRC_ CRC_ CRC_ CRC_ CRC_ CRC_ CRC_ MNT[15] MNT[14] MNT[13] MNT[12] MNT[11] MNT[10] MNT[9] MNT[8] Initial value: 00H CRC_MNT_L (CRC Monitor Low Register): 1075H CRC_MNT[7]...

  • Page 264: Polynomial

    18. Cyclic Redundancy Check (CRC) A96G150 User's manual CRC_ADDR_END_M (CRC END Address Middle Register): 107DH CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ END[15] END[14] END[13] END[12] END[11] END[10] END[9] END[8] Initial value: 00H CRC_ADDR_END_L (CRC END Address Low Register): 107EH...

  • Page 265: Power Down Operation

    19. Power down operation Power down operation A96G150 has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. A96G150 provides three kinds of power saving functions such as Main-IDLE mode, Sub-IDLE mode and STOP mode. During one of these three modes,...

  • Page 266: Peripheral Operation In Idle/Stop Mode

    19. Power down operation A96G150 User's manual 19.1 Peripheral operation in IDLE/STOP mode Table 42 shows operation status of each peripheral in IDLE mode and STOP mode. Table 42. Peripheral Operation Status during Power Down Mode Peripheral IDLE mode STOP mode ALL CPU operations are ALL CPU operations are disabled.

  • Page 267: Idle Mode

    A96G150 User's manual 19. Power down operation 19.2 IDLE mode Power control register is set to ‘01h’ to enter into IDLE mode. In IDLE mode, internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally, but CPU stops.

  • Page 268: Stop Mode

    19. Power down operation A96G150 User's manual 19.3 STOP mode Power control register is set to ‘03H’ to enter into STOP mode. In STOP mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock.

  • Page 269: Released Operation Of Stop Mode

    A96G150 User's manual 19. Power down operation 19.4 Released operation of STOP mode After STOP mode is released, operation begins according to content of related interrupt register just before STOP mode starts (refer to Figure 119). If the global interrupt Enable Flag (IE.EA)is set to `1`, the STOP mode is released by a certain interrupt of which interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine.

  • Page 270: Register Map

    19. Power down operation A96G150 User's manual 19.5 Register map Table 43. Power Down Operation Register Map Name Address Direction Default Description PCON Power Control Register 19.6 Register description PCON (Power Control Register): 87H PCON7 – – – PCON3 PCON2...

  • Page 271: Reset

    Accumulator Stack Pointer (SP) Peripheral Clock Control Register Refer to the Peripheral Registers A96G150 has five types of reset sources as shown in the followings: External RESETB  Power ON RESET (POR)  WDT Overflow Reset (In the case of WDTEN = `1`) ...

  • Page 272: Power On Reset

    20. Reset A96G150 User's manual 20.2 Power on reset When rising device power, POR (Power On Reset) has a function to reset a device. If POR is used, it executes the device RESET function instead of the RESET IC or the RESET circuits.

  • Page 273: Figure 123. Configuration Timing When Power-On

    A96G150 User's manual 20. Reset Counting for configure option read start after POR is released. Internal nPOR PAD RESETB “H” LVR_RESETB External reset have not an effect on counter value for config read. BIT (for Configure) 27 28 01 02 03 04 05 …...

  • Page 274: Figure 124. Boot Process Waveform

    20. Reset A96G150 User's manual :VDD Input :Internal OSC ⑥ ④ Reset Release Config Read ② ① ⑦ ③ ⑤ Figure 124. Boot Process Waveform Table 45. Boot Process Description Process Description Remarks ① No Operation 0.7V to 0.9V ...

  • Page 275: External Resetb Input

    A96G150 User's manual 20. Reset 20.3 External resetb input External resetb is input to a Schmitt trigger. If the resetb pin is held with low for at least 50us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After reset state becomes ‘1’, it needs stabilization time with 16ms and after the stable state, the internal...

  • Page 276: Low Voltage Reset Process

    20.4 Low voltage reset process A96G150 has an On-chip brown-out detection circuit (BOD) for monitoring VDD level during operation by comparing it to a fixed trigger level. Trigger level for the BOD can be selected by configuring LVRVS[3:0] bits to be 1.61V, 1.68V, 1.77V, 1.88V, 2.00V, 2.13V, 2.28V, 2.46V, 2.68V, 2.81V, 3.06V, 3.21V, 3.56V, 3.73V, 3.91V, 4.25V.

  • Page 277: Figure 129. Configuration Timing When Lvr Reset

    A96G150 User's manual 20. Reset “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB BIT (for Config) 27 28 02 03 … … BIT (for Reset) 00 01 02 3F 40 … … 01 02 … 250us X 28h = 10ms...

  • Page 278: Lvi Block Diagram

    20. Reset A96G150 User's manual 20.5 LVI block diagram 1.88V 2.00V 2.13V 2.28V 2.46V 2.68V Reference 2.81V Voltage LVI Cir cuit LVIF 3.06V Gen erator 3.21V 3.56V 3.73V 3.91V LVIEN 4.25V LVIREF LVILS[3:0] Figure 130. LVI Block Diagram...

  • Page 279: Register Map

    A96G150 User's manual 20. Reset 20.6 Register map Table 46. Reset Operation Register Map Name Address Direction Default Description RSTFR Reset Flag Register LVRCR Low Voltage Reset Control Register LVICR Low Voltage Indicator Control Register...

  • Page 280: Reset Operation Register Description

    20. Reset A96G150 User's manual 20.7 Reset operation register description RSTFR (Reset Flag Register): E8H – – – PORF EXTRF WDTRF OCDRF LVRF – – – Initial value: 80H Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit.
  • Page 281 A96G150 User's manual 20. Reset LVRCR (Low Voltage Reset Control Register): D8H – – – LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN – – – Initial value: 00H LVRVS[3:0] LVR Voltage Select LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description 1.61V 1.68V 1.77V 1.88V 2.00V 2.13V...
  • Page 282 20. Reset A96G150 User's manual LVICR (Low Voltage Indicator Control Register): 86H – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – Initial value: 00H LVIF Low Voltage Indicator Flag Bit No detection Detection LVIEN LVI Enable/Disable Disable Enable LVIVS[3:0]...

  • Page 283: Memory Programming

    A96G150 User's manual 21. Memory programming Memory programming A96G150 has flash and data EEPROM memory to which a program can be written, erased, and overwritten while mounted on the board. Serial ISP mode is supported. Flash of A96G150 features the followings: Flash Size : 64Kbytes ...

  • Page 284: Register Description

    21. Memory programming A96G150 User's manual 21.1.2 Register description FEMR (Flash Mode Register): 1020H FSEL ESEL ERASE PBUFF OTPE FEEN Initial value: 00H FSEL Select flash memory. Deselect flash memory Select flash memory ESEL Select data EEPROM. Deselect data EEPROM.
  • Page 285 A96G150 User's manual 21. Memory programming FECR (Flash Control Register): 1021H EXIT1 EXIT0 WRITE READ nFERST nPBRST Initial value: 03H Enable flash bulk erase mode Disable bulk erase mode of Flash memory Enable bulk erase mode of Flash memory Enable data EEPROM bulk erase mode...
  • Page 286 21. Memory programming A96G150 User's manual FESR (Flash Status Register): 1022H PEVBSY REMAPSI REMAP- ROMINT WMODE EMODE VMODE Initial value: 80H PEVBSY Operation status flag. It is cleared automatically when operation starts. Operations are program, erase or verification Busy (Operation processing)
  • Page 287 A96G150 User's manual 21. Memory programming FEARM (Flash address middle Register): 1029H ARM7 ARM6 ARM5 ARM4 ARM3 ARM2 ARM1 ARM0 Initial value: 00H ARM[7:0] Flash address middle FEARH (Flash address high Register): 1028H ARH7 ARH6 ARH5 ARH4 ARH3 ARH2 ARH1...

  • Page 288: Figure 131. Read Device Internal Checksum (Full Size)

    21. Memory programming A96G150 User's manual Start OCD mode entry Write(OCD_CODE, 0xF555, 0xAA) Set checksum read mode Write(OCD_CODE, 0xFAAA, 0x55) Write(OCD_CODE, 0xF555, 0xA5) Write(OCD_XDATA, FEMR, 0x81) Set auto verify mode Write(OCD_CODE, FETR, 0x08) Write(OCD_CODE, FECR, 0x07) Busy check (FESR[7]=L) Read 24 - bit Checksum (H, M, L)

  • Page 289: Figure 132. Read Device Internal Checksum (User Define Size)

    A96G150 User's manual 21. Memory programming Start OCD mode entry Write(OCD_CODE, 0xF555, 0xAA) Set checksum read mode Write(OCD_CODE, 0xFAAA, 0x55) Write(OCD_CODE, 0xF555, 0xA5) Write(OCD_XDATA, FEARM,Start Address Upper) Set auto verify mode Write(OCD_XDATA, FEARL,Start Address Lower) Write(OCD_XDATA, FEARM1,End Address Upper) Write(OCD_XDATA, FEARL1,End Address Lower)

  • Page 290: Table 48. Program And Erase Time

    21. Memory programming A96G150 User's manual FETCR (Flash Time control Register): 1023H TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Initial value: 00H TCR[7:0] Flash Time control Program and erase time is controlled by setting FETCR register. Program and erase timer uses 10-bit counter. It increases by one at each RING clock frequency (f =128KHz).

  • Page 291: Memory Map

    A96G150 User's manual 21. Memory programming 21.2 Memory map 21.2.1 Flash memory map Program memory uses 64K bytes of flash memory. It is read by byte and written by byte or page. One page is 64-bytes FFFFh pgm/ers/vfy Code Memory...

  • Page 292: Data Eeprom Memory Map

    21. Memory programming A96G150 User's manual 21.2.2 Data EEPROM memory map Data EEPROM memory uses 2K bytes of flash memory. It is read by byte and written by byte or page. One page is 32-bytes FFFFh pgm/ers/vfy XDATA Memory 37FFh...

  • Page 293: Serial In-System Program (Isp) Mode

    A96G150 User's manual 21. Memory programming 21.3 Serial In-system Program (ISP) mode Serial In-system Program (ISP) uses the interface of debugger which uses two wires. Refer to Chapter 22.Development tools in details about debugger. 21.3.1 Flash operation Configuration (This Configuration is just used for following description) FEMR[4] &...

  • Page 294: Figure 138. The Sequence Of Bulk Erase Of Flash Memory

    21. Memory programming A96G150 User's manual Master Reset Page Buffer Reset Page Buffer Load Configuration Reg.<0> Set Erase Erase Latency (500us) Page Buffer Reset Configuration Reg.<0> clear Reg.<6:5> setting Cell Read Pass/Fail? Figure 138. The Sequence of Bulk Erase of Flash Memory Flash read ①...
  • Page 295 A96G150 User's manual 21. Memory programming Enable program mode ① Enter OCD(=ISP) mode. NOTE1 ② Set ENBDM bit of BCR. ③ Enable debug and Request debug mode. ④ Enter program/erase mode sequence. NOTE2 Write 0xAA to 0xF555. Write 0x55 to 0xFAAA.
  • Page 296 21. Memory programming A96G150 User's manual Flash page erase mode ① Enable program mode. ② Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 ③ Select page buffer. FEMR:1000_1001 ④ Write ‘h00 to page buffer. (Data value is not important.) ⑤ Set erase mode. FEMR:1001_0001 ⑥...
  • Page 297 A96G150 User's manual 21. Memory programming Flash OTP area read mode ① Enter OCD (=ISP) mode. ② Set ENBDM bit of BCR. ③ Enable debug and Request debug mode. ④ Select OTP area. FEMR:1000_0101 ⑤ Read data from Flash. Flash OTP area write mode ①...
  • Page 298 21. Memory programming A96G150 User's manual Flash OTP area erase mode ① Enable program mode. ② Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 ③ Select page buffer. FEMR:1000_1001 ④ Write ‘h00 to page buffer. (Data value is not important.) ⑤ Set erase mode and select OTP area. FEMR:1001_0101 ⑥...

  • Page 299: Table 49. Operation Mode

    A96G150 User's manual 21. Memory programming Flash page buffer read ① Enable program mode. ② Select page buffer. FEMR:1000_1001 ③ Read data from Flash. Summary of flash program/erase mode Table 49. Operation Mode Operation mode Description Flash read Read cell by byte.

  • Page 300: Data Eeprom Operation

    21. Memory programming A96G150 User's manual 21.3.2 Data EEPROM operation Program and erase operation of Data EEPROM are executed by direct and indirect address mode. Direct address mode uses external data area of 8051. Indirect address mode uses address register of SFR area.
  • Page 301 A96G150 User's manual 21. Memory programming EEPROM write mode ① Enable program mode. ② Reset page buffer. FEMR: 0100_0001 FECR:0000_0010 ③ Select page buffer. FEMR:0100_1001 ④ Write data to page buffer.(Address automatically increases by twin.) ⑤ Set write mode. FEMR:0110_0001 ⑥...
  • Page 302 21. Memory programming A96G150 User's manual EEPROM bulk erase mode ① Enable program mode. ② Reset page buffer. FEMR: 0100_0001 FECR:0000_0010 ③ Select page buffer. FEMR:0100_1001 ④ Write ‘h00 to page buffer. (Data value is not important.) ⑤ Set erase mode. FEMR:0101_0001.

  • Page 303: Mode Entrance Method Of Isp Mode

    A96G150 User's manual 21. Memory programming 21.4 Mode entrance method of ISP mode 21.4.1 Mode entrance method for ISP Table 50. Mode Entrance Method for ISP TARGET MODE DSDA DSCL DSDA OCD(ISP) ‘hC ‘hC ‘hC Release from worst 1.7V Power on reset...

  • Page 304: Security

    21.5 Security A96G150 provides Lock bits which can be left un-programmed (“0”) or can be programmed (“1”) to obtain the additional features listed in Table 51. Security Policy using Lock Bits. The Lock bit can only be erased to “0” with the bulk erase command and a value of more than 0x40 at FETCR.

  • Page 305: Configure Option

    Enable Protection RSTS Select RESETB pin Disable RESETB pin(P52) Enable RESETB pin NOTE: Code write protection and Vector area protection are disabled at OCD Mode. CONFIGURE OPTION 1: ROM Address 0000H (A96G150 64K Series) – – – – PAEN PASS2...
  • Page 306 21. Memory programming A96G150 User's manual CONFIGURE OPTION 1: ROM Address 0000H (A96G158 32K Series) – – – – PAEN PASS2 PASS1 PASS0 Initial value: 00H PAEN Enable Specific Area Write Protection Disable Protection Enable Protection PASS [2:0] Select Specific Area for Write Protection NOTE: When PAEN = ‘1’, it is applied.

  • Page 307: Development Tools

    ABOV semiconductor does not provide any compiler for A96G150. It is recommended to consult a compiler provider. Since A96G150 has Mentor 8051 as its core, and ROM is smaller than 64Kbytes in size, a developer can use any standard 8051 compilers of other providers.

  • Page 308: Core And Debug Tool Information

    NOTES: A96G150 has 96 series core and OCD 1 interface. Also, A96G150 can be operated with OCD II dongle because OCD II dongle includes all of OCD1 function. 95 series core is the old version of 96 series core. 22.2.1 Feature of 94/96/97 Series core ABOV’s microcontroller contains an M8051/CM8051 core that was made by improving the 8051.

  • Page 309: Table 54. Feature Comparison Chart By Series And Cores

    NOTES: A96G150 has 96 series core and OCD 1 interface. Also, A96G150 can be operated with OCD II dongle because OCD II dongle includes all of OCD1 function. EA means that All Interrupt Enable bit or Disable bit (Standard 8051).

  • Page 310: Ocd Type Of 94/96/97 Series Core

    22. Development tools A96G150 User's manual 22.2.2 OCD type of 94/96/97 Series core 96-series core uses OCD 1 for a debug interface, while the cores of 94-series and 97-series use OCD 2 for debug interfaces. The OCD 1 and OCD 2 use the same method in Hardware, but protocols are not compatible each other.

  • Page 311: Interrupt Priority Of 94/96/97 Series Core

    A96G150 User's manual 22. Development tools 22.2.3 Interrupt priority of 94/96/97 Series core In the M8051, users can set interrupt priorities by group. Thus, the 96-series microcontroller with the basic M8051 core only supports interrupt priorities in group units. In the 94-series or 97-series microcontroller, users can set interrupt priorities to have more functions than the existing functions, and set individual priority over each interrupt source.

  • Page 312: Extended Stack Pointer Of 94/96/97 Series Core

    22. Development tools A96G150 User's manual 22.2.4 Extended Stack Pointer of 94/96/97 Series core M8051 uses IRAM area for Stack Pointer. However, 94-series and 97-series microcontrollers use not only IRAM area but also XRAM area for Stack Pointer by configuring additional registers.

  • Page 313: Ocd (On-Chip Debugger) Emulator And Debugger

    A96G150 User's manual 22. Development tools 22.3 OCD (On-chip debugger) emulator and debugger Microcontroller series that uses an 8051 core has an OCD (On-Chip Debugger), a debug emulation block. The OCD is connected to a target microcontroller using two lines such as DSCL and DSDA.

  • Page 314: Figure 141. Ocd 1 And Ocd 2 Connector Pin Diagram

    ― Logic power supply pin. The OCD emulator supports ABOV’s 8051 series MCU emulation. The OCD uses two wires interfacing between PC and MCU, which is attached to user’s system. The OCD can read or change the value of MCU’s internal memory and I/O peripherals. In addition, the OCD controls MCU’s internal debugging logic.

  • Page 315: On-Chip Debug System

    A96G150 supports On-chip debug (OCD) system. We recommend developing and debugging program with A96G1 series. On-chip debug system of A96G150 can be used for programming the non-volatile memories and on-chip debugging. Detail descriptions for programming via the OCD interface can be found in this section.

  • Page 316: Entering Debug Mode

    22. Development tools A96G150 User's manual Figure 143 shows a block diagram of the OCD interface and the On-chip Debug system. Figure 143. On-chip Debugging System in Block Diagram 22.3.2 Entering debug mode While communicating through the OCD, users can enter the microcontroller into DEBUG mode by applying power to it.

  • Page 317: Two-Wire Communication Protocol

    A96G150 User's manual 22. Development tools 22.3.3 Two-wire communication protocol For the OCD interface, the semi-duplex communication protocol is used through separate two wires such as DSCL and DSDA. The DSCL is a serial clock signal and the DSDA is a bi-directional serial address and data.

  • Page 318: Figure 145. 10-Bit Transmission Packet

    22. Development tools A96G150 User's manual Figure 145. 10-bit Transmission Packet Packet transmission timing Figure 146 shows a timing diagram of a packet transmission using the OCD communication protocol. The start bit means a start of a packet and is valid when DSDA falls from ‘H’ to ‘L’ while External Host maintains DSCL to ‘H’.

  • Page 319: Figure 147. Bit Transfer On Serial Bus

    A96G150 User's manual 22. Development tools Figure 147 shows a timing diagram of each bit based on the state of DSCL clock and DSDA data. Similar to I2C signal, DSDA data is allowed to change when DSCL is ‘L’. If the data changes when DSCL is ‘H’, the change means ‘START’...

  • Page 320: Figure 149. Acknowledge On Serial Bus

    22. Development tools A96G150 User's manual As shown in Figure 149, when transferring data, a receiver outputs DSDA to ‘L’ to inform the normal reception of data. If a receiver outputs DSDA to ‘H’, it means error reception of data.

  • Page 321: Programmers

    22. Development tools 22.4 Programmers 22.4.1 E-PGM+ E-PGM+ USB is a single programmer. A user can program A96G150 directly using the E-PGM+. 8 10 Figure 151. E-PGM+ (Single Writer) and Pinouts 22.4.2 OCD emulator OCD emulator allows a user to write code on the device too, since OCD debugger supports ISP (In...

  • Page 322: Gang Programmer

    22. Development tools A96G150 User's manual 22.4.3 Gang programmer E-Gang4 and E-Gang6 allows a user to program on multiple devices at a time. They run not only in PC controlled mode but also in standalone mode without PC control. USB interface is available and it is easy to connect to the handler.

  • Page 323: Flash Programming

    22.5 Flash programming Program memory of A96G150 is a flash type. This flash ROM is accessed through four pins such as DSCL, DSDA, VDD and VSS in serial data format. For more information about flash memory programming, please refer to Chapter 21. Memory programming Table 61 introduces each pin and corresponding I/O status.

  • Page 324: Connection Of Transmission

    22. Development tools A96G150 User's manual 22.6 Connection of transmission OCD’s two-wire communication interface uses Open-Drain Method (Wire-AND Bi-Directional I/O). Normally, it is recommended to place a resister greater than 4.7kΩ for DSCL and DSDA respectively. The capacitive load is recommended to be less than 100pF. Outside these ranges, because the communication may not be accomplished, the connection to Debug mode is not guaranteed.

  • Page 325: Circuit Design Guide

    A96G150 User's manual 22. Development tools 22.7 Circuit design guide When programming flash memory, the programming tool needs 4 signal lines, DSCL, DSDA, VDD, and VSS. If a user designs a PCB circuit, the user should consider the usage of these 4 signal lines for the on-board programming.

  • Page 326: Figure 154. Pcb Design Guide For On-Board Programming

    22. Development tools A96G150 User's manual Figure 154 shows an example circuit where the OCD pins (DSCL and DSDA) are shared with other functions. They are required to be connected when debugging or ISP (In System Program) is executed. Normally, the OCD pins are connected to outside to execute the predefined functions. Even when they are connected for debugging or ISP directly, the OCD pins are shared with other functions by using resistors as shown in Figure 154.

  • Page 327: Appendix

    A96G150 User's manual Appendix Appendix Instruction table Instructions are either1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
  • Page 328 Appendix A96G150 User's manual Table 62. Instruction Table (continued) LOGICAL Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data...
  • Page 329 A96G150 User's manual Appendix Table 62. Instruction Table (continued) DATA TRANSFER Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7 MOV A,#data...
  • Page 330 Appendix A96G150 User's manual Table 62. Instruction Table (continued) BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit...
  • Page 331 A96G150 User's manual Appendix Table 62. Instruction Table (continued) BRANCHING Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...
  • Page 332 Appendix A96G150 User's manual Table 62. Instruction Table (continued) MISCELLANEOUS Mnemonic Description Bytes Cycles Hex code No operation ADDITIONAL INSTRUCTIONS (selected through EO[7:4]) Mnemonic Description Bytes Cycles Hex code MOVC M8051W/M8051EW-specific instruction @(DPTR++),A supporting software download into program memory TRAP...

  • Page 333: Revision History

    A96G150 User's manual Revision history Revision history Revision Date Notes 1.00 2022. 06. 22 First creation...
  • Page 334 ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders.

Table of Contents