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Abov A96G140 User Manual

Cmos single chip 8-bit mcu with 12-bit adc general purpose microcontroller
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Introduction
This user's manual targets application developers who use A96G140/A96G148 for their specific
needs. It provides complete information of how to use A96G140/A96G148 device. Standard functions
and blocks including corresponding register information of A96G140/A96G148 are introduced in each
chapter, while instruction set is in Appendix.
A96G140/A96G148 is based on M8051 core, and provides standard features of 8051 such as 8-bit
ALU, PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit data
bus and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost effective solutions:
64Kbytes of FLASH, 256bytes of IRAM, 2304bytes of XRAM, general purpose I/O, basic interval timer,
watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 16-bit PWM output,
watch timer, buzzer driving port, USI, 12-bit A/D converter, on-chip POR, LVR, LVI, on-chip oscillator
and clock circuitry.
As a field proven best seller, A96G140/A96G148 has been sold more than 3 billion units up to now,
and introduces rich features such as excellent noise immunity, code optimization, cost effectiveness,
and so on.
Reference document
A96G140/A96G148 programming tools and manuals released by ABOV: They are available
at ABOV website, www.abov.co.kr/e_main.php.
SDK-51 User's guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel's 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentor website:
CMOS Single Chip 8-bit MCU with 12-bit ADC
https://www.mentor.com/products/ip/peripheral/microcontroller/
Global Top Smart MCU Innovator
www.abov.co.kr
A96G140/A96G148
General Purpose Microcontroller
User's Manual
Version 1.13

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Summary of Contents for Abov A96G140

  • Page 1 USI, 12-bit A/D converter, on-chip POR, LVR, LVI, on-chip oscillator and clock circuitry. As a field proven best seller, A96G140/A96G148 has been sold more than 3 billion units up to now, and introduces rich features such as excellent noise immunity, code optimization, cost effectiveness, and so on.

  • Page 2: Table Of Contents

    Contents A96G140/A96G148 User’s manual Contents Description ..............................21 Device overview ......................... 21 A96G140/A96G148 block diagram ..................22 Pinouts and pin description ........................24 Pinouts ............................24 Pin description ..........................28 Port structures .............................. 33 Memory organization ..........................35 Program memory ........................35 Data memory ..........................
  • Page 3 A96G140/A96G148 User’s manual Contents 5.2.1 P0 port description ........................51 5.2.2 Register description for P0 ....................51 P1 port............................54 5.3.1 P1 port description ........................54 5.3.2 Register description for P1 ....................54 P2 port............................58 5.4.1 P2 port description ........................58 5.4.2...
  • Page 4 Contents A96G140/A96G148 User’s manual Saving/restore general purpose registers ..............75 6.10 Interrupt timing .......................... 76 6.11 Interrupt register overview ....................76 6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) ............76 6.11.2 Interrupt Priority Register (IP and IP1) ................76 6.11.3...
  • Page 5 A96G140/A96G148 User’s manual Contents Timer 0/1/2/3/4/5 ........................96 11.1 Timer 0 ............................96 11.1.1 8-bit timer/counter mode ..................... 96 11.1.2 8-bit PWM mode ........................98 11.1.3 8-bit capture mode ........................ 100 11.1.4 Timer 0 block diagram ......................102 11.1.5 Register map ..........................102 11.1.6...
  • Page 6 Contents A96G140/A96G148 User’s manual 11.4.4 16-bit timer 3 block diagram ..................... 130 11.4.5 Register map ..........................130 11.4.6 Register description ........................ 130 11.5 Timer 4 ............................133 11.5.1 16-bit timer/counter mode ....................134 11.5.2 16-bit capture mode ......................136 11.5.3 16-bit PPG mode ........................
  • Page 7 A96G140/A96G148 User’s manual Contents 13.5 Register description ........................ 157 USI (USART + SPI + I2C) ...................... 160 14.1 USIn UART mode ........................160 14.2 USIn UART block diagram ....................161 14.3 USIn clock generation ......................162 14.4 USIn external clock (SCKn) ....................163 14.5...
  • Page 8 Contents A96G140/A96G148 User’s manual 14.16 USIn I2C data transfer ......................174 14.17 USIn I2C acknowledge ......................174 14.18 USIn I2C synchronization/ arbitration ................175 14.19 USIn I2C operation ......................... 176 14.19.1 USIn I2C master transmitter ..................177 14.19.2 USIn I2C master receiver ..................... 179 14.19.3...
  • Page 9 A96G140/A96G148 User’s manual Contents 15.8.2 Receiver flag and interrupt ....................202 15.8.3 Parity checker ..........................202 15.8.4 Disabling receiver ........................203 15.8.5 Asynchronous data reception .................... 203 15.9 SPI mode ............................. 204 15.9.1 SPI clock formats and timing ..................... 205 15.10...
  • Page 10 Contents A96G140/A96G148 User’s manual Memory programming ......................234 18.1 Flash control and status registers ..................234 18.1.1 Register map ..........................234 18.1.2 Register description ........................ 234 18.2 Memory map ..........................241 18.2.1 Flash memory map ......................... 241 18.3 Serial in-system program mode ..................242 18.3.1...
  • Page 11 A96G140/A96G148 User’s manual Contents 19.14 Data retention voltage in stop mode ................261 19.15 Internal flash ROM characteristics ................... 262 19.16 Input/output capacitance..................... 263 19.17 Main clock oscillator characteristics ................263 19.18 Sub-clock oscillator characteristics .................. 264 19.19 Main oscillation stabilization characteristics ............... 265 19.20...
  • Page 12 Contents A96G140/A96G148 User’s manual 21.4 32 SOP package information ..................... 285 21.5 28 SOP package information ..................... 287 21.6 28 TSSOP package information ..................289 Ordering information ......................291 Appendix ................................293 Instruction table ............................. 293 Revision history ..............................299 Worldwide Distributors and Sales Offices ....................
  • Page 13 List of figures List of figures FIGURE 1. A96G140/A96G148 BLOCK DIAGRAM ...................... 23 FIGURE 2. A96G140/A96G148 48LQFP-0707 PIN ASSIGNMENT ............... 24 FIGURE 3. A96G140/A96G148 44MQFP-1010 PIN ASSIGNMENT ..............25 FIGURE 4. A96G140/A96G148 32LQFP PIN ASSIGNMENT ................... 26 FIGURE 5. A96G140/A96G148 32SOP PIN ASSIGNMENT ..................27 FIGURE 6.
  • Page 14 List of figures A96G140/A96G148 User’s manual FIGURE 35. EXPRESS TIMER OVERFLOW IN CAPTURE MODE ................101 FIGURE 36. 8-BIT TIMER 0 BLOCK DIAGRAM......................102 FIGURE 37. 16-BIT TIMER/COUNTER MODE OF TIMER 1 ................... 106 FIGURE 38. 16-BIT TIMER/COUNTER MODE OPERATION EXAMPLE ............. 106 FIGURE 39.
  • Page 15 A96G140/A96G148 User’s manual List of figures FIGURE 74. 16-BIT PPG MODE OPERATION EXAMPLE ..................148 FIGURE 75. 16-BIT TIMER 5 BLOCK DIAGRAM ......................149 FIGURE 76. BUZZER DRIVER BLOCK DIAGRAM ......................152 FIGURE 77. 12-BIT ADC BLOCK DIAGRAM ......................... 155 FIGURE 78.
  • Page 16 List of figures A96G140/A96G148 User’s manual FIGURE 113. RESET BLOCK DIAGRAM .......................... 224 FIGURE 114. FAST VDD RISING TIME..........................225 FIGURE 115. INTERNAL RESET RELEASE TIMING ON POWER-UP ..............225 FIGURE 116. CONFIGURATION TIMING WHEN POWER-ON ................226 FIGURE 117. BOOT PROCESS WAVEFORM ......................... 226 FIGURE 118.
  • Page 17 FIGURE 166. 32 LQFP PACKAGE OUTLINE ........................283 FIGURE 167. 32 SOP PACKAGE OUTLINE ........................285 FIGURE 168. 28 SOP PACKAGE OUTLINE ........................287 FIGURE 169. 28 TSSOP PACKAGE OUTLINE ....................... 289 FIGURE 170. A96G140/A96G148 DEVICE NUMBERING NOMENCLATURE ..........292...
  • Page 18 List of tables A96G140/A96G148 User’s manual List of tables TABLE 1. A96G140/A96G148 DEVICE FEATURES AND PERIPHERAL COUNTS ..........21 TABLE 2. NORMAL PIN DESCRIPTION ..........................28 TABLE 3. . SFR MAP SUMMARY ............................39 TABLE 4. XSFR MAP SUMMARY ............................40 TABLE 5.
  • Page 19 A96G140/A96G148 User’s manual List of tables TABLE 35. CPOL FUNCTIONALITY ........................... 205 TABLE 36. EXAMPLE CONDITION OF RTO ........................208 TABLE 37. USART2 REGISTER MAP ..........................209 TABLE 38. EXAMPLES OF UBAUD SETTINGS FOR COMMONLY USED OSCILLATOR FREQUENCIES ....................................... 216 TABLE 39.
  • Page 20 TABLE 74. 32 SOP PACKAGE MECHANICAL DATA ....................286 TABLE 75. 28 SOP PACKAGE MECHANICAL DATA ....................288 TABLE 76. 28 TSSOP PACKAGE MECHANICAL DATA ..................... 290 TABLE 77. A96G140/A96G148 DEVICE ORDERING INFORMATION ..............291 TABLE 78. INSTRUCTION TABLE ............................293...

  • Page 21: Description

    A96G140/A96G148 User’s manual 1. Description 1 Description A96G140/A96G148 is an advanced CMOS 8-bit microcontroller with 64Kbytes of FLASH. This is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. Device overview In this section, features of A96G140/A96G148 and peripheral counts are introduced.

  • Page 22: A96G140/A96G148 Block Diagram

    -40℃ to +85℃ Pb-free packages  48 LQFP 0707  Package 44 MQFP 1010  32 LQFP, 32 SOP  28 SOP, 28 TSSOP  A96G140/A96G148 block diagram In this section, A96G140/A96G148 device with peripherals are described in a block diagram.

  • Page 23: Figure 1. A96G140/A96G148 Block Diagram

    32.768kHz, Crystal OSC Timer / Counter 1 channel, 8-bit 5 channels, 16-bit Buzzer 1 channel, 8-bit 1-ch 8-bit (T0) UART 5-ch 16-bit (T1/T2/T3/T4/T5) 3 channels, 8-bit 16 Input channels, 12-bit 3 channels, 8-bit 2 channels, 8-bit Figure 1. A96G140/A96G148 Block Diagram...

  • Page 24: Pinouts And Pin Description

    2. Pinouts and pin description A96G140/A96G148 User’s manual 2 Pinouts and pin description In this chapter, A96G140/A96G148 device pinouts and pin descriptions are introduced. Pinouts P55/RESETB P04/AN2/EINT2/(T3O)/(PWM3O) P40/RXD0/SCL0/MISO0 P41/TXD0/SDA0/MOSI0 P05/AN3/EINT3/(EC3) P06/AN4/EINT4/T5O/PWM5O P42/SCK0 A96G140CL P43/SS0 P07/AN5/EINT5 P37/LED0 P17/AN6/EINT6/SS2 A96G148CL P16/AN7/EINT7/XCK P36/LED1...

  • Page 25: Figure 3. A96G140/A96G148 44Mqfp-1010 Pin Assignment

    The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P44-P47 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 44-pin package is used. Figure 3. A96G140/A96G148 44MQFP-1010 Pin Assignment...

  • Page 26: Figure 4. A96G140/A96G148 32Lqfp Pin Assignment

    The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P14-P17, P23-P25, P34-P37 and P43-P47 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 32-pin package is used. Figure 4. A96G140/A96G148 32LQFP Pin Assignment...

  • Page 27: Figure 5. A96G140/A96G148 32Sop Pin Assignment

    The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P14-P17, P23-P25, P34-P37 and P43-P47 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 32-pin package is used. Figure 5. A96G140/A96G148 32SOP Pin Assignment P50/XOUT P00/EC3/DSDA/(RXD2)

  • Page 28: Pin Description

    2. Pinouts and pin description A96G140/A96G148 User’s manual Pin description Table 2. Normal Pin Description Function Shared with Name RESET Port 0 is a bit-programmable I/O port Input EC3/DSDA/(RXD2) which can be configured as a Schmitt- T3O/PWM3O/DSCL/(TXD2) trigger input, a push-pull output, or an AN0/AVREF/EINT0/T4O/PWM4O open-drain output.
  • Page 29 A96G140/A96G148 User’s manual 2. Pinouts and pin description Table 2. Normal Pin Description (continued) Function Shared with Name RESET Port 4 is a bit-programmable I/O port which Input RXD0/SCL0/MISO0 can be configured as an input, a push-pull TXD0/SDA0/MOSI0 output, or an open-drain output.
  • Page 30 2. Pinouts and pin description A96G140/A96G148 User’s manual Table 2. Normal Pin Description (continued) Function Shared with Name RESET Timer 3 interval output Input P01/DSCL P04/AN2/EINT2/PWM3O Timer 4 interval output Input P02/AN0/AVREF/EINT0/PWM4O Timer 5 interval output Input P06/AN4/EINT4/PWM5O Timer 0 PWM output...
  • Page 31 A96G140/A96G148 User’s manual 2. Pinouts and pin description Table 2. Normal Pin Description (continued) Function Shared with Name RESET USART2 data input RXD2 Input P00/EC3/DSDA P15/AN8/MISO2 USART2 slave selection input/output Input P17/AN6/EINT6 USART2 external clock input/output Input P16/AN7/EINT7 A/D converter reference voltage...
  • Page 32 2. Pinouts and pin description A96G140/A96G148 User’s manual Table 2. Normal Pin Description (continued) Function Shared with Name RESET Sub oscillator pins SXIN Input P53/T0O/PWM0O SXOUT P54/EINT10 Power input pins VDD, ― ― ― NOTES: The P14–P17, P23–P25, P34–P37, and P43-P47 are not in the 32-pin package.

  • Page 33: Port Structures

    A96G140/A96G148 User’s manual 3. Port structure 3 Port structures In this chapter, two port structures are introduced in figures 1 and 2 regarding general purpose I/O port and external interrupt I/O port respectively. Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V)

  • Page 34: Figure 8. External Interrupt I/O Port

    3. Port structure A96G140/A96G148 User’s manual LevelShift (1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE DIRECTION REGISTER SUB-FUNC DIRECTION R(400Ω) EXTERNAL INTERRUPT POLARITY INTERRUPT ENABLE EDGE FLAG CLEAR PORTx INPUT...

  • Page 35: Memory Organization

    External data memory (XRAM) is 2304bytes. Program memory A 16-bit program counter is capable of addressing up to 64Kbytes, and A96G140/A96G148 has just 64Kbytes program memory space. Figure 9 shows a map of the lower part of the program memory.

  • Page 36: Data Memory

    4. Memory organization A96G140/A96G148 User’s manual FFFFH 64KB FLASH 7FFFH 32KB FLASH 0000H NOTE: The 64Kbytes includes the Interrupt Vector Region. Figure 9. Program Memory Map Data memory Internal data memory space is divided into three blocks, which are generally referred to as lower 128bytes, upper 128bytes, and SFR space.

  • Page 37: Figure 10. Data Memory Map

    A96G140/A96G148 User’s manual 4. Memory organization All of the bytes in the lower 128bytes can be accessed by either direct or indirect addressing. The upper 128bytes of RAM can only be accessed by indirect addressing. These spaces are used for data RAM and stack.

  • Page 38: External Data Memory

    Register Bank 0 8bytes (8bytes) Figure 11. Lower 128bytes of RAM External data memory A96G140/A96G148 has 2304bytes of XRAM and XSFR. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit.

  • Page 39: Sfr Map

    A96G140/A96G148 User’s manual 4. Memory organization 107FH Extended Special Function Registers 128bytes (Indirect Addressing) 1000H Not used 08FFH External RAM 2304bytes (Indirect Addressing) 0000H Figure 12. XDATA Memory Area SFR map 4.4.1 SFR map summary Table 3. . SFR Map Summary ―...

  • Page 40: Table 4. Xsfr Map Summary

    4. Memory organization A96G140/A96G148 User’s manual Table 3. SFR Map Summary (continued) ― Reserved M8051 compatible 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 0B8H P2IO T1CRL T1CRH T1ADRL T1ADRH T1BDRL T1BDRH 0B0H P1IO T0CR T0CNT T0DR/ – – –...

  • Page 41: Sfr Map

    A96G140/A96G148 User’s manual 4. Memory organization 4.4.2 SFR map Table 5. SFR Map Address Function Symbol @Reset P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1...
  • Page 42 4. Memory organization A96G140/A96G148 User’s manual Table 5. SFR Map (continued) Address Function Symbol @Reset P4 Data Register P0 Direction Register P0IO Extended Operation Register – – – – P4 Pull-up Resistor Selection Register P4PU External Interrupt Polarity 0 Low Register...
  • Page 43 A96G140/A96G148 User’s manual 4. Memory organization Table 5. SFR Map (continued) Address Function Symbol @Reset External Interrupt Flag 0 Register EIFLAG0 P3 Direction Register P3IO Timer 2 Control Low Register T2CRL – – Timer 2 Control High Register T2CRH –...
  • Page 44 4. Memory organization A96G140/A96G148 User’s manual Table 5. SFR Map (continued) Address Function Symbol @Reset Accumulator Register USI0 Status Register 1 USI0ST1 – USI0 Status Register 2 USI0ST2 USI0 Baud Rate Generation Register USI0BD USI0 SDA Hold Time Register USI0SHDR...

  • Page 45: Table 6. Xsfr Map

    A96G140/A96G148 User’s manual 4. Memory organization Table 6. XSFR Map Address Function Symbol @Reset 1000H Timer 3 Control High Register T3CRH – – – – 1001H Timer 3 Control Low Register T3CRL – – 1002H Timer 3 A Data High Register...

  • Page 46: Compiler Compatible Sfr

    4. Memory organization A96G140/A96G148 User’s manual 4.4.3 Compiler compatible SFR ACC (Accumulator Register): E0H Initial value: 00H Accumulator B (B Register): F0H Initial value: 00H B Register SP (Stack Pointer): 81H Initial value: 07H Stack Pointer DPL (Data Pointer Register Low): 82H...
  • Page 47 A96G140/A96G148 User’s manual 4. Memory organization DPH1 (Data Pointer Register High 1): 85H DPH1 Initial value: 00H DPH1 Data Pointer High 1 PSW (Program Status Word Register): D0H Initial value: 00H Carry Flag Auxiliary Carry Flag General Purpose User-Definable Flag...

  • Page 48: 5 I/O Ports

    5. I/O ports A96G140/A96G148 User’s manual 5 I/O ports A96G140/A96G148 has groups of I/O ports (P0 ~ P5). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements.
  • Page 49 A96G140/A96G148 User’s manual 5. I/O ports...

  • Page 50: Register Map

    5. I/O ports A96G140/A96G148 User’s manual 5.1.7 Register Map Table 7. Port Register Map Name Address Direction Default Description P0 Data Register P0IO P0 Direction Register P0PU P0 Pull-up Resistor Selection Register P0OD P0 Open-drain Selection Register P0DB P0 De-bounce Enable Register...

  • Page 51: P0 Port

    A96G140/A96G148 User’s manual 5. I/O ports P0 port 5.2.1 P0 port description P0 is an 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open- drain selection register (P0OD).
  • Page 52 5. I/O ports A96G140/A96G148 User’s manual P0OD (P0 Open-drain Selection Register): 91H P07OD P06OD P05OD P04OD P03OD P02OD P01OD P00OD Initial value: 00H P0OD[7:0] Configure Open-drain of P0 Port Push-pull output Open-drain output P0DB (P0 De-bounce Enable Register): DEH DBCLK1...
  • Page 53 A96G140/A96G148 User’s manual 5. I/O ports P0FSRH (Port 0 Function Selection High Register): D3H P0FSRH7 P0FSRH6 P0FSRH5 P0FSRH4 P0FSRH3 P0FSRH2 P0FSRH1 P0FSRH0 Initial value: 00H P0FSRH[7:6] P07 Function Select P0FSRH7 P0FSRH6 Description I/O Port (EINT5 function possible when input) reserved...

  • Page 54: P1 Port

    5. I/O ports A96G140/A96G148 User’s manual P0FSRL (Port 0 Function Selection Low Register): D2H P0FSRL7 P0FSRL6 P0FSRL5 P0FSRL4 P0FSRL3 P0FSRL2 P0FSRL1 P0FSRL0 Initial value: 00H P0FSRL[7:6] P03 Function Select P0FSRL7 P0FSRL6 Description I/O Port(EINT1 function possible when input) reserved AN1 Function...
  • Page 55 A96G140/A96G148 User’s manual 5. I/O ports P1 (P1 Data Register): 88H Initial value: 00H P1[7:0] I/O Data P1IO (P1 Direction Register): B1H P17IO P16IO P15IO P14IO P13IO P12IO P11IO P10IO Initial value: 00H P1IO[7:0] P1 Data I/O Direction Input Output...
  • Page 56 5. I/O ports A96G140/A96G148 User’s manual P15DB (P1/P5 De-bounce Enable Register): DFH – – P54DB P52DB P17DB P16DB P12DB P11DB – – Initial value: 00H P54DB Configure De-bounce of P54 Port Disable Enable P52DB Configure De-bounce of P52 Port Disable...
  • Page 57 A96G140/A96G148 User’s manual 5. I/O ports P1FSRH (Port 1 Function Selection High Register): D5H P1FSRH7 P1FSRH6 P1FSRH5 P1FSRH4 P1FSRH3 P1FSRH2 P1FSRH1 P1FSRH0 Initial value: 00H P1FSRH[7:6] P17 Function Select P1FSRH7 P1FSRH6 Description I/O Port(EINT6 function possible when input) reserved AN6 Function...

  • Page 58: P2 Port

    5. I/O ports A96G140/A96G148 User’s manual P1FSRL (Port 1 Function Selection Low Register): D4H P1FSRL7 P1FSRL6 P1FSRL5 P1FSRL4 P1FSRL3 P1FSRL2 P1FSRL1 P1FSRL0 Initial value: 00H P1FSRL[7:6] P13 Function Select P1FSRL7 P1FSRL6 Description I/O Port(EC1 function possible when input) reserved AN10 Function...
  • Page 59 A96G140/A96G148 User’s manual 5. I/O ports P2 (P2 Data Register): 90H Initial value: 00H P2[7:0] I/O Data P2IO (P2 Direction Register): B9H P27IO P26IO P25IO P24IO P23IO P22IO P21IO P20IO Initial value: 00H P2IO[7:0] P2 Data I/O Direction Input Output...

  • Page 60: P3 Port

    5. I/O ports A96G140/A96G148 User’s manual P2FSR (Port 2 Function Selection Register): D6H P2FSR4 P2FSR3 P2FSR2 P2FSR1 P2FSR0 Initial value: 00H P2FSR4 P22 Function Select I/O Port SS1 Function P2FSR[3:2] P21 Function Select P2FSR3 P2FSR2 Description I/O Port reserved AN15 Function...
  • Page 61 A96G140/A96G148 User’s manual 5. I/O ports P3IO (P3 Direction Register): C1H P37IO P36IO P35IO P34IO P33IO P32IO P31IO P30IO Initial value: 00H P3IO[7:0] P3 Data I/O Direction Input Output P3PU (P3 Pull-up Resistor Selection Register): AFH P37PU P36PU P35PU P34PU...

  • Page 62: P4 Port

    5. I/O ports A96G140/A96G148 User’s manual P3FSR (Port 3 Function Selection Register): EEH P3FSR7 P3FSR6 P3FSR5 P3FSR4 P3FSR3 P3FSR2 P3FSR1 P3FSR0 Initial value: 00H P3FSR7 P37 Function select I/O Port LED0 Function P3FSR6 P36 Function Select I/O Port LED1 Function...
  • Page 63 A96G140/A96G148 User’s manual 5. I/O ports P4 (P4 Data Register): A0H Initial value: 00H P4[7:0] I/O Data P4IO (P4 Direction Register): C9H P47IO P46IO P45IO P44IO P43IO P42IO P41IO P40IO Initial value: 00H P4IO[7:0] P4 Data I/O Direction Input Output...

  • Page 64: P5 Port

    5. I/O ports A96G140/A96G148 User’s manual P4FSR (Port 4 Function Selection Register): EFH P4FSR3 P4FSR2 P4FSR1 P4FSR0 Initial value: 00H P4FSR3 P43 Function Select I/O Port SS0 Function P4FSR2 P42 Function Select I/O Port SCK0 Function P4FSR1 P41 Function Select...
  • Page 65 A96G140/A96G148 User’s manual 5. I/O ports P5PU (P5 Pull-up Resistor Selection Register): 95H – – P55PU P54PU P53PU P52PU P51PU P50PU – – Initial value: 00H P5PU[5:0] Configure Pull-up Resistor of P5 Port Disable Enable P5FSR (Port 5 Function Selection Register): FFH...

  • Page 66: Interrupt Controller

    6. Interrupt controller A96G140/A96G148 User’s manual 6 Interrupt controller A96G140/A96G148 supports up to 23 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. In addition, they have four levels of priority assigned to themselves.

  • Page 67: External Interrupt

    A96G140/A96G148 User’s manual 6. Interrupt controller Interrupt Highest Lowest Group 0 (Bit0) Interrupt 0 Interrupt 6 Interrupt 12 Interrupt 18 Highest 1 (Bit1) Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 2 (Bit2) Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20...

  • Page 68: Block Diagram

    6. Interrupt controller A96G140/A96G148 User’s manual EINT8 Pin FLAG8 INT6 Interrupt EINT10 Pin FLAG10 INT0 Interrupt EINT11 Pin FLAG11 INT1 Interrupt EINT12 Pin FLAG12 INT11 Interrupt EIPOL1 FLAG0 EINT0 Pin EINT1 Pin FLAG1 EINT2 Pin FLAG2 FLAG3 EINT3 Pin INT5 Interrupt...

  • Page 69: Figure 15. Interrupt Controller Block Diagram

    A96G140/A96G148 User’s manual 6. Interrupt controller EIPOL1 EI FLAG1.1 EINT10 FLAG10 EI FLAG1.2 Priority High EINT11 FLAG11 USI1 I2C I2C1IFR USI1 Rx USI1 Tx EIPOL0H/L EI FLAG0.0 EINT0 FLAG0 EI FLAG0.1 EINT1 FLAG1 EI FLAG0.2 EINT2 FLAG2 EI FLAG0.3 EINT3 FLAG3 EI FLAG0.4...

  • Page 70: Interrupt Vector Table

    A96G140/A96G148 User’s manual Interrupt vector table Interrupt controller of A96G140/A96G148 supports 24 interrupt sources as shown in table 8. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.

  • Page 71: Interrupt Sequence

    A96G140/A96G148 User’s manual 6. Interrupt controller And it remains ‘1’ until CPU accepts interrupt. If the interrupt is served, the interrupt request flag will be cleared automatically. Interrupt sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction.

  • Page 72: Effective Timing After Controlling Interrupt Bit

    6. Interrupt controller A96G140/A96G148 User’s manual IE.EA Flag 0 Program Counter low Byte SP  SP + 1 M (SP)  (PCL) Saves PC value in order to continue process again after executing ISR Program Counter high Byte SP  SP + 1 M (SP) ...

  • Page 73: Multi-Interrupt

    A96G140/A96G148 User’s manual 6. Interrupt controller Interrupt Enable Register command After executing IE set/clear, enable register is effective. Next Instruction Next Instruction Figure 17. Effective Timing of Interrupt Enable Register Case B in figure 18 shows the effective time after controlling Interrupt Flag Registers.

  • Page 74: Interrupt Enable Accept Timing

    6. Interrupt controller A96G140/A96G148 User’s manual Main Program Service INT1 ISR INT0 ISR Set EA Occur Occur INT1 Interrupt INT0 Interrupt RETI RETI Figure 19. Effective Timing of Multi-Interrupt Figure 19 shows an example of multi-interrupt processing. While INT1 is served, INT0 which has higher priority than INT1 is occurred.

  • Page 75: Interrupt Service Routine Address

    A96G140/A96G148 User’s manual 6. Interrupt controller System Max. 4 Machine Cycle 4 Machine Cycle Clock Interrupt goes Interrupt Interrupt Processing active latched Interrupt Routine : LCALL & LJMP Figure 20. Interrupt Response Timing Diagram Interrupt service routine address Basic Interval Timer...

  • Page 76: Interrupt Timing

    6. Interrupt controller A96G140/A96G148 User’s manual 6.10 Interrupt timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-bit interrupt Vector INT_VEC PROGA NOTE: Variable x and n of a command cycle CLPx imply the followings: ...

  • Page 77: External Interrupt Flag Register (Eiflag0 And Eiflag1)

    A96G140/A96G148 User’s manual 6. Interrupt controller After a reset, IP and IP1 are cleared to ‘00H’. If interrupts have the same priority level, lower number interrupt is served first. 6.11.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1) External Interrupt Flag 0 Register (EIFLAG0) and External Interrupt Flag 1 Register (EIFLAG1) are set to ‘1’...
  • Page 78 6. Interrupt controller A96G140/A96G148 User’s manual IE (Interrupt Enable Register): A8H – INT5E INT4E INT3E INT2E INT1E INT0E – Initial value: 00H Enable or Disable All Interrupt bits All Interrupt disable All Interrupt enable INT5E Enable or Disable External Interrupt 0 ~ 7 (EINT0 ~ EINT7)
  • Page 79 A96G140/A96G148 User’s manual 6. Interrupt controller IE1 (Interrupt Enable Register 1): A9H – – INT11E INT10E INT9E INT8E INT7E INT6E – – Initial value: 00H INT11E Enable or Disable External Interrupt 12 (EINT12) Disable Enable INT10E Enable or Disable USI0Tx Interrupt...
  • Page 80 6. Interrupt controller A96G140/A96G148 User’s manual IE2 (Interrupt Enable Register 2): AAH –- – INT17E INT16E INT15E INT14E INT13E INT12E – – Initial value: 00H INT17E Enable or Disable Timer 4/5 Match Interrupt Disable Enable INT16E Enable or Disable Timer 3 Match Interrupt...
  • Page 81 A96G140/A96G148 User’s manual 6. Interrupt controller IE3 (Interrupt Enable Register 3): ABH – – INT23E INT22E INT21E INT20E INT19E INT18E – – Initial value: 00H INT23E Enable or Disable LVI Interrupt Disable Enable INT22E Enable or Disable BIT Interrupt Disable...
  • Page 82 6. Interrupt controller A96G140/A96G148 User’s manual EIFLAG0 (External Interrupt Flag0 Register): C0H FLAG7 FLAG6 FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 FLAG0 Initial value: 00H EIFLAG0[7:0] When an External Interrupt 0-7 is occurred, the flag becomes ‘1’.The flag is cleared only by writing ‘0’ to the bit. So, the flag should be cleared by software.
  • Page 83 A96G140/A96G148 User’s manual 6. Interrupt controller EIFLAG1 (External Interrupt Flag 1 Register): A6H – – T0OVIFR T0IFR FLAG12 FLAG11 FLAG10 FLAG8 – – Initial value: 00H When T0 overflow interrupt occurs, this bit becomes ‘1’. For clearing T0OVIFR bit, write‘0’ to this bit or automatically clear by INT_ACK signal.

  • Page 84: Clock Generator

    — HSIRC OSC/32 (1MHz) — HSIRC OSC/64 (0.5MHz) Main crystal oscillator (4~12MHz)  Sub-crystal Oscillator (32.768kHz)  Internal LSIRC oscillator (128kHz)  Clock generator block diagram In this section, a clock generator of A96G140/A96G148 is described in a block diagram.

  • Page 85: Register Map

    A96G140/A96G148 User’s manual 7. Clock generator Main OSC XOUT STOP Mode IRCS[2:0] XCLKE System SCLK Clock Gen. (Core, System, Clock Per ipheral) Chang e HIRC HIRC O SC 1/16 (32MHz) 1/32 Stabilization Time 1/64 Generation BITCK[2:0] STOP Mode overflow HSIRCE...
  • Page 86 7. Clock generator A96G140/A96G148 User’s manual OSCCR (Oscillator Control Register): C8H – LSIRCE IRCS2 IRCS1 IRCS0 HSIRCE XCLKE SCLKE – Initial value: 28H LSIRCE Control the Operation of the Low Frequency (128kHz) internal RC Oscillator at Stop mode Disable operation of LSIRC OSC...
  • Page 87 A96G140/A96G148 User’s manual 7. Clock generator XTFLSR (Main Crystal OSC Filter Selection Register): 1038H NFSEL1 NFSEL0 MX_FIL_DIS MX_ISEL1 MX_ISEL0 SUB_FIL_DIS SUB_ISEL1 SUB_ISEL0 Initial value: 00H NFSEL[1:0] Noise Filter Selective Option NFSEL1 NFSEL0 Description 18ns (Default, 12MHz) 22ns (12MHz) 26ns (8MHz)

  • Page 88: Basic Interval Timer

    A96G140/A96G148 User’s manual 8 Basic interval timer A96G140/A96G148 has a free running 8-bit Basic Interval Timer (BIT). BIT generates the time base for watchdog timer counting, and provides a basic interval timer interrupt (BITIFR). BIT of A96G140/A96G148 features the followings: During Power On, BIT gives a stable clock generation time ...

  • Page 89: Bit Register Description

    A96G140/A96G148 User’s manual 8. Basic interval timer BIT register description BITCNT (Basic Interval Timer Counter Register): 8CH BITCNT7 BITCNT6 BITCNT5 BITCNT4 BITCNT3 BITCNT2 BITCNT1 BITCNT0 Initial value: 00H BITCNT[7:0] BIT Counter BITCR (Basic Interval Timer Control Register): 8BH BITIFR BITCK2...

  • Page 90: Watchdog Timer

    9. Watchdog timer A96G140/A96G148 User’s manual 9 Watchdog timer Watchdog timer (WDT) rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. Watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.

  • Page 91: Wdt Block Diagram

    A96G140/A96G148 User’s manual 9. Watchdog timer WDT block diagram Watchdog Timer Counter Register Clear BIT Overflow To Reset WDTCNT Circuit WDTEN Clear WDTIFR INT_ACK comparator WDTIF WDTDR Watchdog Timer Data Register WDTCL WDTRSON WDTCR Figure 27. Watch Dog Timer Interrupt Timing Waveform Register map Table 12.
  • Page 92 9. Watchdog timer A96G140/A96G148 User’s manual WDTDR (Watch Dog Timer Data Register: Write Case): 8EH WDTDR7 WDTDR 6 WDTDR 5 WDTDR 4 WDTDR 3 WDTDR 2 WDTDR 1 WDTDR 0 Initial value: FFH WDTDR[7:0] Set a period WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTDR Value+1) NOTE: Do not write “0”...

  • Page 93: 10 Watch Timer

    7-bit counter in order to increase resolution. In WTDR, it can control WT clear and set interval value at write time, and it can read 7-bit WT counter value at read time. 10.1 WT block diagram In this section, watch timer of A96G140/A96G148 is described in a block diagram. S UB Match Clear...

  • Page 94: Watch Timer Register Description

    10. Watch timer A96G140/A96G148 User’s manual Table 13. Watch Timer Register Map Name Address Direction Default Description WTCNT Watch Timer Counter Register WTDR Watch Timer Data Register WTCR Watch Timer Control Register 10.3 Watch timer register description WTCNT (Watch Timer Counter Register: Read Case): 89H –...
  • Page 95 A96G140/A96G148 User’s manual 10. Watch timer WTCR (Watch Timer Control Register): 96H – – WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 – – Initial value: 00H WTEN Control Watch Timer Disable Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write WTIFR ‘0’...

  • Page 96: Timer 0/1/2/3/4/5

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11 Timer 0/1/2/3/4/5 11.1 Timer 0 An 8-bit timer 0 consists of a multiplexer, a timer 0 counter register, a timer 0 data register, a timer 0 capture data register and a timer 0 control register (T0CNT, T0DR, T0CDR, T0CR).

  • Page 97: Figure 29. 8-Bit Timer/Counter Mode For Timer 0

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 ADDRESS : B2H T0CR T0EN T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC INITIAL VALUE: 0000_0000B Match signal Clear fx/2 T0CC fx/4 8-bit Timer 0 Counter fx/8 INT_ACK T0CNT(8Bit) fx/32 Clear fx/128 fx/512 Match To interrupt...

  • Page 98: 8-Bit Pwm Mode

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11.1.2 8-bit PWM mode Timer 0 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T0O/PWM0O pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting the T0O/PWM0O function by P5FSR[5:4] bits.

  • Page 99: Figure 32. Pwm Output Waveforms In Pwm Mode For Timer 0

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 PWM Mode(T0MS = 01b) Set T0EN Timer 0 clock T0CNT T0DR T0 Overflow Interrupt 1. T0DR = 4AH T0PWM T0 Match Interrupt 2. T0DR = 00H T0PWM T0 Match Interrupt 3. T0DR = FFH...

  • Page 100: 8-Bit Capture Mode

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11.1.3 8-bit capture mode Timer 0 capture mode is set by configuring T0MS[1:0] as ‘1x’. Clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode has, and the interrupt occurs when T0CNT equals to T0DR.

  • Page 101: Figure 34. Input Capture Mode Operation For Timer 0

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 Figure 34. Input Capture Mode Operation for Timer 0 Figure 35. Express Timer Overflow in Capture Mode...

  • Page 102: Timer 0 Block Diagram

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11.1.4 Timer 0 block diagram INT_ACK Clear To interrupt T0OVIFR block fx/2 fx/4 8-bit Timer 0 Counter Match signal fx/8 Clear INT_ACK T0CNT (8Bit) fx/32 T0CC Clear fx/128 Clear fx/512 Match To interrupt T0EN...
  • Page 103 A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 T0DR (Timer 0 Data Register): B4H T0DR7 T0DR6 T0DR5 T0DR4 T0DR3 T0DR2 T0DR1 T0DR0 Initial value: FFH T0DR[7:0] T0 Data T0CDR (Timer 0 Capture Data Register: Read Case, Capture mode only): B4H T0CDR7 T0CDR6...

  • Page 104: Timer 1

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11.2 Timer 1 A 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register high/low and timer 1 control register high/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH, T1CRL).
  • Page 105 A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 The external clock (EC1) counts up the timer at the rising edge. If the EC1 is selected as a clock source by T1CK[2:0], EC1 port should be set to the input port by P13IO bit.

  • Page 106: Figure 37. 16-Bit Timer/Counter Mode Of Timer 1

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual ADDRESS:BBH – – – – T1EN T1MS1 T1MS0 T1CC T1CRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR T1CRL INITIAL VALUE : 0000_0000B – 16-bit A Data Register...

  • Page 107: 16-Bit Capture Mode

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 11.2.2 16-bit capture mode It uses an internal/external clock as a clock source. Basically, the 16-bit timer 1 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T1CNTH/T1CNTL is equal to T1ADRH/T1ADRL.

  • Page 108: 16-Bit Ppg Mode

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual Figure 40. 16-bit Capture Mode Operation Example 11.2.3 16-bit PPG mode TIMER 1 has a PPG (Programmable Pulse Generation) function. In PPG mode, T1O/PWM1O pin outputs up to 16-bit resolution PWM output. For this function, T1O/PWM1O pin must be configured as a PWM output by setting P1FSRL[5:4] to ‘11’.

  • Page 109: Figure 41. 16-Bit Ppg Mode Of Timer 1

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 ADDRESS:BBH – – – – T1EN T1MS1 T1MS0 T1CC T1CRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR T1CRL INITIAL VALUE : 0000_0000B – 16-bit A Data Register...

  • Page 110: Figure 42. 16-Bit Ppg Mode Operation Example

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual Repeat Mode(T1MS = 11b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock Counter T1ADRH/L T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L PWM1O B Match A Match 2. T1BDRH/L >= T1ADRH/L...

  • Page 111: 16-Bit Timer 1 Block Diagram

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 11.2.4 16-bit timer 1 block diagram In this section, a 16-bit timer 1 is described in a block diagram. 16-bit A Data Register T1ADRH/T1ADRL A Match Reload T1CC T1EN To Timer 2 T1CK[2:0] block...
  • Page 112 11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual T1ADRH (Timer 1 A data High Register): BDH T1ADRH7 T1ADRH6 T1ADRH5 T1ADRH4 T1ADRH3 T1ADRH2 T1ADRH1 T1ADRH0 Initial value: FFH T1ADRH[7:0] T1 A Data High Byte T1ADRL (Timer 1 A Data Low Register): BCH T1ADRL7...
  • Page 113 A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 T1CRH (Timer 1ControlHigh Register): BBH – – – – T1EN T1MS1 T1MS0 T1CC – – – – Initial value: 00H T1EN Control Timer 1 Timer 1 disable Timer 1 enable (Counter clear and start)

  • Page 114: Timer 2

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual T1CRL (Timer 1ControlLow Register): BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR – Initial value: 00H T1CK[2:0] Select Timer 1 clock source. fx is main system clock frequency T1CK2 T1CK1 T1CK0 Description fx/2048...

  • Page 115: 16-Bit Timer/Counter Mode

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 The timer/counter 2 can be a divided clock of a system clock which is selected from prescaler output and T1 A Match (timer 1 A match signal). The clock source is selected by a clock selection logic, controlled by clock selection bits (T2CK[2:0]).

  • Page 116: Figure 44. 16-Bit Timer/Counter Mode Of Timer 2

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual ADDRESS:C3H – – – – T2EN T2MS1 T2MS0 T2CC T2CRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:C2H – – T2CK2 T2CK1 T2CK0 T2IFR T2POL T2CNTR T2CRL INITIAL VALUE : 0000_0000B – –...

  • Page 117: 16-Bit Capture Mode

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 11.3.2 16-bit capture mode Timer 2 capture mode is set by configuring T2MS[1:0] as ‘01’. It uses an internal clock as a clock source. Basically, the 16-bit timer 2 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T2CNTH/T2CNTL is equal to T2ADRH/T2ADRL.

  • Page 118: Figure 47. 16-Bit Capture Mode Operation Example

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual Figure 47. 16-bit Capture Mode Operation Example Figure 48. Express Timer Overflow in Capture Mode...

  • Page 119: 16-Bit Ppg Mode

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 11.3.3 16-bit PPG mode TIMER 2 has a PPG (Programmable Pulse Generation) function. In PPG mode, T2O/PWM2O pin outputs up to 16-bit resolution PWM output. For this function, T2O/PWM2O pin must be configured as a PWM output by setting P1FSRL[3:2] to ‘11’.

  • Page 120: Figure 50. 16-Bit Ppg Mode Operation Example

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual Repeat Mode(T2MS = 11b) and "Start High"(T2POL = 0b). Clear and Start Set T2EN Timer 2 clock Counter T2ADRH/L T2 Interrupt 1. T2BDRH/L(5) < T2ADRH/L PWM2O B Match A Match 2. T2BDRH/L >= T2ADRH/L...

  • Page 121: 16-Bit Timer 2 Block Diagram

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 11.3.4 16-bit timer 2 block diagram In this section, a 16-bit timer 2 is described in a block diagram. 16-bit A Data Register T2ADRH/T2ADRL A Match Reload T2CC T2CK[2:0] T2EN INT_ACK Buffer Register A...
  • Page 122 11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual T2ADRH (Timer 2 A data High Register): C5H T2ADRH7 T2ADRH6 T2ADRH5 T2ADRH4 T2ADRH3 T2ADRH2 T2ADRH1 T2ADRH0 Initial value: FFH T2ADRH[7:0] T2 A Data High Byte T2ADRL (Timer 2 A Data Low Register): C4H T2ADRL7...
  • Page 123 A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 T2CRH (Timer 2ControlHigh Register): C3H – – – – T2EN T2MS1 T2MS0 T2CC – – – – Initial value: 00H T2EN Control Timer 2 Timer 2 disable Timer 2 enable (Counter clear and start)

  • Page 124: Timer 3

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11.4 Timer 3 A 16-bit timer 3 consists of a multiplexer, timer 3 A data high/low register, timer 3 B data high/low register and timer 3 control high/low register (T3ADRH, T3ADRL, T3BDRH, T3BDRL, T3CRH, and T3CRL).

  • Page 125: Figure 45. 16-Bit Timer/Counter Mode Operation Example

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 by T3CK[2:0], EC3 port should be set as an input port by configuring P00 IO bit. ADDRESS:1000H – – – – T3EN T3MS1 T3MS0 T3CC T3CRH INITIAL VALUE : 0000_0000B – – – –...

  • Page 126: 16-Bit Capture Mode

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11.4.2 16-bit capture mode Timer 3 capture mode is set by configuring T3MS[1:0] as ‘01’. It uses an internal/external clock as a clock source. Basically, the 16-bit timer 3 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T3CNTH/T3CNTL is equal to T3ADRH/T3ADRL.

  • Page 127: Figure 55. 16-Bit Capture Mode Operation Example

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 Figure 55. 16-bit Capture Mode Operation Example Figure 56. Express Timer Overflow in Capture Mode...

  • Page 128: 16-Bit Ppg Mode

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11.4.3 16-bit PPG mode TIMER 3 has a PPG (Programmable Pulse Generation) function. In PPG mode, T3O/PWM3O pin outputs up to 16-bit resolution PWM output. For this function, T3O/PWM3O pin must be configured as a PWM output by setting P0FSRH[1:0] to ‘11’...

  • Page 129: Figure 58. 16-Bit Ppg Mode Operation Example

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 Repeat Mode(T3MS = 11b) and "Start High"(T3POL = 0b). Clear and Start Set T3EN Timer 3 clock Counter T3ADRH/L T3 Interrupt 1. T3BDRH/L(5) < T3ADRH/L PWM3O B Match A Match 2. T3BDRH/L >= T3ADRH/L...

  • Page 130: 16-Bit Timer 3 Block Diagram

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11.4.4 16-bit timer 3 block diagram In this section, a 16-bit timer 3 is described in a block diagram. 16-bit A Data Register T3ADRH/T3ADRL A Match Reload T3CC T3EN To Timer 4 T3CK[2:0] block...
  • Page 131 A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 T3ADRH (Timer 3 A data High Register): 1002H T3ADRH7 T3ADRH6 T3ADRH5 T3ADRH4 T3ADRH3 T3ADRH2 T3ADRH1 T3ADRH0 Initial value: FFH T3ADRH[7:0] T3 A Data High Byte T3ADRL (Timer 3 A Data Low Register): 1003H T3ADRL7...
  • Page 132 11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual T3CRH (Timer 3 Control High Register): 1000H – – – – T3EN T3MS1 T3MS0 T3CC – – – – Initial value: 00H T3EN Control Timer 3 Timer 3 disable Timer 3 enable (Counter clear and start)

  • Page 133: Timer 4

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 T3CRL (Timer 3 Control Low Register): 1001H – T3CK2 T3CK1 T3CK0 T3IFR T3POL T3ECE T3CNTR – Initial value: 00H T3CK[2:0] Select Timer 3 clock source. fx is main system clock frequency T3CK2 T3CK1 T3CK0 Description...

  • Page 134: 16-Bit Timer/Counter Mode

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual The timer/counter 4 can be a divided clock of a system clock selected from prescaler output and T3 A Match (timer 3 A match signal). The clock source is selected by a clock selection logic controlled by clock selection bits (T4CK[2:0]).

  • Page 135: Figure 53. 16-Bit Timer/Counter Mode Operation Example

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 ADDRES S:1008H – – – – T4EN T4MS1 T4MS0 T4CC T4CRH INITIAL VALUE : 0000_0000B – – – – ADDRES S:1009H – – T4CK2 T4CK1 T4CK0 T4IFR T4POL T4CNTR T4CRL INITIAL VALUE : 0000_0000B –...

  • Page 136: 16-Bit Capture Mode

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11.5.2 16-bit capture mode Timer 4 capture mode is set by configuring T4MS[1:0] as ‘01’. It uses an internal clock as a clock source. Basically, the 16-bit timer 4 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T4CNTH/T4CNTL is equal to T4ADRH/T4ADRL.

  • Page 137: Figure 63. 16-Bit Capture Mode Operation Example

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 Figure 63. 16-bit Capture Mode Operation Example Figure 64. Express Timer Overflow in Capture Mode...

  • Page 138: 16-Bit Ppg Mode

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11.5.3 16-bit PPG mode TIMER 4 has a PPG (Programmable Pulse Generation) function. In PPG mode, T4O/PWM4O pin outputs up to 16-bit resolution PWM output. For this function, T4O/PWM4O pin must be configured as a PWM output by setting P0FSRH[3:2] to ‘11’.

  • Page 139: Figure 66. 16-Bit Ppg Mode Operation Example

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 Repeat Mode(T4MS = 11b) and "Start High"(T4POL = 0b). Clear and Start Set T4EN Timer 4 clock Counter T4ADRH/L T4 Interrupt 1. T4BDRH/L(5) < T4ADRH/L PWM4O B Match A Match 2. T4BDRH/L >= T4ADRH/L...

  • Page 140: 16-Bit Timer 4 Block Diagram

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual 11.5.4 16-bit timer 4 block diagram In this section, a 16-bit timer 4 is described in a block diagram. 16-bit A Data Re gister T4ADRH/T4ADRL A Match Reload T4CC T4CK[2:0] T4EN Buffer Register A...
  • Page 141 A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 T4ADRH (Timer 4 A data High Register): 100AH T4ADRH7 T4ADRH6 T4ADRH5 T4ADRH4 T4ADRH3 T4ADRH2 T4ADRH1 T4ADRH0 Initial value: FFH T4ADRH[7:0] T4 A Data High Byte T4ADRL (Timer 4 A Data Low Register): 100BH T4ADRL7...
  • Page 142 11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual T4CRH (Timer 4 Control High Register): 1008H – – – – T4EN T4MS1 T4MS0 T4CC – – – – Initial value: 00H T4EN Control Timer 4 Timer 4 disable Timer 4 enable (Counter clear and start)

  • Page 143: Timer 5

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 11.6 Timer 5 A 16-bit timer 5 consists of a multiplexer, timer 5 A data high/low register, timer 5 B data high/low register and timer 5 control high/low register (T5ADRH, T5ADRL, T5BDRH, T5BDRL, T5CRH, and T5CRL).

  • Page 144: Figure 61. 16-Bit Timer/Counter Mode Operation Example

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual ADDRES S:1010H – – – – T5EN T5MS1 T5MS0 T5CC T5CRH INITIAL VALUE : 0000_0000B – – – – ADDRES S:1011H – – T5CK2 T5CK1 T5CK0 T5IFR T5POL T5CNTR T5CRL INITIAL VALUE : 0000_0000B –...

  • Page 145: 16-Bit Capture Mode

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 11.6.2 16-bit capture mode Timer 5 capture mode is set by configuring T5MS[1:0] as ‘01’. It uses an internal clock as a clock source. Basically, the 16-bit timer 5 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T5CNTH/T5CNTL is equal to T5ADRH/T5ADRL.

  • Page 146: Figure 71. 16-Bit Capture Mode Operation Example

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual Figure 71. 16-bit Capture Mode Operation Example Figure 72. Express Timer Overflow in Capture Mode...

  • Page 147: 16-Bit Ppg Mode

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 11.6.3 16-bit PPG mode TIMER 5 has a PPG (Programmable Pulse Generation) function. In PPG mode, T5O/PWM5O pin outputs up to 16-bit resolution PWM output. For this function, T5O/PWM5O pin must be configured as a PWM output by setting P0FSRH[5:4] to ‘11’.

  • Page 148: Figure 74. 16-Bit Ppg Mode Operation Example

    11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual Repeat Mode(T5MS = 11b) and "Start High"(T5POL = 0b). Clear and Start Set T5EN Timer 5 clock Counter T5ADRH/L T5 Interrupt 1. T5BDRH/L(5) < T5ADRH/L PWM5O B Match A Match 2. T5BDRH/L >= T5ADRH/L...

  • Page 149: 16-Bit Timer 5 Block Diagram

    A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 11.6.4 16-bit timer 5 block diagram In this section, a 16-bit timer 5 is described in a block diagram. 16-bit A Data Re gister T5ADRH/T5ADRL A Match Reload T5CC T5CK[2:0] T5EN Buffer Register A...
  • Page 150 11. Timer 0/1/2/3/4/5 A96G140/A96G148 User’s manual T5ADRH (Timer 5 A data High Register): 1012H T5ADRH7 T5ADRH6 T5ADRH5 T5ADRH4 T5ADRH3 T5ADRH2 T5ADRH1 T5ADRH0 Initial value: FFH T5ADRH[7:0] T5 A Data High Byte T5ADRL (Timer 5 A Data Low Register): 1013H T5ADRL7...
  • Page 151 A96G140/A96G148 User’s manual 11. Timer 0/1/2/3/4/5 T5CRH (Timer 5 Control High Register): 1010H – – – – T5EN T5MS1 T5MS0 T5CC – – – – Initial value: 00H T5EN Control Timer 5 Timer 5 disable Timer 5 enable (Counter clear and start)

  • Page 152: 12 Buzzer Driver

    A96G140/A96G148 User’s manual 12 Buzzer driver A buzzer of A96G140/A96G148 consists of 8-bit counter, a buzzer data register (BUZDR), and a buzzer control register (BUZCR). It outputs square wave (61.035Hz to 125.0KHz @ 8MHz) through P13/AN10/EC1/BUZO pin, and its buzzer data register (BUZDR) controls the buzzer frequency (refer to the following expression).

  • Page 153: Register Description

    A96G140/A96G148 User’s manual 12. Buzzer driver Table 27. Buzzer Driver Register Map Name Address Direction Default Description BUZDR Buzzer Data Register BUZCR Buzzer Control Register 12.3 Register description BUZDR (Buzzer Data Register): 8FH BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1...

  • Page 154: 13 12-Bit Adc

    A96G140/A96G148 User’s manual 13 12-bit ADC Analog-to-digital converter (ADC) of A96G140/A96G148 allows conversion of an analog input signal to corresponding 12-bit digital value. This A/D module has eight analog inputs. Output of the multiplexer becomes input into the converter which generates the result through successive approximation.

  • Page 155: Figure 77. 12-Bit Adc Block Diagram

    A96G140/A96G148 User’s manual 13. 12-bit ADC TRIG[2:0] ADSEL[3:0] (Select one input pin of the assigned pins) ADST T1 A match signal Start T3 A match signal EXTINT0~7 EXTINT8 Clock ADCLK Selector Clear Input Pins AFLAG AN14 AN15 Comparator Control To interrupt...

  • Page 156: Adc Operation

    13. 12-bit ADC A96G140/A96G148 User’s manual 13.3 ADC operation In this section, control registers and align bits are introduced in figure 80, and ADC operation flow sequence is introduced in figure 81. Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8...

  • Page 157: Register Map

    A96G140/A96G148 User’s manual 13. 12-bit ADC Figure 81. ADC Operation Flow Sequence 13.4 Register map Table 28. ADC Register Map Name Address Direction Default Description ADCDRH A/D Converter Data High Register ADCDRL A/D Converter Data Low Register ADCCRH A/D Converter Control High Register...
  • Page 158 13. 12-bit ADC A96G140/A96G148 User’s manual ADCDRL (A/D Converter Data Low Register): 9EH ADDM3 ADDM2 ADDM1 ADDM0 ADDL7 ADDL6 ADDL5 ADDL4 ADDL3 ADDL2 ADDL1 ADDL0 Initial value: xxH ADDM[3:0] MSB align, A/D Converter Low Data (4-bit) ADDL[7:0] LSB align, A/D Converter Low Data (8-bit)
  • Page 159 A96G140/A96G148 User’s manual 13. 12-bit ADC ADCCRL (A/D Converter Counter Low Register): 9CH STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value: 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable...

  • Page 160: Usi (Usart + Spi + I2C)

    A96G140/A96G148 User’s manual 14 USI (USART + SPI + I2C) USI stands for the combination of USART, SPI and I2C. A96G140/A96G148 has two USI function blocks, USI0 and USI1, which are identical to each other functionally. Each USI block consists of USI...

  • Page 161: Usin Uart Block Diagram

    A96G140/A96G148 User’s manual 14. USI Transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. A write buffer allows continuous transfer of data without any delay between frames.

  • Page 162: Usin Clock Generation

    14. USI A96G140/A96G148 User’s manual 14.3 USIn clock generation Figure 83. Clock Generation Block Diagram (USIn) Clock generation logic generates base clock signal for the transmitter and the receiver. The USIn supports four modes of clock operation such as normal asynchronous mode, double speed asynchronous mode, master synchronous mode and slave synchronous mode.

  • Page 163: Usin External Clock (Sckn)

    A96G140/A96G148 User’s manual 14. USI 14.4 USIn external clock (SCKn) External clocking is used in synchronous mode of operation. External clock input from the SCKn pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.

  • Page 164: Usin Uart Parity Bit

    14. USI A96G140/A96G148 User’s manual 1 start bit  5, 6, 7, 8 or 9 data bits  no, even or odd parity bit  1 or 2 stop bits  A frame starts with a start bit followed by the least significant data bit (LSB). The next data bits, up to nine, are succeeding, ending with the most significant bit (MSB).

  • Page 165: Usin Uart Transmitter

    A96G140/A96G148 User’s manual 14. USI = Dn-1 ^ … ^ D3 ^ D2 ^ D1 ^ D0 ^ 0  even = Dn-1 ^ … ^ D3 ^ D2 ^ D1 ^ D0 ^ 1  : Parity bit using even parity ...

  • Page 166: Usin Uart Parity Generator

    14. USI A96G140/A96G148 User’s manual The TXCn flag is automatically cleared when the transmit complete interrupt serve routine is executed, or it can be cleared by writing ‘0’ to TXCn bit in USInST1 register. When the transmit complete interrupt enable (TXCIEn) bit in USInCR2 register is set and the global interrupt is enabled, UART transmit complete interrupt is generated while TXCn flag is set.

  • Page 167: Usin Uart Receiver Flag And Interrupt

    A96G140/A96G148 User’s manual 14. USI 14.9.2 USIn UART receiver flag and interrupt The UART receiver has one flag that indicates the receiver state. The receive complete (RXCn) flag indicates whether there are unread data in the receive buffer. This flag is set when there is unread data in the receive buffer and cleared when the receive buffer is empty.

  • Page 168: Figure 86. Asynchronous Start Bit Sampling (Usin)

    14. USI A96G140/A96G148 User’s manual The data recovery logic does sampling and low pass filtering the incoming bits, and removing the noise of RXDn pin. The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate is 16 times of the baud-rate in normal mode and 8 times the baud-rate for double speed mode (DBLSn=1).

  • Page 169: Usin Spi Mode

    A96G140/A96G148 User’s manual 14. USI BIT n RXDn Sample (DBLSn = 0) Sample (DBLSn = 1) Figure 87. Asynchronous Sampling of Data and Parity Bit (USIn) The process for detecting stop bit is same as clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (FEn) flag is set.

  • Page 170: Usin Spi Clock Formats And Timing

    14. USI A96G140/A96G148 User’s manual Note that during SPI mode of operation, the pin RXDn is renamed as MISOn and TXDn is renamed as MOSIn for compatibility to other SPI devices. 14.11 USIn SPI clock formats and timing To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the USIn has a clock polarity bit (CPOLn) and a clock phase control bit (CPHAn) to select one of four clock formats for data transfers.

  • Page 171: Figure 90. Usin Spi Clock Formats When Cphan = 1

    A96G140/A96G148 User’s manual 14. USI goes to active low. The first SCKn edge causes both the master and the slave to sample the data bit value on their MISOn and MOSIn inputs, respectively. At the second SCKn edge, the USIn shifts the second data bit value out to the MOSIn and MISOn outputs of the master and slave, respectively.

  • Page 172: Usin Spi Block Diagram

    14. USI A96G140/A96G148 User’s manual In master mode of operation, even if transmission is not enabled (TXEn=0), writing data to the USInDR register is necessary because the clock SCKn is generated from transmitter block. 14.12 USIn SPI block diagram USInBD...

  • Page 173: Usin I2C Bit Transfer

    A96G140/A96G148 User’s manual 14. USI Both master and slave operation  Bus busy detection  14.14 USIn I2C bit transfer The data on the SDAn line must be stable during HIGH period of the clock, SCLn. The HIGH or LOW state of the data line can only change when the clock signal on the SCLn line is LOW.

  • Page 174: Usin I2C Data Transfer

    14. USI A96G140/A96G148 User’s manual SDAn SCLn START Condition STOP Condition Figure 93. START and STOP Condition (USIn) 14.16 USIn I2C data transfer Every byte put on the SDAn line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited.

  • Page 175: Usin I2C Synchronization/ Arbitration

    A96G140/A96G148 User’s manual 14. USI The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave.

  • Page 176: Usin I2C Operation

    14. USI A96G140/A96G148 User’s manual Wait High Start High Counting Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT SCLn Figure 96. Clock Synchronization during Arbitration Procedure (USIn) Arbitration Process Device 1 loses Device1 outputs not adapted Arbitration High...

  • Page 177: Usin I2C Master Transmitter

    A96G140/A96G148 User’s manual 14. USI 14.19.1 USIn I2C master transmitter To operate I2C in master transmitter, follow the recommended steps below: Enable I2C by setting USInMS[1:0] bits in USInCR1 and USInEN bit in USInCR2. This provides main clock to the peripheral.
  • Page 178 14. USI A96G140/A96G148 User’s manual set the STOPCn bit in USInCR4. Case 3: Master transmits repeated START condition with not checking ACK signal. In this case, load SLAn+R/W into the USInDR and set STARTCn bit in USInCR4. After doing one of the actions above, write any arbitrary to USInST2 to release SCLn line.

  • Page 179: Usin I2C Master Receiver

    A96G140/A96G148 User’s manual 14. USI 14.19.2 USIn I2C master receiver To operate I2C in master receiver, follow the recommended steps below: Enable I2C by setting USInMS[1:0] bits in USInCR1and USInEN bit in USInCR2. This provides main clock to the peripheral.

  • Page 180: Usin I2C Slave Transmitter

    14. USI A96G140/A96G148 User’s manual Case 2: Master stops data transfer because it receives no ACK signal from slave. In this case, set the STOPCn bit in USInCR4. Case 3: Master transmits repeated START condition due to no ACK signal from slave.

  • Page 181: Usin I2C Slave Receiver

    A96G140/A96G148 User’s manual 14. USI If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn. Note that the hold time of SDAn is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USInSDHR.
  • Page 182 14. USI A96G140/A96G148 User’s manual If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn. Note that the hold time of SDAn is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USInSDHR.

  • Page 183: Usin I2C Block Diagram

    A96G140/A96G148 User’s manual 14. USI 14.20 USIn I2C block diagram IICnIFR To interrupt block Slave Address Register USInSAR RXACKn, GCALLn, Interrupt IICnIE TENDn, STOPDn, Generator SSELn, MLOSTn, General Call And USInGCE BUSYn, TMODEn Address Detector Receive Shift Register SDAn USInDR, (Rx)

  • Page 184: Usin Register Description

    14. USI A96G140/A96G148 User’s manual Table 31. USI Register Map (continued) Name Address Direction Default Description USI0ST1 USI0 Status Register 1 USI0ST2 USI0 Status Register 2 USI1BD USI1 Baud Rate Generation Register USI1DR USI1 Data Register USI1SDHR USI1 SDA Hold Time Register...
  • Page 185 A96G140/A96G148 User’s manual 14. USI USInDR (USIn Data Register: For UART, SPI, and I2C mode): E5H/F5H, n = 0, 1 USInDR7 USInDR 6 USInDR 5 USInDR 4 USInDR 3 USInDR 2 USInDR 1 USInDR 0 Initial value: 00H USInDR[7:0] The USIn transmit buffer and receive buffer share the same I/O address with this DATA register.
  • Page 186 14. USI A96G140/A96G148 User’s manual USInSCLR (USInSCL Low Period Register: For I2C mode): E6H/F6H, n = 0, 1 USInSCLR7 USInSCLR6 USInSCLR5 USInSCLR 4 USInSCLR 3 USInSCLR 2 USInSCLR 1 USInSCLR 0 Initial value: 3FH USInSCLR[7:0] This register defines the high period of SCLn when it operates in I2C master mode.
  • Page 187 A96G140/A96G148 User’s manual 14. USI USInCR1 (USIn Control Register 1: For UART, SPI, and I2C mode): D9H/E9H, n = 0, 1 USInS1 USInS0 USInMS1 USInMS0 USInPM1 USInPM0 USInS2 CPOLn ORDn CPHAn Initial value: 00H USInMS[1:0] Selects operation mode of USIn...
  • Page 188 14. USI A96G140/A96G148 User’s manual USInCR2 (USIn Control Register 2: For UART, SPI, and I2C mode): DAH/EAH, n = 0, 1 DRIEn TXCIEn RXCIEn WAKEIEn TXEn RXEn USInEN DBLSn Initial value: 00H DRIEn Interrupt enable bit for data register empty (only UART and SPI mode).
  • Page 189 A96G140/A96G148 User’s manual 14. USI USInCR3 (USIn Control Register 3: For UART, SPI, and I2C mode): DBH/EBH, n = 0, 1 MASTERn LOOPSn DISSCKn USInSSEN FXCHn USInSB USInTX8 USInRX8 Initial value: 00H MASTERn Selects master or slave in SPI and synchronous mode operation and controls the direction of SCKn pin Slave mode operation (External clock for SCKn).
  • Page 190 14. USI A96G140/A96G148 User’s manual USI0CR4 (USIn Control Register 4: For I2C mode): DCH/ECH, n = 0, 1 – IICnIFR RESETn IICnIE ACKnEN IMASTERn STOPCn STARTCn – Initial value: 00H IICnIFR This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’.
  • Page 191 A96G140/A96G148 User’s manual 14. USI USInST1 (USIn Status Register 1: For UART and SPI mode): E1H/F1H, n = 0, 1 DREn TXCn RXCn WAKEn USInRST DORn Initial value: 80H DREn The DREn flag indicates if the transmit buffer (USInDR) is ready to receive new data.

  • Page 192: Baud Rate Settings (Example)

    14. USI A96G140/A96G148 User’s manual USInST2 (USIn Status Register 2: For I2C mode): E2H/F2H, n = 0, 1 GCALLn TENDn STOPDn SSELn MLOSTn BUSYn TMODEn RXACKn Initial value: 00H (NOTE) GCALLn This bit has different meaning depending on whether I2C is master or slave.

  • Page 193: Table 32. Example1 Of Usi0Bd And Usi1Bdsettings For Commonly Used Oscillator

    A96G140/A96G148 User’s manual 14. USI Table 32. Example1 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies Baud fx = 1.00MHz fx = 1.8432MHz fx = 2.00MHz rate USI0BD/USI1BD Error USI0BD/USI1BD Error USI0BD/USI1BD Error (bps) 2400 0.2% 0.0% 0.2% 4800 0.2%...

  • Page 194: Table 33. Example2 Of Usi0Bd And Usi1Bdsettings For Commonly Used Oscillator

    14. USI A96G140/A96G148 User’s manual Table 33. Example2 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies Baud rate fx = 8.00MHz fx = 11.0592MHz (bps) USI0BD/USI1BD Error USI0BD/USI1BD Error ― ― 2400 0.2% 4800 0.2% 0.0% 9600 0.2% 0.0% 14.4k...

  • Page 195: 15 Usart2

    15. USART 2 15 USART2 Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. USART2 of A96G140/A96G148 features the followings: Full Duplex Operation (Independent Serial Receive and Transmit Registers)  Asynchronous or Synchronous Operation ...

  • Page 196: Block Diagram

    15. USART 2 A96G140/A96G148 User’s manual 15.1 Block diagram UBAUD SCLK Baud Rate Generator Master Clock Sync Logic Control UMSEL[1:0] Rx Interrupt RXD2/ MISO2 Clock Control Recovery Data Recovery UMSEL1&UMSEL0 DOR/PE/FE UDATA[0] Master Checker (Rx) UDATA[1] Stop bit UMSEL0 (Rx)

  • Page 197: Clock Generation

    A96G140/A96G148 User’s manual 15. USART 2 15.2 Clock generation Clock generation logic generates a base clock signal for the Transmitter and the Receiver. USART2 supports four modes of clock operation such as Normal Asynchronous mode, Double Speed Asynchronous mode, Master Synchronous mode, and Slave Synchronous mode.

  • Page 198: External Clock (Xck)

    15. USART 2 A96G140/A96G148 User’s manual 15.3 External clock (XCK) External clocking is used by the synchronous or SPI slave modes of operation. External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must then pass through an edge detector before it can be used by the Transmitter and Receiver.

  • Page 199: Data Format

    A96G140/A96G148 User’s manual 15. USART 2 15.5 Data format A serial frame is defined to consist of one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. USART2 supports all 30 combinations of the followings as a valid frame format.

  • Page 200: Parity Bit

    15. USART 2 A96G140/A96G148 User’s manual 15.6 Parity bit Parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive-or is inverted. The parity bit is located between St + bits and first stop bit of a serial frame.

  • Page 201: Parity Generator

    A96G140/A96G148 User’s manual 15. USART 2 which has not yet been moved into the shift register. And also this flag can be cleared by writing ‘0’ to this bit field. Writing ‘1’ to this field is not valid. When Data Register Empty Interrupt Enable (UDRIE) bit in UCTRL2 register is set and Global Interrupt is enabled, USART2 Data Register Empty Interrupt is generated while UDRE flag is set.

  • Page 202: Receiver Flag And Interrupt

    15. USART 2 A96G140/A96G148 User’s manual reading the UDATA register. If 9-bit characters are used (USIZE[2:0] = 7), the ninth bit is stored in RX8 bit field in the UCTRL3 register. The 9th bit must be read from the RX8 bit before reading the low 8 bits from the UDATA register.

  • Page 203: Disabling Receiver

    A96G140/A96G148 User’s manual 15. USART 2 15.8.4 Disabling receiver In contrast to Transmitter, disabling the Receiver by clearing RXE bit makes the Receiver inactive immediately. When the Receiver is disabled the Receiver flushes the receive buffer and the remaining data in the buffer is all reset. Function of USART2 is not overridden on the RXD2 pin, so the RXD2 pin becomes normal GPIO or primary function pin.

  • Page 204: Spi Mode

    15. USART 2 A96G140/A96G148 User’s manual If more than 2 samples have low levels, the received bit is considered to a logic 0. If more than 2 samples have high levels, the received bit is considered to a logic 1. The data recovery process is then repeated until a complete frame is received including the first stop bit.

  • Page 205: Spi Clock Formats And Timing

    A96G140/A96G148 User’s manual 15. USART 2 Programmable transmit bit rate  When SPI mode is enabled (UMSEL[1:0]=3), the Slave Select (SS2) pin becomes active low input in slave mode operation, or can be output in master mode operation if SPISS bit is set.

  • Page 206: Figure 106. Spi Clock Formats When Ucpha = 0

    15. USART 2 A96G140/A96G148 User’s manual (UCPOL=0) (UCPOL=1) SAMPLE MOSI MSB First … BIT7 BIT6 BIT2 BIT1 BIT0 LSB First … BIT0 BIT1 BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 106. SPI Clock Formats when UCPHA = 0...

  • Page 207: Figure 107. Spi Clock Formats When Ucpha = 1

    A96G140/A96G148 User’s manual 15. USART 2 When UCPHA=0, the slave begins to drive its MISO2 output with the first data bit value when SS goes to active low. The first XCK edge causes both the master and the slave to sample the data bit value on their MISO2 and MOSI inputs, respectively.

  • Page 208: Receiver Time Out (Rto)

    15. USART 2 A96G140/A96G148 User’s manual In master mode of operation, even if transmission is not enabled (TXE=0), writing data to UDATA register is necessary because the clock XCK is generated from a transmitter block. 15.10 Receiver time out (RTO) This USART2 system supports the time out function.

  • Page 209: Register Map

    A96G140/A96G148 User’s manual 15. USART 2 15.11 Register map Table 37. USART2 Register Map Name Address Direction Default Description UCTRL1 USART2 Control 1 Register UCTRL2 USART2 Control 2 Register UCTRL3 USART2 Control 3 Register UCTRL4 1018H USART2 Control 4 Register...
  • Page 210 15. USART 2 A96G140/A96G148 User’s manual UCTRL1 (USART2 Control 1 Register) CBH USIZE1 USIZE0 UMSEL1 UMSEL0 UPM1 UPM0 USIZE2 UCPOL UDORD UCPHA Initial value: 00 UMSEL[1:0] Selects operation mode of USART2 UMSEL1 UMSEL0 Operating Mode Asynchronous Mode (Normal Uart) Synchronous Mode (Synchronous Uart)
  • Page 211 A96G140/A96G148 User’s manual 15. USART 2 UCTRL2 (USART2 Control 2 Register) CCH UDRIE TXCIE RXCIE WAKEIE USARTEN Initial value: 00 UDRIE Interrupt enable bit for USART2 Data Register Empty. Interrupt from UDRE is inhibited (use polling) When UDRE is set, request an interrupt TXCIE Interrupt enable bit for Transmit Complete.
  • Page 212 15. USART 2 A96G140/A96G148 User’s manual UCTRL3 (USART2 Control 3 Register) CDH MASTER LOOPS DISXCK SPISS USBS Initial value: 00 MASTER Selects master or slave in SPI or Synchronous mode operation and controls the direction of XCK pin. Slave mode operation and XCK is input pin.
  • Page 213 A96G140/A96G148 User’s manual 15. USART 2 UCTRL4 (USART2 Control 4 Register) 1018H RTOEN RTO_FLAG FPCREN AOVSSEL AOVSEN Initial value: 00 RTOEN Enable receiver time out. Disable Enable RTO_FLAG This bit is set when RTO count overflows. This flag can generate an RTO interrupt.
  • Page 214 15. USART 2 A96G140/A96G148 User’s manual USTAT (USART2 Status Register) CFH UDRE WAKE SOFTRST Initial value: 80 UDRE The UDRE flag indicates if the transmit buffer (UDATA) is ready to be loaded with new data. If UDRE is ‘1’, it means the transmit buffer is empty and can hold one or two new data.
  • Page 215 A96G140/A96G148 User’s manual 15. USART 2 UBAUD (USART Baud-Rate Generation Register) FCH UBAUD7 UBAUD6 UBAUD5 UBAUD4 UBAUD3 UBAUD2 UBAUD1 UBAUD0 Initial value: FF UBAUD [7:0] The value in this register is used to generate internal baud rate in asynchronous mode or to generate XCK clock in synchronous or SPI mode.

  • Page 216: Baud Rate Settings (Example)

    15. USART 2 A96G140/A96G148 User’s manual RTOCH (Receiver Time Out Counter High Register) 101AH RTOCH7 RTOCH6 RTOCH5 RTOCH4 RTOCH3 RTOCH2 RTOCH1 RTOCH0 Initial value: 00 RTOCL (Receiver Time Out Counter Low Register) 101BH RTOCL7 RTOCL6 RTOCL5 RTOCL4 RTOCL3 RTOCL2 RTOCL1...

  • Page 217: 0% Error Baud Rate

    15.14 0% error baud rate USART2 system of A96G140/A96G148 supports floating point counter logic for 0% error of baud rate. By using 8-bit floating point counter logic, cumulative error to below the decimal point can be removed. Floating point counter value is defined by baud rate error. In the baud rate formula, BAUD is presented in the integer count value.

  • Page 218: Figure 109. 0% Error Baud Rate Block Diagram

    15. USART 2 A96G140/A96G148 User’s manual Integer count value TXD clock 0% Error Baud rate Generator Integer count value - 1 8bit Max floating point count value 8bit floating point counter Figure 109. 0% Error Baud Rate Block Diagram...

  • Page 219: 16 Power Down Operation

    16. Power down operation 16 Power down operation A96G140/A96G148 has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. A96G140/A96G148 provides three kinds of power saving functions such as Main-IDLE mode, Sub-IDLE mode and STOP mode. During one of these three modes, program will be stopped.

  • Page 220: Idle Mode

    16. Power down operation A96G140/A96G148 User’s manual Table 39. Peripheral Operation Status during Power Down Mode (continued) Peripheral IDLE mode STOP mode Release Method By RESET By RESET   All Interrupts Timer Interrupt (EC0, EC1,   EC3) External Interrupt ...

  • Page 221: Released Operation Of Stop Mode

    A96G140/A96G148 User’s manual 16. Power down operation Sources to exit from STOP mode is hardware reset and interrupts. The hardware reset re-defines all control registers. When awaking from STOP mode, enough oscillation stabilization time is required to normal operation. Figure 111 shows the timing diagram.

  • Page 222: Register Map

    16. Power down operation A96G140/A96G148 User’s manual SET PCON[7:0] SET IEx.b STOP Mode Interrupt Request Corresponding Interrupt IEx.b==1 ? Enable Bit (IE, IE1, IE2, IE3) STOP Mode Release Interrupt Service Routine Next Instruction Figure 112. STOP Mode Release Flow 16.5 Register map Table 40.
  • Page 223 A96G140/A96G148 User’s manual 16. Power down operation PCON (Power Control Register): 87H – – – PCON7 PCON3 PCON2 PCON1 PCON0 – – – Initial value: 00H PCON[7:0] Power Control IDLE mode enable STOP mode enable Other Values Normal operation NOTES: To enter into IDLE mode, PCON must be set to ‘01H’.

  • Page 224: 17 Reset

    Accumulator Stack Pointer (SP) Peripheral Clock Control Register Refer to the Peripheral Registers A96G140/A96G148 has five types of reset sources as shown in the followings: External RESETB  Power ON RESET (POR)  WDT Overflow Reset (In the case of WDTEN = `1`) ...

  • Page 225: Figure 114. Fast Vdd Rising Time

    A96G140/A96G148 User’s manual 17. Reset Fast VDD Rise Time, max. 30.0V/ms nPOR BIT Overflows (Internal Signal) BIT Starts Internal RESETB Oscillation Figure 114. Fast VDD Rising Time Slow VDD Rise Time, min. 0.15V/ms =1.4V (Typ) nPOR BIT Overflows (Internal Signal)

  • Page 226: Figure 116. Configuration Timing When Power-On

    17. Reset A96G140/A96G148 User’s manual Counting for configure option read start after POR is released Internal nPOR PAD RESETB “H” LVR_RESETB .. 27 28 BIT (for Configure) 00 01 02 03 BIT (for Reset) 1us X 256 X 28h = about 10ms...

  • Page 227: External Resetb Input

    A96G140/A96G148 User’s manual 17. Reset Table 42. Boot Process Description Process Description Remarks ① No Operation 0.7V to 0.9V  LSIRC (128KHz) ON  ② 1st POR level Detection About 1.1V to 1.3V ③ (LSIRC 128KHz/32)x32h Delay Slew Rate >= 0.025V/ms ...

  • Page 228: Low Voltage Reset Process

    17.4 Low voltage reset process A96G140/A96G148 has an On-chip brown-out detection circuit (BOD) for monitoring VDD level during operation by comparing it to a fixed trigger level. Trigger level for the BOD can be selected by configuring LVRVS[3:0] bits to be 1.62V, 1.68V, 1.77V, 1.88V,2.00V, 2.13V, 2.28V, 2.46V, 2.67V, 2.80V, 3.04V, 3.20V, 3.55V, 3.75V, 3.99V, 4.25V.

  • Page 229: Figure 120. Block Diagram Of Lvr

    A96G140/A96G148 User’s manual 17. Reset External VDD Brown Out Detector LVRVS[3:0] RESET_BODB (BOD) LVREN LVRF CPU Write (Low Voltage Reset Flag) SCLK (System CLK) nPOR Figure 120. Block Diagram of LVR Internal 16ms RESETB t < 16ms 16ms Internal RESETB...

  • Page 230: Lvi Block Diagram

    17. Reset A96G140/A96G148 User’s manual “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB ..27 28 BIT (for Config) 00 01 02 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms...

  • Page 231: Register Map

    A96G140/A96G148 User’s manual 17. Reset 17.6 Register Map Table 43. Reset Operation Register Map Name Address Direction Default Description RSTFR Reset Flag Register LVRCR Low Voltage Reset Control Register LVICR Low Voltage Indicator Control Register 17.7 Reset Operation Register Description RSTFR (Reset Flag Register): E8H –...
  • Page 232 17. Reset A96G140/A96G148 User’s manual LVRCR (Low Voltage Reset Control Register): D8H – – – LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN – – – Initial value: 00H LVRVS[3:0] LVR Voltage Select LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description 1.61V 1.68V 1.77V 1.88V 2.00V 2.13V...
  • Page 233 A96G140/A96G148 User’s manual 17. Reset LVICR (Low Voltage Indicator Control Register): 86H – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – Initial value: 00H LVIF Low Voltage Indicator Flag Bit No detection Detection LVIEN LVI Enable/Disable Disable Enable LVIVS[3:0]...

  • Page 234: 18 Memory Programming

    18. Memory programming A96G140/A96G148 User’s manual 18 Memory programming A96G140/A96G148 has flash memory to which a program can be written, erased, and overwritten while mounted on the board. Serial ISP mode is supported. Flash of A96G140/A96G148 features the followings: Flash Size : 64Kbytes ...
  • Page 235 A96G140/A96G148 User’s manual 18. Memory programming FEMR (Flash Mode Register): 1020H FSEL ERASE PBUFF OTPE FEEN Initial value: 00H FSEL Select flash memory. Deselect flash memory Select flash memory Enable program or program verify mode with VFY Disable program or program verify mode...
  • Page 236 18. Memory programming A96G140/A96G148 User’s manual FECR (Flash Control Register): 1021H EXIT1 EXIT0 WRITE READ nFERST nPBRST Initial value: 03H Enable flash bulk erase mode Disable bulk erase mode of Flash memory Enable bulk erase mode of Flash memory EXIT[1:0] Exit from program mode.
  • Page 237 A96G140/A96G148 User’s manual 18. Memory programming FESR (Flash Status Register): 1022H PEVBSY REMAPSI REMAP- ROMINT WMODE EMODE VMODE Initial value: 80H PEVBSY Operation status flag. It is cleared automatically when operation starts. Operations are program, erase or verification Busy (Operation processing)
  • Page 238 18. Memory programming A96G140/A96G148 User’s manual FEARM (Flash address middle Register): 1029H ARM7 ARM6 ARM5 ARM4 ARM3 ARM2 ARM1 ARM0 Initial value: 00H ARM[7:0] Flash address middle FEARH (Flash address high Register): 1028H ARH7 ARH6 ARH5 ARH4 ARH3 ARH2 ARH1...

  • Page 239: Figure 124. Read Device Internal Checksum (Full Size)

    A96G140/A96G148 User’s manual 18. Memory programming Start OCD mode entry Write(OCD_CODE, 0xF555, 0xAA) Set checksum read mode Write(OCD_CODE, 0xFAAA, 0x55) Write(OCD_CODE, 0xF555, 0xA5) Write(OCD_XDATA, FEMR, 0x81) Set auto verify mode Write(OCD_CODE, FETR, 0x08) Write(OCD_CODE, FECR, 0x07) Busy check (FESR[7]=L) Read 24 - bit Checksum (H, M, L)

  • Page 240: Figure 125. Read Device Internal Checksum (User Define Size)

    18. Memory programming A96G140/A96G148 User’s manual Start OCD mode entry Write(OCD_CODE, 0xF555, 0xAA) Set checksum read mode Write(OCD_CODE, 0xFAAA, 0x55) Write(OCD_CODE, 0xF555, 0xA5) Write(OCD_XDATA, FEARM,Start Address Upper) Set auto verify mode Write(OCD_XDATA, FEARL,Start Address Lower) Write(OCD_XDATA, FEARM1,End Address Upper) Write(OCD_XDATA, FEARL1,End Address Lower)

  • Page 241: Memory Map

    A96G140/A96G148 User’s manual 18. Memory programming FETCR (Flash Time control Register): 1023H TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Initial value: 00H TCR[7:0] Flash Time control Program and erase time is controlled by setting FETCR register. Program and erase timer uses 10-bit counter.

  • Page 242: Serial In-System Program Mode

    18. Memory programming A96G140/A96G148 User’s manual FFFFh pgm/ers/vfy Code Memory (PROGRAM) 0000h Figure 126. Flash Memory Map PAGE ADDRESS WORD ADDRESS Program Memory 0x3FF Page 1023 0x3F Page 1022 0x00 Page 1 Page 0 * Page buffer size: 64Bytes 0x000 Figure 127.

  • Page 243: Figure 128. The Sequence Of Page Program And Erase Of Flash Memory

    A96G140/A96G148 User’s manual 18. Memory programming Configuration (This Configuration is just used for follow description) FEMR[4] & [1] FEMR[5] & [1] FEMR[2] FECR[6] FECR[7] ERASE&VFY PGM&VFY OTPE Master Reset Page Buffer Reset Page Buffer Load (0X00H) Page Buffer Reset Page Buffer Load...

  • Page 244: Figure 129. The Sequence Of Bulk Erase Of Flash Memory

    18. Memory programming A96G140/A96G148 User’s manual Master Reset Page Buffer Reset Page Buffer Load Configuration Reg.<0> Erase Erase Latency (500us) Page Buffer Reset Configuration Reg.<0> clear Reg.<6:5> setting Cell Read Pass/Fail? Figure 129. The Sequence of Bulk Erase of Flash Memory Flash read ①...
  • Page 245 A96G140/A96G148 User’s manual 18. Memory programming ④ Enter program/erase mode sequence. NOTE2 Write 0xAA to 0xF555. Write 0x55 to 0xFAAA. Write 0xA5 to 0xF555. NOTES: Refer to how to enter ISP mode. Command sequence to activate Flash write/erase mode. It is composed of sequentially writing data of Flash memory.
  • Page 246 18. Memory programming A96G140/A96G148 User’s manual ⑨ Insert one NOP operation ⑩ Read FESR until PEVBSY is 1. ⑪ Repeat ② to ⑧ until all pages are erased Flash bulk erase mode ① Enable program mode. ② Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 ③...
  • Page 247 A96G140/A96G148 User’s manual 18. Memory programming ⑥ Set page address. FEARH:FEARM:FEARL=20’hx_xxxx ⑦ Set FETCR. ⑧ Start program. FECR:0000_1011 ⑨ Insert one NOP operation ⑩ Read FESR until PEVBSY is 1. Flash OTP area erase mode ① Enable program mode. ② Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 ③...

  • Page 248: Mode Entrance Method Of Isp Mode

    18. Memory programming A96G140/A96G148 User’s manual ③ Read data from Flash Flash page buffer read ① Enable program mode. ② Select page buffer. FEMR:1000_1001 ③ Read data from Flash. Summary of flash program/erase mode Table 46. Operation Mode Operation mode...

  • Page 249: Security

    18.5 Security A96G140/A96G148 provides Lock bits which can be left un-programmed (“0”) or can be programmed (“1”) to obtain the additional features listed in table 47. The Lock bit can only be erased to “0” with the bulk erase command and a value of more than 0x40 at FETCR.
  • Page 250 Enable Protection RSTS Select RESETB pin Disable RESETB pin(P55) Enable RESETB pin Note: Code write protection and Vector area protection are disabled at OCD Mode. CONFIGURE OPTION 1: ROM Address 0000H (A96G140/A96G148 64K Series) – – – – PAEN PASS2...

  • Page 251: Electrical Characteristics

    A96G140/A96G148 User’s manual 19. Electrical characteristics 19 Electrical characteristics 19.1 Absolute maximum ratings Table 49. Absolute Maximum Ratings Parameter Symbol Rating Unit Note Supply Voltage -0.3~+6.5 – Normal Voltage Pin Voltage on any pin with respect to VSS 0.3~VDD+0.3 0.3~VDD+0.3 42.5...

  • Page 252: Recommended Operating Conditions

    19. Electrical characteristics A96G140/A96G148 User’s manual 19.2 Recommended operating conditions Table 50. Recommended Operating Conditions =-40°C ~ 85°C) Parameter Symbol Conditions Unit Operating Voltage = 32 ~ 38kHz Sub Crystal – = 4 ~10MHz Main – Crystal = 4 ~12MHz –...

  • Page 253: Power On Reset Characteristics

    A96G140/A96G148 User’s manual 19. Electrical characteristics 19.4 Power on reset characteristics Table 52. Power-on Reset Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit RESET Release Level – – 1.32 – VDD Voltage Rising Time – 0.05 –...

  • Page 254: High Internal Rc Oscillator Characteristics

    19. Electrical characteristics A96G140/A96G148 User’s manual 19.6 High internal RC oscillator characteristics Table 54. High Internal RC Oscillator Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit Frequency = 2.0 – 5.5V – – Tolerance – = 0°C to +50°C With –...

  • Page 255: Dc Characteristics

    A96G140/A96G148 User’s manual 19. Electrical characteristics 19.8 DC characteristics Table 56. DC Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f = 16MHz) Parameter Symbol Conditions Unit Input High All input pins 0.7VDD – Voltage Input All input pins –...

  • Page 256: Ac Characteristics

    19. Electrical characteristics A96G140/A96G148 User’s manual (IDLE) Table 56. DC Characteristics (continued) = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f = 16MHz) Parameter Symbol Conditions Unit = 8MHz, VDD= 5V±10% – 16MHz, VDD= HSIRC 5V±10% STOP @ WDT on, VDD= –...

  • Page 257: Usart Characteristics

    A96G140/A96G148 User’s manual 19. Electrical characteristics External 0.8VDD Interrupt 0.2VDD RESETB 0.2VDD ECWL ECWH 0.8VDD 0.2VDD Figure 131. AC Timing 19.10 USART characteristics Table 58. USART Characteristics = -40°C ~ +85°C, VDD=1.8V ~ 5.5V, f =8MHz) Parameter Symbol Unit Serial port clock cycle time...

  • Page 258: Spi0/1 Characteristics

    19. Electrical characteristics A96G140/A96G148 User’s manual HIGH Figure 132. Waveform for USART Timing Characteristics Shift Clock Data Out Data In Valid Valid Valid Valid Valid Valid Valid Valid Figure 133. Timing Waveform for the USART Module 19.11 SPI0/1 characteristics Table 59. SPI0/1/2 Characteristics =-40°C–...

  • Page 259: Uart0/1 Characteristics

    A96G140/A96G148 User’s manual 19. Electrical characteristics (Output/Input) 0.8VDD SCKn (CPOLn=0) (Output/Input) 0.2VDD SCKL SCKH SCKn (CPOLn=1) (Output/Input) MISOn/MOSIn (Data Input) MISOn/MOSIn (Data Output) NOTE: n =0, 1 and 2 Figure 134. SPI0/1/2 Timing 19.12 UART0/1 characteristics Table 60. UART0/1 Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, f...

  • Page 260: I2C0/1 Characteristics

    19. Electrical characteristics A96G140/A96G148 User’s manual Table 60. UART0/1 Characteristics (continued) =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, f =8MHz) Parameter Symbol Unit Input data hold after clock rising – – edge Serial port clock High, Low level 1280 HIGH width HIGH Figure 135.

  • Page 261: Data Retention Voltage In Stop Mode

    A96G140/A96G148 User’s manual 19. Electrical characteristics Table 61. I2C0/1 Characteristics (continued) =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Parameter Symbol Standard Mode High-Speed Mode Unit Bus Free Time – – Start Condition Setup Time – – STSU Start Condition Hold Time –...

  • Page 262: Internal Flash Rom Characteristics

    19. Electrical characteristics A96G140/A96G148 User’s manual Idle Mode (Watchdog Timer Active) Stop Mode Normal Operating Mode Data Retention DDDR Execution of STOP Instruction 0.8V INT Request WAIT NOTE: tWAIT is the same as (the selected bit overflow of BIT) X 1/(BIT Clock) Figure 138.

  • Page 263: Input/Output Capacitance

    A96G140/A96G148 User’s manual 19. Electrical characteristics Table 63. Internal Flash Rom Characteristics (continued) =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Condition Unit Page Buffer Reset Time – – – Flash Programming – – – Frequency Endurance –...

  • Page 264: Sub-Clock Oscillator Characteristics

    19. Electrical characteristics A96G140/A96G148 User’s manual XOUT Figure 140. Crystal/Ceramic Oscillator XOUT External Open Clock Source Figure 141. External Clock 19.18 Sub-clock oscillator characteristics Table 66. Sub Clock Oscillator Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Oscillator Parameter Condition Unit...

  • Page 265: Main Oscillation Stabilization Characteristics

    A96G140/A96G148 User’s manual 19. Electrical characteristics SXIN SXOUT External Open Clock Source Figure 143. External Clock 19.19 Main oscillation stabilization characteristics Table 67. Main Oscillation Stabilization Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Oscillator Parameter Unit Crystal fx > 4MHz, VDD = 2.7V ~ 5.5V, –...

  • Page 266: Operating Voltage Range

    19. Electrical characteristics A96G140/A96G148 User’s manual Table 68. Sub Oscillation Stabilization Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Oscillator Parameter Unit Crystal =-40°C ~+85°C – – = 25°C External Clock SXIN input high and low width – 0.8VDD SXIN 0.2VDD Figure 145.

  • Page 267: Recommended Circuit And Layout

    A96G140/A96G148 User’s manual 19. Electrical characteristics 19.22 Recommended circuit and layout This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the PCB layout. 0.1uF DC Po we r 0.1uF VS S The MCU power line (VDD and VSS)

  • Page 268: Figure 148. Run (Idd1) Current

    19. Electrical characteristics A96G140/A96G148 User’s manual 2.250 2.200 2.150 2.100 2.050 2.000 1.950 1.900 1.850 -40℃ 25℃ 85℃ 5.5V 3.3V 1.8V Figure 148. RUN (IDD1) Current 1.300 1.250 1.200 1.150 1.100 1.050 1.000 0.950 -40℃ 25℃ 85℃ 5.5V 3.3V 1.8V...

  • Page 269: Figure 150. Stop1 (Idd3) Current

    A96G140/A96G148 User’s manual 19. Electrical characteristics 5.00 4.00 3.00 2.00 1.00 0.00 -40℃ 25℃ 85℃ 5.5V 3.3V 1.8V Figure 150. STOP1 (IDD3) Current 2.50 2.00 1.50 1.00 0.50 0.00 -40℃ 25℃ 85℃ 5.5V 3.3V 1.8V Figure 151. Stop2 (IDD4) Current...

  • Page 270: 20 Development Tools

    ABOV semiconductor does not provide any compiler for A96G140/A96G148. It is recommended to consult a compiler provider. Since A96G140/A96G148 has Mentor 8051 as its core, and ROM is smaller than 64Kbytes in size, a developer can use any standard 8051 compiler of other providers.

  • Page 271: Programmers

    A96G140/A96G148 User’s manual 20. Development tools 20.3 Programmers 20.3.1 E-PGM+ E-PGM+ USB is a single programmer. A user can program A96G140/A96G148 directly using the E- PGM+. DSDA DSCL Figure 153. E-PGM+ (Single Writer) and Pinouts 20.3.2 OCD emulator OCD emulator allows a user to write code on the device too, since OCD debugger supports ISP (In System Programming).

  • Page 272: Flash Programming

    20.4 Flash programming Program memory of A96G140/A96G148 is a flash type. This flash ROM is accessed through four pins such as DSCL, DSDA, VDD, and VSS in serial data format. For more information about flash memory programming, please refer to chapter 18.

  • Page 273: On-Chip Debug System

    On-chip debug system A96G140/A96G148 supports On-chip debug (OCD) system. We recommend to develop and debug program with A96G1 series. On-chip debug system of A96G140/A96G148 can be used for programming the non-volatile memories and on-chip debugging. Detail descriptions for programming via the OCD interface can be found in this section.

  • Page 274: Two-Pin External Interface

    20. Development tools A96G140/A96G148 User’s manual Table 70. OCD Features Two wire external interface 1 for serial clock input  1 for bi-directional serial data bus  Debugger accesses All internal peripherals  Internal data RAM  Program Counter ...

  • Page 275: Figure 157. 10-Bit Transmission Packet

    A96G140/A96G148 User’s manual 20. Development tools Basic transmission packet 10-bit packet transmission using two-pin interface.  1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge.  Parity is even of ‘1’ for 8-bit data in transmitter.  Receiver generates acknowledge bit as ‘0’ when transmission for 8-bit data and its parity ...

  • Page 276: Figure 158. Data Transfer On Twin Bus

    20. Development tools A96G140/A96G148 User’s manual Figure 158. Data Transfer on Twin Bus Figure 159. Bit Transfer on Serial Bus Figure 160. Start and Stop Condition...

  • Page 277: Figure 161. Acknowledge On Serial Bus

    A96G140/A96G148 User’s manual 20. Development tools Figure 161. Acknowledge on Serial Bus Figure 162. Clock Synchronization during Wait Procedure Connection of transmission Two-pin interface connection uses open-drain (wire-AND bidirectional I/O).

  • Page 278: Figure 163. Connection Of Transmission

    20. Development tools A96G140/A96G148 User’s manual Figure 163. Connection of Transmission...

  • Page 279: 21 Package Information

    A96G140/A96G148 User’s manual 21. Package information 21 Package information This chapter provides A96G140/A96G148 package information. 21.1 48 LQFP package information Figure 164. 48 LQFP Package Outline...

  • Page 280: Table 71. 48 Lqfp Package Mechanical Data

    21. Package information A96G140/A96G148 User’s manual Table 71. 48 LQFP Package Mechanical Data Symbol Min. Nom. Max. ― ― 1.60 ― 0.05 0.15 1.35 1.40 1.45 0.17 0.22 0.27 0.17 0.20 0.23 ― 0.09 0.20 ― 0.09 0.16 8.80 9.00 9.20...

  • Page 281: 44 Mqfp Package Information

    A96G140/A96G148 User’s manual 21. Package information 21.2 44 MQFP package information Figure 165. 44 MQFP Package Outline...

  • Page 282: Table 72. 44 Mqfp Package Mechanical Data

    21. Package information A96G140/A96G148 User’s manual Table 72. 44 MQFP Package Mechanical Data Symbol Min. Nom. Max. ― ― 2.45 ― 0.00 0.25 1.80 2.10 2.20 ― 0.28 0.45 0.28 0.35 0.41 ― 0.11 0.23 0.11 0.15 0.19 12.90 13.20 13.50...

  • Page 283: 32 Lqfp Package Information

    A96G140/A96G148 User’s manual 21. Package information 21.3 32 LQFP package information Figure 166. 32 LQFP Package Outline...

  • Page 284: Table 73. 32 Lqfp Package Mechanical Data

    21. Package information A96G140/A96G148 User’s manual Table 73. 32 LQFP Package Mechanical Data Symbol Min. Nom. Max. ― ― 1.60 ― 0.05 0.20 1.35 1.40 1.45 0.30 0.37 0.42 0.30 0.35 0.40 ― 0.09 0.20 ― 0.09 0.16 8.80 9.00 9.20...

  • Page 285: 32 Sop Package Information

    A96G140/A96G148 User’s manual 21. Package information 21.4 32 SOP package information Figure 167. 32 SOP Package Outline...

  • Page 286: Table 74. 32 Sop Package Mechanical Data

    21. Package information A96G140/A96G148 User’s manual Table 74. 32 SOP Package Mechanical Data Symbol Min. Nom. Max. ― ― 1.60 ― 0.05 0.20 1.35 1.40 1.45 0.30 0.37 0.42 0.30 0.35 0.40 ― 0.09 0.20 ― 0.09 0.16 8.80 9.00 9.20...

  • Page 287: Sop Package Information

    A96G140/A96G148 User’s manual 21. Package information 21.5 28 SOP package information Figure 168. 28 SOP Package Outline...

  • Page 288: Table 75. 28 Sop Package Mechanical Data

    21. Package information A96G140/A96G148 User’s manual Table 75. 28 SOP Package Mechanical Data Symbol Min. Nom. Max. ― ― 2.80 ― 0.10 0.30 ― ― 2.05 ― 0.31 0.54 ― 0.27 0.50 ― 0.10 0.33 ― 0.10 0.30 ― 17.40 18.20...

  • Page 289: 28 Tssop Package Information

    A96G140/A96G148 User’s manual 21. Package information 21.6 28 TSSOP package information Figure 169. 28 TSSOP Package Outline...

  • Page 290: Table 76. 28 Tssop Package Mechanical Data

    21. Package information A96G140/A96G148 User’s manual Table 76. 28 TSSOP Package Mechanical Data Symbol Min. Nom. Max. ― ― 1.20 ― 0.05 0.15 0.80 1.00 1.05 ― 0.19 0.30 0.19 0.22 0.25 ― 0.09 0.20 ― 0.09 0.16 9.60 9.70 9.80...

  • Page 291: 22 Ordering Information

    A96G140/A96G148 User’s manual 22. Ordering information 22 Ordering information Table 77. A96G140/A96G148 Device Ordering Information Device FLASH XRAM IRAM I/O PORT Package name A96G140CL 64Kbytes 2304bytes 256bytes 16inputs 48 LQFP A96G148CL 32Kbytes A96G140SQ 16inputs 44 MQFP A96G148SQ A96G140KN 12inputs 32 LQFP...

  • Page 292: Figure 170. A96G140/A96G148 Device Numbering Nomenclature

    44 pin 32 pin Package Type 28 pin LQFP 0.5mm Pin Pitch LQFP 0.8mm Pin Pitch MQFP Temperature TSSOP none -40°C ~ 85°C -40°C ~ 105°C Product Information Internal management code Packing Tape & Reel Figure 170. A96G140/A96G148 Device Numbering Nomenclature...

  • Page 293: Appendix

    A96G140/A96G148 User’s manual Appendix Appendix Instruction table Instructions are either1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
  • Page 294 Appendix A96G140/A96G148 User’s manual Table 78. Instruction Table (continued) LOGICAL Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data...
  • Page 295 A96G140/A96G148 User’s manual Appendix Table 78. Instruction Table (continued) DATA TRANSFER Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7 MOV A,#data...
  • Page 296 Appendix A96G140/A96G148 User’s manual Table 78. Instruction Table (continued) BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit...
  • Page 297 A96G140/A96G148 User’s manual Appendix Table 78. Instruction Table (continued) BRANCHING Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...
  • Page 298 Appendix A96G140/A96G148 User’s manual Table 78. Instruction Table (continued) MISCELLANEOUS Mnemonic Description Bytes Cycles Hex code No operation ADDITIONAL INSTRUCTIONS (selected through EO[7:4]) Mnemonic Description Bytes Cycles Hex code MOVC M8051W/M8051EW-specific instruction @(DPTR++),A supporting software download into program memory TRAP...

  • Page 299: Revision History

    A96G140/A96G148 User’s manual Revision history Revision history Date Revision Description 2019.08.05 1.00 First creation 2019.10.02 1.10 Added Receive Time Out (RTO) and 0% Error Baud Rate  features of USART on page Fixed device name from A96G140/A96G148KL  A96G140/A96G148KN on page 19.

  • Page 300: Worldwide Distributors And Sales Offices

    Worldwide distributors and sales offices A96G140/A96G148 User’s manual Worldwide Distributors and Sales Offices Distributors Korea Finechips Greenchips Co., Ltd. Tel: +82-31-702-1558 Tel: +82-31-370-0900 Tel: +82-2-573-0061 Fax: +82-31-702-3057 Fax: +82-31-371-2401 Fax: +82-2-573-0067 www.finechips.com www.fstc.co.kr www.greenchips.co.kr IDEA INC SAEMICHIPS Co., Ltd. SJ Solution...
  • Page 301 (office equipment, communication equipment, measuring equipment, domestic electrification, etc.). Please make sure that you consult with us before you use these ABOV Semiconductor products in equipment that require high quality and / or reliability, and in equipment that could have major impact to personal safety (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types of safety devices, etc.) ABOV Semiconductor cannot accept liability for any damage that may...

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