Abov A96G174 User Manual
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Abov A96G174 User Manual

16 mhz 8-bit a96g174 microcontroller 8 kbyte flash memory, 12-bit adc, 3 timers, usart, i2c, window wdt
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8 Kbyte Flash memory, 12-bit ADC, 3 Timers, USART, I2C,

Introduction

This user's manual targets application developers who use A96G174/A96S174 for their specific needs.
It provides complete information of how to use A96G174/A96S174 device. Standard functions and
blocks including corresponding register information of A96G174/A96S174 are introduced in each
chapter, while instruction set is in Appendix.
A96G174/A96S174 is based on M8051 core, and provides standard features of 8051 such as 8-bit ALU,
PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit data bus
and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost-effective solutions:
8Kbytes of FLASH, 256bytes of IRAM, and 256bytes of XRAM
Basic interval timer, watchdog timer, and 8/16-bit timer/counter
16-bit PPG output, 8-bit PWM output, 16-bit PWM output, USART, I2C, and 12-bit ADC
On-chip POR, LVR, LVI
On-chip oscillator and clock circuitry.
As a field proven best seller, A96G174/A96S174 introduces rich features such as excellent noise
immunity, code optimization, cost effectiveness, and so on.

Reference document

A96G174/A96S174 programming tools and manuals released by ABOV: They are available at
ABOV website, www.abovsemi.com.
SDK-51 User's guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel's 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentor website:
16 MHz 8-bit A96G174 Microcontroller
https://www.mentor.com/products/ip/peripheral/microcontroller/
Global Top Smart MCU Innovator, ABOV Semiconductor
www.abovsemi.com
A96G174/A96S174
User's Manual
Window WDT
User's Manual Version 1.11

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Summary of Contents for Abov A96G174

  • Page 1: Introduction

    A96G174/A96S174 are introduced in each chapter, while instruction set is in Appendix. A96G174/A96S174 is based on M8051 core, and provides standard features of 8051 such as 8-bit ALU, PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit data bus and 2x16-bit address bus, and 8/11/16-bit operations.

  • Page 2: Table Of Contents

    A96G174/A96S174 User’s manual Contents Introduction.............................. 1 Reference document ..........................1 Description ........................... 11 Device overview ........................11 A96G174/A96S174 block diagram..................13 Pinouts and pin description ......................14 Pinouts ..........................14 Pin description........................20 Port structures ..........................23 Central Processing Unit(CPU) ..................... 25 Architecture and registers ....................
  • Page 3 A96G174/A96S174 User’s manual Contents Interrupt enable accept timing ..................... 63 Interrupt service routine address ..................63 7.10 Saving/restore general purpose registers ................63 7.11 Interrupt timing ........................64 7.12 Interrupt register overview ....................64 7.12.1 Interrupt Enable Register (IE, IE1, and IE2) ............64 7.12.2 Interrupt Priority Register (IP and IP1) ..............
  • Page 4 Contents A96G174/A96S174 User’s manual 12.3 ADC operation........................110 12.4 Register map ........................111 12.5 Register description ......................111 I2C .............................. 114 13.1 Block diagram ........................114 13.2 Bit transfer ......................... 115 13.3 Start/ repeated start/ stop ....................115 13.4 Data transfer ........................116 13.5 Acknowledge ........................
  • Page 5 A96G174/A96S174 User’s manual Contents 16.1 Reset block diagram ......................159 16.2 Power on reset ........................160 16.3 External RESETB input ..................... 162 16.4 Low voltage reset process ....................164 16.5 LVI block diagram ......................165 16.6 Register Map ........................166 16.7 Reset Operation Register Description ................
  • Page 6 A96G174/A96S174 User’s manual List of figures Figure 1. A96G174/A96S174 Block Diagram ..................13 Figure 2. A96G174 20TSSOP Pin Assignment ..................14 Figure 3. A96S174 20TSSOP pin assignment ..................15 Figure 4. A96G174 20SOP Pin Assignment ..................16 Figure 5. A96G174 20QFN Pin Assignment ..................17 Figure 6.
  • Page 7 A96G174/A96S174 User’s manual List of figures Figure 48. 16-bit Timer 1 Block Diagram ....................95 Figure 49. 16-bit Timer/Counter Mode of Timer 2 ................100 Figure 50. 16-bit Timer/Counter Mode Operation Example ..............100 Figure 51. 16-bit Capture Mode of Timer 2 ..................101 Figure 52.
  • Page 8 List of figures A96G174/A96S174 User’s manual Figure 98. The Sequence of Bulk Erase of Flash Memory ..............178 Figure 99. ISP Mode ........................... 182 Figure 100. Configuration of the Extended Stack Pointer ..............190 Figure 101. OCD 1 and OCD 2 Connector Pin Diagram ..............192 Figure 102.
  • Page 9 List of tables List of tables Table 1. A96G174/A96S174 Device Features and Peripheral Counts ..........11 Table 1. A96G174/A96S174 Device Features and Peripheral Counts (continued) ......12 Table 2. Normal Pin Description ......................20 Table 2. Normal Pin Description (continued)..................21 Table 2.
  • Page 10 List of tables A96G174/A96S174 User’s manual Table 43. Debug Feature by Series ....................191 Table 44. OCD 1 and OCD 2 Pin Description ..................192 Table 45. OCD Features ........................193 Table 46. Pins for Flash Programming ....................200 Table 47. Instruction Table ........................204 Table 47.

  • Page 11: Description

    A96G174/A96S174 User’s manual 1. Description 1 Description A96G174/A96S174 is an advanced CMOS 8-bit microcontroller with 8Kbytes of FLASH. This is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. Device overview In this section, features of A96G174/A96S174 and peripheral counts are introduced.

  • Page 12: Table 1. A96G174/A96S174 Device Features And Peripheral Counts (Continued)

    1. Description A96G174/A96S174 User’s manual Table 1. A96G174/A96S174 Device Features and Peripheral Counts (continued) Peripherals Description Reset Power  Reset release level: 1.32V reset Low voltage  5 levels detect reset  1.61/1.77/2.13/2.46/3.56V Low voltage indicator  3 levels detect ...

  • Page 13: A96G174/A96S174 Block Diagram

    A96G174/A96S174 User’s manual 1. Description A96G174/A96S174 block diagram In this section, A96G174/A96S174 device with peripherals is described in a block diagram. Flash CORE XRAM M8051 256B IRAM 256B General purpose I/O In-system programming 18 ports normal I/O Power control Power on reset...

  • Page 14: Pinouts And Pin Description

    2. Pinouts and pin description A96G174/A96S174 User’s manual 2 Pinouts and pin description Pinouts and pin descriptions of A96G174/A96S174 device are introduce in the following sections. Pinouts P21/AN2 SS/DSDA/EC0/AN3/P00 P20/AN1/T1O/PWM1O SDA/DSCL/AN4/P01 SCL/RESETB/EINT0/P02 P17/AN0/PWM1OB T0O/PWM0O/AN5/P03 A96G174FR P16/AN14 (20TSSOP) T2O/PWM2O/AN6/P04 P15/AN13/EINT2/RXD(MISO) SCK/AN7/P05...

  • Page 15: Figure 3. A96S174 20Tssop Pin Assignment

    A96G174/A96S174 User’s manual 2. Pinouts and pin description XCK/EC1/EINT1/AN11/P13 P12/(T0O)/(PWM0O)/(SS) P11/(T2O)/(PWM2O)/(SDA) TXD(MOSI)/AN12/P14 P10/AN10 RXD(MISO)/EINT2/AN13/P15 RESETB/AN14/P16 P07/AN9/(T1O)/(PWM1O)MISO(RXD) PWM1OB/AN0/P17 A96S174FR P06/AN8/(PWM1OB)/MOSI(TXD) (20TSSOP) T1O/PWM1O/AN1/P20 P05/AN7/SCK P04/AN6/T2O/PWM2O P03/AN5/T0O/PWM0O P02/EITN0/SCL P01/DSCL/AN4/SDA SS/DSDA/EC0/AN3/P00 NOTES: The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P21 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 20-pin package is used.

  • Page 16: Figure 4. A96G174 20Sop Pin Assignment

    The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P22 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 20-pin package is used. Figure 4. A96G174 20SOP Pin Assignment...

  • Page 17: Figure 5. A96G174 20Qfn Pin Assignment

    The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P22 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 20-pin package is used. Figure 5. A96G174 20QFN Pin Assignment...

  • Page 18: Figure 6. A96S174 20Qfn Pin Assignment

    2. Pinouts and pin description A96G174/A96S174 User’s manual P10/AN10 RESETB/AN14/P16 PWM1OB/AN0/P17 P07/AN9/T1O/PWM1O/MISO(RXD) A96S174FU P06/AN8/(PWM1OB)/MOSI(TXD) T1O/PWM1O/AN1/P20 (20QFN) P05/AN7/SCK P04/AN6/T2O/PWM2O NOTES: The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P21 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 20-pin package is used.

  • Page 19: Figure 7. A94G174 16Sopn Pin Assignment

    A96G174/A96S174 User’s manual 2. Pinouts and pin description P21/AN2 SS/DSDA/EC0/AN3/P00 P20/AN1/T1O/PWM1O SDA/DSCL/AN4/P01 A96G174AE P17/AN0/PWM1OB SCL/RESETB/EINT0/P02 (16SOPN) T0O/PWM0O/AN5/P03 P16/AN14 T2O/PWM2O/AN6/P04 P15/AN13/EINT2/RXD(MISO) SCK/AN7/P05 P14/AN12/TXD(MOSI) MOSI(TXD)/(PWM1OB)/AN8/P06 P13/AN11/EINT1/EC1/XCK NOTE: The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA Figure 7. A94G174 16SOPN Pin Assignment...

  • Page 20: Pin Description

    Pull-up DSCL OCD debugger clock I2C data signal 4(12) 1(9) P02* IOUS Port 0 bit 2 Input/output RESETB A96G174 only, Reset pin Pull-up EINT0 External interrupt input ch-0 I2C clock signal 5(13) 2(10) P03* IOUS Port 0 bit 3 Input/output...

  • Page 21: Table 2. Normal Pin Description (Continued)

    A96G174/A96S174 User’s manual 2. Pinouts and pin description Table 2. Normal Pin Description (continued) Remark Pin no. PIN Name Description 20TSSOP 20QFN 16SOPN 9(17) 6(14) Timer 1 interval output PWM1O Timer 1 PWM output 10(18) 7(15) P10* IOUS Port 1 bit 0 Input/output...

  • Page 22: Table 2. Normal Pin Description (Continued)

    2. Pinouts and pin description A96G174/A96S174 User’s manual Table 2. Normal Pin Description (continued) Remark Pin no. PIN Name Description 20TSSOP 20QFN 16SOPN 20(6) 15(3) P20* IOUS Port 2 bit 0 Input/output ADC input ch-1 Timer 1 interval output PWM1O...

  • Page 23: Port Structures

    A96G174/A96S174 User’s manual 3. Port structures 3 Port structures In this chapter, two port structures are introduced in Figure 8 & Figure 9 regarding general purpose I/O port and external interrupt I/O port respectively. Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V)

  • Page 24: Figure 9. External Interrupt I/O Port

    3. Port structures A96G174/A96S174 User’s manual LevelShift (1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE DIRECTION REGISTER SUB-FUNC DIRECTION R(400Ω) EXTERNAL INTERRUPT POLARITY INTERRUPT ENABLE EDGE FLAG CLEAR PORTx INPUT...

  • Page 25: Central Processing Unit(Cpu)

    A96G174/A96S174 User’s manual 4. Central Processing Unit ABOV 4 Central Processing Unit(CPU) Central Processing Unit (CPU) of A96G174/A96S174 is based on Mentor Graphics M8051EW core, which offers improved code efficiency and high performance. Architecture and registers Figure 10 shows a block diagram of the M8051EW architecture. As shown in the figure, the M8051EW supports both Program Memory and External Data Memory.
  • Page 26 4. Central Processing Unit ABOV A96G174/A96S174 User’s manual Debug support (OCD and OCD II):  The M8051EW offers a Debug Mode together with a set of dedicated debug signals which can be used by external debug hardware, OCD and OCD II, to provide start/stop program execution in response to both hardware and software triggers, single step operation and program execution tracing.

  • Page 27: Addressing

    A96G174/A96S174 User’s manual 4. Central Processing Unit ABOV Addressing The M8051EW supports six types of addressing modes as listed below: Direct addressing mode: In this mode, the operand is specified by the 8-bit address field. Only internal data and SFRs can be accessed using this mode.

  • Page 28: Instruction Set

    4. Central Processing Unit ABOV A96G174/A96S174 User’s manual Instruction set An instruction is a single operation of a processor that is defined by the instruction set. The M8051EW uses the instruction set of 8051 that is broadly classified into five functional categories:...
  • Page 29 A96G174/A96S174 User’s manual 4. Central Processing Unit ABOV External data memory: Data can be moved between the accumulator and the external memory  location in one of two addressing modes. In 8-bit addressing mode, the external location is addressed by either R0 or R1; in 16-bit addressing mode, the location is addressed by the DPTR.

  • Page 30: Memory Organization

    Internal data memory (IRAM) is 256bytes and it includes the stack area. External data memory (XRAM) is 256bytes. Program memory A 16-bit program counter is capable of addressing up to 64Kbytes, and A96G174/A96S174 has just 8Kbytes program memory space. Figure 11 shows a map of the lower part of the program memory.

  • Page 31: Data Memory

    A96G174/A96S174 User’s manual 5. Memory organization NOTE: The 8Kbytes includes the Interrupt Vector Region. Figure 11. Program Memory Map Data memory Internal data memory space is divided into three blocks, which are generally referred to as lower 128bytes, upper 128bytes, and SFR space. Internal data memory addresses are always one byte wide, which implies an address space of 256bytes.

  • Page 32: Figure 12. Data Memory Map

    5. Memory organization A96G174/A96S174 User’s manual All of the bytes in the lower 128bytes can be accessed by either direct or indirect addressing. The upper 128bytes of RAM can only be accessed by indirect addressing. These spaces are used for data RAM and stack.

  • Page 33: Figure 13. Lower 128Bytes Of Ram

    A96G174/A96S174 User’s manual 5. Memory organization 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58...

  • Page 34: External Data Memory

    5. Memory organization A96G174/A96S174 User’s manual External data memory A96G174/A96S174 has 256bytes of XRAM and XSFR. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. 107FH Extended Special Function Registers...

  • Page 35: Sfr Map

    A96G174/A96S174 User’s manual 5. Memory organization SFR map 5.4.1 SFR map summary Table 3. SFR Map Summary ― Reserved M8051 compatible 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 0F8H – – – UBAUD UDATA – 0F0H 0E8H RSTFR I2CSAR...

  • Page 36: Table 4. Xsfr Map Summary

    5. Memory organization A96G174/A96S174 User’s manual Table 4. XSFR Map Summary 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 1078H – – – – – – – – 1070H – – – – – – – – 1068H – –...

  • Page 37: Sfr Map

    A96G174/A96S174 User’s manual 5. Memory organization 5.4.2 SFR map Table 5. SFR Map Address Function Symbol @Reset P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1...

  • Page 38: Table 5. Sfr Map (Continued)

    5. Memory organization A96G174/A96S174 User’s manual Table 5. SFR Map (continued) Address Function Symbol @Reset P0 Direction Register P0IO Extended Operation Register – – – – External Interrupt Polarity 0 Low Register EIPOL0L External Interrupt Polarity 0 High Register EIPOL0H...

  • Page 39: Table 5. Sfr Map (Continued)

    A96G174/A96S174 User’s manual 5. Memory organization Table 5. SFR Map (continued) Address Function Symbol @Reset External Interrupt Flag 0 Register EIFLAG0 Timer 2 Control Low Register T2CRL – – Timer 2 Control High Register T2CRH – – – – Timer 2 A Data Low Register...

  • Page 40: Table 6. Xsfr Map

    5. Memory organization A96G174/A96S174 User’s manual Table 6. XSFR Map Address Function Symbol @Reset 1010H Watch Dog Timer Clear Register WDTC 1011H Watch Dog Timer Status Register WDTSR 1012H Watch Dog Timer Count H Register WDTCNTH 1013H Watch Dog Timer Count L Register...

  • Page 41: Compiler Compatible Sfr

    A96G174/A96S174 User’s manual 5. Memory organization 5.4.3 Compiler compatible SFR ACC (Accumulator Register): E0H Initial value: 00H Accumulator B (B Register): F0H Initial value: 00H B Register SP (Stack Pointer): 81H Initial value: 07H Stack Pointer DPL (Data Pointer Register Low): 82H...
  • Page 42 5. Memory organization A96G174/A96S174 User’s manual DPH1 (Data Pointer Register High 1): 85H DPH1 Initial value: 00H DPH1 Data Pointer High 1 PSW (Program Status Word Register): D0H Initial value: 00H Carry Flag Auxiliary Carry Flag General Purpose User-Definable Flag...

  • Page 43: 6 I/O Ports

    6. I/O ports 6 I/O ports A96G174/A96S174 has 3 groups of I/O ports (P0 ~ P2). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements.

  • Page 44: Register Map

    6. I/O ports A96G174/A96S174 User’s manual 6.1.7 Register Map Table 7. Port Register Map Name Address Direction Default Description P0 Data Register P0IO P0 Direction Register P0PU P0 Pull-up Resistor Selection Register P0OD P0 Open-drain Selection Register P0DB P0 De-bounce Enable Register...

  • Page 45: P0 Port

    A96G174/A96S174 User’s manual 6. I/O ports P0 port 6.2.1 P0 port description P0 is an 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register (P0OD).
  • Page 46 6. I/O ports A96G174/A96S174 User’s manual P0DB (P0 De-bounce Enable Register): DEH DBCLK1 DBCLK0 P07DB P06DB P05DB P04DB P03DB P02DB Initial value: 00H DBCLK[1:0] Configure De-bounce Clock of Port DBCLK1 DBCLK0 Description fx/1 fx/4 fx/4096 LSIRC (128kHz) P07DB Configure De-bounce of P07 Port...
  • Page 47 A96G174/A96S174 User’s manual 6. I/O ports P0FSRH (Port 0 Function Selection High Register): D3H P0FSRH7 P0FSRH6 P0FSRH5 P0FSRH4 P0FSRH3 P0FSRH2 P0FSRH1 P0FSRH0 Initial value: 00H P0FSRH[7:6] P07 Function Select P0FSRH7 P0FSRH6 Description I/O Port RXD/MISO Function T1O/PWM1O AN9 Function P0FSRH[5:4]...
  • Page 48 6. I/O ports A96G174/A96S174 User’s manual P0FSRL (Port 0 Function Selection Low Register): D2H P0FSRL7 P0FSRL6 P0FSRL5 P0FSRL4 P0FSRL3 P0FSRL2 P0FSRL1 P0FSRL0 Initial value: 00H P0FSRL[7:6] P03 Function Select P0FSRL7 P0FSRL6 Description I/O Port Reserved T0O/PWM0O Function AN5 Function P0FSRL[5:4]...

  • Page 49: P1 Port

    A96G174/A96S174 User’s manual 6. I/O ports P1 port 6.3.1 P1 port description P1 is an 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P1DB), P1 pull-up resistor selection register (P1PU), and P1 open-drain selection register (P1OD).
  • Page 50 6. I/O ports A96G174/A96S174 User’s manual P1DB (P1 De-bounce Enable Register): DFH P17DB P16DB P15DB P14DB P13DB P12DB P11DB P10DB Initial value: 00H P17DB Configure De-bounce of P17 Port Disable Enable P16DB Configure De-bounce of P16 Port Disable Enable P15DB...
  • Page 51 A96G174/A96S174 User’s manual 6. I/O ports P1FSRH (Port 1 Function Selection High Register): D5H P1FSRH7 P1FSRH6 P1FSRH5 P1FSRH4 P1FSRH3 P1FSRH2 P1FSRH1 P1FSRH0 Initial value: 00H P1FSRH[7:6] P17 Function Select P1FSRH7 P1FSRH6 Description I/O Port Reserved PWM1OB Function AN0 Function P1FSRH[5:4]...
  • Page 52 6. I/O ports A96G174/A96S174 User’s manual P1FSRL (Port 1 Function Selection Low Register): D4H P1FSRL7 P1FSRL6 P1FSRL5 P1FSRL4 P1FSRL3 P1FSRL2 P1FSRL1 P1FSRL0 Initial value: 00H P1FSRL[7:6] P13 Function Select P1FSRL7 P1FSRL6 Description I/O Port(EC1/EINT1 function possible when input) XCK Function...

  • Page 53: P2 Port

    A96G174/A96S174 User’s manual 6. I/O ports P2 port 6.4.1 P2 port description P2 is an 8-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU) andP2 open-drain selection register (P2OD).Refer to the port function selection registers for the P2 function selection.
  • Page 54 6. I/O ports A96G174/A96S174 User’s manual P2FSR (Port 2 Function Selection Register): D6H P2FSR3 P2FSR2 P2FSR1 P2FSR0 Initial value: 00H P2FSR[3:2] P21 Function Select P2FSR3 P2FSR2 Description I/O Port reserved Reserved AN2 Function P2FSR[1:0] P20 Function Select P2FSR1 P2FSR0 Description...

  • Page 55: Interrupt Controller

    A96G174/A96S174 User’s manual 7. Interrupt controller 7 Interrupt controller A96G174/A96S174 supports up to 14 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. In addition, they have four levels of priority assigned to themselves.

  • Page 56: External Interrupt

    7. Interrupt controller A96G174/A96S174 User’s manual Interrupt Highest Lowest Group 0 (Bit0) Interrupt 0 Interrupt 6 Interrupt 12 Interrupt 18 Highest 1 (Bit1) Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 2 (Bit2) Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20...

  • Page 57: Pin Change Interrupt

    A96G174/A96S174 User’s manual 7. Interrupt controller Pin Change Interrupt The pin change interrupt on P1 ports receive the both edge (Falling-edge and Rising-edge) interrupt request as shown in Figure 17. Also each pin change interrupt source had enable setting bits. The FLAG (flag register) register provides the status of ports change interrupts.

  • Page 58: Block Diagram

    7. Interrupt controller A96G174/A96S174 User’s manual Block diagram EIPOL EI FLAG.1 EINT0 FLAG0 EI FLAG.2 EINT1 Priority High FLAG1 EINT2 FLAG2 FLAG3 Level 0 USART RX Level 1 Level 2 Release Level 3 USART TX Stop/Sleep T0 Match T1 Match...

  • Page 59: Interrupt Vector Table

    7. Interrupt controller Interrupt vector table Interrupt controller of A96G174/A96S174 supports 14 interrupt sources as shown in Table 8. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.

  • Page 60: Interrupt Sequence

    7. Interrupt controller A96G174/A96S174 User’s manual Interrupt sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack.

  • Page 61: Effective Timing After Controlling Interrupt Bit

    A96G174/A96S174 User’s manual 7. Interrupt controller Effective timing after controlling interrupt bit Case A in Figure 20 shows the effective time after controlling Interrupt Enable Registers (IE, IE1, and IE2). Interrupt Enable Register command After executing IE set/clear, enable register is effective.

  • Page 62: Multi-Interrupt

    7. Interrupt controller A96G174/A96S174 User’s manual Multi-interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. However, for special features, multi-interrupt processing can be executed by software.

  • Page 63: Interrupt Enable Accept Timing

    A96G174/A96S174 User’s manual 7. Interrupt controller Interrupt enable accept timing System Max. 4 Machine Cycle 4 Machine Cycle Clock Interrupt goes Interrupt Interrupt Processing active latched Interrupt Routine : LCALL & LJMP Figure 23. Interrupt Response Timing Diagram Interrupt service routine address...

  • Page 64: Interrupt Timing

    7. Interrupt controller A96G174/A96S174 User’s manual 7.11 Interrupt timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-bit interrupt Vector INT_VEC PROGA NOTE: Variable x and n of a command cycle CLPx imply the followings: ...

  • Page 65: External Interrupt Flag Register (Eiflag0 And Eiflag1)

    A96G174/A96S174 User’s manual 7. Interrupt controller After a reset, IP and IP1 are cleared to ‘00H’. If interrupts have the same priority level, lower number interrupt is served first. 7.12.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1) External Interrupt Flag 0 Register (EIFLAG0) and External Interrupt Flag 1 Register (EIFLAG1) are set to ‘1’...

  • Page 66: Interrupt Register Description

    7. Interrupt controller A96G174/A96S174 User’s manual 7.12.6 Interrupt register description IE (Interrupt Enable Register): A8H – INT5E INT4E INT3E INT2E INT1E INT0E – Initial value: 00H Enable or Disable All Interrupt bits All Interrupt disable All Interrupt enable INT5E Enable or Disable USART TX Interrupt...
  • Page 67 A96G174/A96S174 User’s manual 7. Interrupt controller IE1 (Interrupt Enable Register 1): A9H – – INT11E INT10E INT9E INT8E INT7E INT6E – – Initial value: 00H INT11E Enable or Disable ADC Interrupt Disable Enable INT10E Enable or Disable LVI Interrupt Disable...
  • Page 68 7. Interrupt controller A96G174/A96S174 User’s manual IP1 (Interrupt Priority Register 1): F8H – – IP15 IP14 IP13 IP12 IP11 IP10 – – Initial value: 00H IP[5:0], IP1[5:0] Select Interrupt Group Priority IP1x Description level 0 (lowest) level 1 level 2...

  • Page 69: Clock Generator

    — HSIRC OSC/16 (2MHz) — HSIRC OSC/32 (1MHz) — HSIRC OSC/64 (0.5MHz) Internal LSIRC oscillator (128kHz)  Clock generator block diagram In this section, a clock generator of A96G174/A96S174 is described in a block diagram. IRCS[2:0] System SCLK Clock Gen. (Core, System,...

  • Page 70: Register Map

    8. Clock generator A96G174/A96S174 User’s manual Register map Table 10. Clock Generator Register Map Name Address Direction Default Description SCCR System and Clock Control Register OSCCR Oscillator Control Register Register description SCCR (System and Clock Control Register): 8AH – –...

  • Page 71: Basic Interval Timer

    9. Basic interval timer 9 Basic interval timer A96G174/A96S174 has a free running 8-bit Basic Interval Timer (BIT). BIT generates the time base for watchdog timer counting, and provides a basic interval timer interrupt (BITIFR). BIT of A96G174/A96S174 features the followings: During Power On, BIT gives a stable clock generation time ...

  • Page 72: Bit Register Description

    9. Basic interval timer A96G174/A96S174 User’s manual BIT register description BITCNT (Basic Interval Timer Counter Register): 8CH BITCNT7 BITCNT6 BITCNT5 BITCNT4 BITCNT3 BITCNT2 BITCNT1 BITCNT0 Initial value: 00H BITCNT[7:0] BIT Counter BITCR (Basic Interval Timer Control Register): 8BH BITIFR BITCK2...

  • Page 73: 10 Watchdog Timer

    A96G174/A96S174 User’s manual 10. Watchdog timer 10 Watchdog timer The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. The watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.

  • Page 74: Setting Window Open Period Of Watchdog Timer

    10. Watchdog timer A96G174/A96S174 User’s manual 10.1 Setting window open period of watchdog timer 1. WDT window open period is selected as 50%. Counting Overflow Start time Window close(50%) Window open(50%) Counter clear & Start again, Watchdog reset is occurred, if 96H is written to WDTC.

  • Page 75: Wdt Block Diagram

    A96G174/A96S174 User’s manual 10. Watchdog timer Table 12. Watch Dog Timer Register Map Setting of window open period Window close period Window open period 50%, WINDOW[1:0]=00b & WDTPDON = 1 75%, WINDOW[1:0]=01b & WDTPDON = 1 100%, WINDOW[1:0]=10b & WDTPDON = 1 WDTCNT = “0000H”...

  • Page 76: Register Description

    10. Watchdog timer A96G174/A96S174 User’s manual 10.4 Register description WDTCNTH (Watch Dog Timer Counter High Register: Read Case): 1012H WDTCNT 15 WDTCNT 14 WDTCNT 13 WDTCNT 12 WDTCNT11 WDTCNT 10 WDTCNT 9 WDTCNT 8 Initial value: 00H WDTCNT[15:8] WDT Counter...
  • Page 77 A96G174/A96S174 User’s manual 10. Watchdog timer WDTIDR (Watch Dog Timer Identification Register: Write Case): 8EH WDTID7 WDTID 6 WDTID 5 WDTID 4 WDTID 3 WDTID 2 WDTID 1 WDTID 0 Initial value: 00H WDTDR[7:0] WDT Identification for a WDTCR Others No identification value.

  • Page 78: Timer 0/1/2

    11. Timer 0/1/2 A96G174/A96S174 User’s manual 11 Timer 0/1/2 11.1 Timer 0 An 8-bit timer 0 consists of a multiplexer, a timer 0 counter register, a timer 0 data register, a timer 0 capture data register and a timer 0 control register (T0CNT, T0DR, T0CDR, T0CR).

  • Page 79: Figure 31. 8-Bit Timer/Counter Mode For Timer 0

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 ADDRESS : B2H T0CR T0EN T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC INITIAL VALUE: 0000_0000B Match signal Clear fx/2 T0CC fx/4 8-bit Timer 0 Counter fx/8 INT_ACK T0CNT(8Bit) fx/32 Clear fx/128 fx/512 Match To interrupt...

  • Page 80: 8-Bit Pwm Mode

    11. Timer 0/1/2 A96G174/A96S174 User’s manual 11.1.2 8-bit PWM mode Timer 0 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T0O/PWM0O pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting the T0O/PWM0O function by PxFSR bits.

  • Page 81: Figure 34. Pwm Output Waveforms In Pwm Mode For Timer 0

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 PWM Mode(T0MS = 01b) Set T0EN Timer 0 clock T0CNT T0DR T0 Overflow Interrupt 1. T0DR = 4AH T0PWM T0 Match Interrupt 2. T0DR = 00H T0PWM T0 Match Interrupt 3. T0DR = FFH...

  • Page 82: 8-Bit Capture Mode

    11. Timer 0/1/2 A96G174/A96S174 User’s manual 11.1.3 8-bit capture mode Timer 0 capture mode is set by configuring T0MS[1:0] as ‘1x’. Clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode has, and the interrupt occurs when T0CNT equals to T0DR.

  • Page 83: Figure 36. Input Capture Mode Operation For Timer 0

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 Figure 36. Input Capture Mode Operation for Timer 0 Figure 37. Express Timer Overflow in Capture Mode...

  • Page 84: Timer 0 Block Diagram

    11. Timer 0/1/2 A96G174/A96S174 User’s manual 11.1.4 Timer 0 block diagram fx/2 fx/4 8-bit Timer 0 Counter Match signa l fx/8 Clear INT_ACK T0CNT (8Bit) fx/32 T0CC Clear fx/128 Clear fx/512 Match To in terr upt T0EN T0IFR block fx/2048...

  • Page 85: Register Description

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 11.1.6 Register description T0CNT (Timer 0 Counter Register): B3H T0CNT7 T0CNT6 T0CNT5 T0CNT4 T0CNT3 T0CNT2 T0CNT1 T0CNT0 Initial value: 00H T0CNT[7:0] T0 Counter T0DR (Timer 0 Data Register): B4H T0DR7 T0DR6 T0DR5 T0DR4 T0DR3...
  • Page 86 11. Timer 0/1/2 A96G174/A96S174 User’s manual T0CR (Timer 0 Control Register): B2H – T0EN T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC – Initial value: 00H T0EN Control Timer 0 Timer 0 disable Timer 0 enable T0MS[1:0] Control Timer 0 Operation Mode...

  • Page 87: Timer 1

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 11.2 Timer 1 A 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register high/low and timer 1 control register high/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH, T1CRL, T1DRH, T1DRL).

  • Page 88: Figure 39. 16-Bit Timer/Counter Mode Of Timer 1

    11. Timer 0/1/2 A96G174/A96S174 User’s manual The external clock (EC1) counts up the timer at the rising edge. If the EC1 is selected as a clock source by T1CK[2:0], EC1 port should be set to the input port by PxIO bit.

  • Page 89: 16-Bit Capture Mode

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 11.2.2 16-bit capture mode It uses an internal/external clock as a clock source. Basically, the 16-bit timer 1 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T1CNTH/T1CNTL is equal to T1ADRH/T1ADRL.

  • Page 90: Figure 42. Input Capture Mode Operation For Timer1

    11. Timer 0/1/2 A96G174/A96S174 User’s manual T1BDRH/L Load T1CNTH/L Value Count Pulse Period Up-count TIME EINT1 PIN Interrupt Request Interrupt Interval Period (FLAG1) Figure 42. Input Capture Mode Operation for timer1 FFFF FFFF T1CNTH/L Interrupt Request (T1IFR) EINT11 PIN Interrupt...

  • Page 91: 16-Bit Ppg Mode

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 11.2.3 16-bit PPG mode TIMER 1 has a PPG (Programmable Pulse Generation) function. In PPG mode, T1O/PWM1O pin outputs up to 16-bit resolution PWM output. For this function, T1O/PWM1O pin must be configured as a PWM output by setting PxFSR.

  • Page 92: Figure 45. 16-Bit Ppg Mode Operation Example

    11. Timer 0/1/2 A96G174/A96S174 User’s manual Repeat Mode(T1MS = 11b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock Counter T1ADRH/L T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L PWM1O B Match A Match 2. T1BDRH/L >= T1ADRH/L...

  • Page 93: 16-Bit Complementary Pwm Mode (Dead Time)

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 11.2.4 16-bit Complementary PWM mode (Dead Time) The timer 1 has a Complementary PWM function. The complementary PWM output function operates when T1BEN is set. In PPG mode, PWM1O/PWM1OB pin outputs up to 16-bit resolution complementary PWM output.

  • Page 94: Figure 47. 16-Bit Complementary Pwm Mode Timing Chart For Timer 1

    11. Timer 0/1/2 A96G174/A96S174 User’s manual Repeat Mode(T1MS = 11b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock T1_Counter ···· ···· ···· TZ_Counter T1ADRH/L T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L, T1CDRH/L(2), T1DDRH/L(5), PWM1O B Match...

  • Page 95: 16-Bit Timer 1 Block Diagram

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 11.2.5 16-bit timer 1 block diagram In this section, a 16-bit timer 1 is described in a block diagram. 16-bit A Data Re gister 16-bit D Data Register T1ADRH/T1ADRL T1DDRH/T1DDRL Reload Reload Buffer Reg ister A...

  • Page 96: Register Description

    11. Timer 0/1/2 A96G174/A96S174 User’s manual 11.2.7 Register description T1ADRH (Timer 1 A data High Register): BDH T1ADRH7 T1ADRH6 T1ADRH5 T1ADRH4 T1ADRH3 T1ADRH2 T1ADRH1 T1ADRH0 Initial value: FFH T1ADRH[7:0] T1 A Data High Byte T1ADRL (Timer 1 A Data Low Register): BCH...
  • Page 97 A96G174/A96S174 User’s manual 11. Timer 0/1/2 T1DDRH (Timer 1 D Data High Register): DCH T1DDRH7 T1DDRH6 T1DDRH5 T1DDRH4 T1DDRH3 T1DDRH2 T1DDRH1 T1DDRH0 Initial value: FFH T1DDRH[7:0] T1 D Data High Byte T1DDRL (Timer 1 D Data Low Register): DBH T1DDRL7...
  • Page 98 11. Timer 0/1/2 A96G174/A96S174 User’s manual T1CRL (Timer 1ControlLow Register): BAH T1CK2 T1CK1 T1CK0 T1IFR T1BPOL T1POL T1ECE T1CNTR Initial value: 00H T1CK[2:0] Select Timer 1 clock source. fx is main system clock frequency T1CK2 T1CK1 T1CK0 Description fx/2048 fx/64...

  • Page 99: Timer 2

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 11.3 Timer 2 A 16-bit timer 2 consists of a multiplexer, timer 2 A data high/low register, timer 2 B data high/low register and timer 2 control high/low register (T2ADRH, T2ADRL, T2BDRH, T2BDRL, T2CRH, and T2CRL).

  • Page 100: Figure 49. 16-Bit Timer/Counter Mode Of Timer 2

    11. Timer 0/1/2 A96G174/A96S174 User’s manual ADDRESS:C3H – – – – T2EN T2MS1 T2MS0 T2CC T2CRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:C2H – – T2CK2 T2CK1 T2CK0 T2IFR T2POL T2CNTR T2CRL INITIAL VALUE : 0000_0000B – –...

  • Page 101: 16-Bit Capture Mode

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 11.3.2 16-bit capture mode Timer 2 capture mode is set by configuring T2MS[1:0] as ‘01’. It uses an internal clock as a clock source. Basically, the 16-bit timer 2 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T2CNTH/T2CNTL is equal to T2ADRH/T2ADRL.

  • Page 102: Figure 52. 16-Bit Capture Mode Operation Example

    11. Timer 0/1/2 A96G174/A96S174 User’s manual Figure 52. 16-bit Capture Mode Operation Example Figure 53. Express Timer Overflow in Capture Mode...

  • Page 103: 16-Bit Ppg Mode

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 11.3.3 16-bit PPG mode TIMER 2 has a PPG (Programmable Pulse Generation) function. In PPG mode, T2O/PWM2O pin outputs up to 16-bit resolution PWM output. For this function, T2O/PWM2O pin must be configured as a PWM output by setting PxFSR.

  • Page 104: Figure 55. 16-Bit Ppg Mode Operation Example

    11. Timer 0/1/2 A96G174/A96S174 User’s manual Repeat Mode(T2MS = 11b) and "Start High"(T2POL = 0b). Clear and Start Set T2EN Timer 2 clock Counter T2ADRH/L T2 Interrupt 1. T2BDRH/L(5) < T2ADRH/L PWM2O B Match A Match 2. T2BDRH/L >= T2ADRH/L...

  • Page 105: 16-Bit Timer 2 Block Diagram

    A96G174/A96S174 User’s manual 11. Timer 0/1/2 11.3.4 16-bit timer 2 block diagram In this section, a 16-bit timer 2 is described in a block diagram. 16-bit A Data Register T2ADRH/T2ADRL A Match Reload T2CC T2CK[2:0] T2EN INT_ACK Buffer Register A...

  • Page 106: Register Description

    11. Timer 0/1/2 A96G174/A96S174 User’s manual 11.3.6 Register description T2ADRH (Timer 2 A data High Register): C5H T2ADRH7 T2ADRH6 T2ADRH5 T2ADRH4 T2ADRH3 T2ADRH2 T2ADRH1 T2ADRH0 Initial value: FFH T2ADRH[7:0] T2 A Data High Byte T2ADRL (Timer 2 A Data Low Register): C4H...
  • Page 107 A96G174/A96S174 User’s manual 11. Timer 0/1/2 T2CRH (Timer 2ControlHigh Register): C3H – – – – T2EN T2MS1 T2MS0 T2CC – – – – Initial value: 00H T2EN Control Timer 2 Timer 2 disable Timer 2 enable (Counter clear and start)

  • Page 108: 12 12-Bit Adc

    A96G174/A96S174 User’s manual 12 12-bit ADC Analog-to-digital converter (ADC) of A96G174/A96S174 allows conversion of an analog input signal to corresponding 12-bit digital value. This A/D module has eight analog inputs. Output of the multiplexer becomes input into the converter which generates the result through successive approximation.

  • Page 109: Block Diagram

    A96G174/A96S174 User’s manual 12. 12-bit ADC 12.2 Block diagram In this section, the 12-bit ADC is described in a block diagram, and an analog input pin and a power pin with capacitors respectively are introduced. TRIG[2:0] ADSEL[3:0] ADST (Select one input pin...

  • Page 110: Adc Operation

    12. 12-bit ADC A96G174/A96S174 User’s manual 12.3 ADC operation In this section, control registers and align bits are introduced in Figure 59, and ADC operation flow sequence is introduced in Figure 60. Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8...

  • Page 111: Register Map

    A96G174/A96S174 User’s manual 12. 12-bit ADC Figure 60. ADC Operation Flow Sequence 12.4 Register map Table 20. ADC Register Map Name Address Direction Default Description ADCDRH A/D Converter Data High Register ADCDRL A/D Converter Data Low Register ADCCRH A/D Converter Control High Register...
  • Page 112 12. 12-bit ADC A96G174/A96S174 User’s manual ADCDRL (A/D Converter Data Low Register): 9EH ADDM3 ADDM2 ADDM1 ADDM0 ADDL7 ADDL6 ADDL5 ADDL4 ADDL3 ADDL2 ADDL1 ADDL0 Initial value: xxH ADDM[3:0] MSB align, A/D Converter Low Data (4-bit) ADDL[7:0] LSB align, A/D Converter Low Data (8-bit)
  • Page 113 A96G174/A96S174 User’s manual 12. 12-bit ADC ADCCRL (A/D Converter Counter Low Register): 9CH STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value: 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable...

  • Page 114: 13 I2C

    13. I2C A96G174/A96S174 User’s manual 13 I2C The I C is one of industrial standard serial communication protocols, and which uses 2 bus lines Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL lines are open-drain output, each line needs pull-up resistor.

  • Page 115: Bit Transfer

    A96G174/A96S174 User’s manual 13. I2C 13.2 Bit transfer The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high.

  • Page 116: Data Transfer

    13. I2C A96G174/A96S174 User’s manual 13.4 Data transfer Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first.

  • Page 117: Synchronization/ Arbitration

    A96G174/A96S174 User’s manual 13. I2C The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave.

  • Page 118: Figure 66. Clock Synchronization During Arbitration Procedure

    13. I2C A96G174/A96S174 User’s manual Wait High Start High Counting Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT SCLn Figure 66. Clock Synchronization during Arbitration Procedure Arbitration Process Device 1 loses Device1 outputs not adapted Arbitration High Device1...

  • Page 119: Block Operation

    A96G174/A96S174 User’s manual 13. I2C 13.7 Block operation The I2C block as peripheral design is independently operating with main CPU operation. The operation of I2C block does a byte unit of I2C frame. After finishing a byte operation (transmit/receive data and clock) on I2C bus system, I2C block generate I2C interrupt for next byte operation.

  • Page 120: I2C Interrupt Service

    13. I2C A96G174/A96S174 User’s manual ③ Depended on I2C devices, it shall define I2C SCL max clock and write the value of SCL Low /high time and SDA hold time on I2CSCLLR, I2CSCLHR, I2CSDAHR as following diagram I2CSDAHR sdah I2CSCLHR...

  • Page 121: Master Transmitter

    A96G174/A96S174 User’s manual 13. I2C I2C Interrupt occur at after the following cases As I2C Master Device — Sending a byte on I2CDR register after setting Start bit. ( GCALL interrupt ) — Sending a byte on I2CDR register after write to I2CSR. ( TEND interrupt ) —...
  • Page 122 13. I2C A96G174/A96S174 User’s manual I2C Interrupt Service If(Master Mode) and (TMODE) If( ACK and GCALL or ACK and TEND ) If ( Not End of Data ) I2CDR = NEXT DATA; // load target Salve Address I2CSR = 0xFF;...

  • Page 123: Slave Receiver

    A96G174/A96S174 User’s manual 13. I2C 13.7.4 Slave Receiver I2C Block that is under IIC enable and INTEN enable on I2CMR is monitoring I2C bus lines for being a start condition and self-address with I2CSAD. To have both signals of start signal and getting self- address, I2C block generate I2C interrupt with the status bits (SSEL, BUSY RXACK, SLAVE mode ...)

  • Page 124: Register Map

    13. I2C A96G174/A96S174 User’s manual 13.8 Register map Table 21. Register Map Name Address Direction Default Description I2CMR I2C Mode Control Register I2CSR I2C Status Register I2CSCLLR SCL Low Period Register I2CSCLHR SCL High Period Register I2CSDAHR SDA Hold Time Register...

  • Page 125: I2C Register Description

    A96G174/A96S174 User’s manual 13. I2C 13.9 I2C register description I2CMR (I2C Mode Control Register): E1H IICEN RESET INTEN ACKEN MASTER STOP START Initial value: 00H This is interrupt flag bit. No interrupt is generated or interrupt is cleared An interrupt is generated...
  • Page 126 13. I2C A96G174/A96S174 User’s manual I2CSR (I2C Status Register): E2H GCALL TEND STOP SSEL MLOST BUSY TMODE RXACK Initial value: 00H GCALL This bit has different meaning depending on whether I2C is master or slave. Note 1) When I2C is a master, this bit represents whether it received AACK (Address ACK) from slave.
  • Page 127 A96G174/A96S174 User’s manual 13. I2C I2CSCLLR (SCL Low Period Register): E3H SCLL7 SCLL6 SCLL5 SCLL4 SCLL3 SCLL2 SCLL1 SCLL0 Initial value: 3FH SCLL[7:0] This register defines the LOW period of SCL when I2C operates in master mode. The base clock is SCLK, the system clock, and the period is calculated by the formula : tSCLK×...
  • Page 128 13. I2C A96G174/A96S174 User’s manual I2CSAR (I2C Slave Address Register): E9H SLA7 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 GCALLEN Initial value: 00H SLA[7:1] These bits configure the slave address of this I2C module when I2C operates in slave mode. GCALLEN This bit decides whether I2C allows general call address or not when I2C operates in slave mode.

  • Page 129: 14 Usart

    14. USART 14 USART Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. USART of A96G174/A96S174 features the followings: Full Duplex Operation (Independent Serial Receive and Transmit Registers)  Asynchronous or Synchronous Operation ...

  • Page 130: Block Diagram

    14. USART A96G174/A96S174 User’s manual 14.1 Block diagram UBAUD SCLK Baud Rate Generator Master Clock Sync Logic Control UMSEL[1:0] Rx Interrupt RXD2/ MISO2 Clock Control Recovery Data Recovery UMSEL1&UMSEL0 DOR/PE/FE UDATA[0] Master Checker (Rx) UDATA[1] Stop bit UMSEL0 (Rx) UPM0...

  • Page 131: Clock Generation

    A96G174/A96S174 User’s manual 14. USART 14.2 Clock generation Clock generation logic generates a base clock signal for the Transmitter and the Receiver. USART supports four modes of clock operation such as Normal Asynchronous mode, Double Speed Asynchronous mode, Master Synchronous mode, and Slave Synchronous mode.

  • Page 132: External Clock (Xck)

    14. USART A96G174/A96S174 User’s manual 14.3 External clock (XCK) External clocking is used by the synchronous or SPI slave modes of operation. External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must then pass through an edge detector before it can be used by the Transmitter and Receiver.

  • Page 133: Data Format

    A96G174/A96S174 User’s manual 14. USART 14.5 Data format A serial frame is defined to consist of one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. USART supports all 30 combinations of the followings as a valid frame format.

  • Page 134: Parity Bit

    14. USART A96G174/A96S174 User’s manual 14.6 Parity bit Parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive-or is inverted. The parity bit is located between St + bits and first stop bit of a serial frame.

  • Page 135: Parity Generator

    A96G174/A96S174 User’s manual 14. USART UDRE flag indicates whether the transmit buffer is ready to be loaded with new data. This bit is set when the transmit buffer is empty and cleared when the transmit buffer contains transmission data which has not yet been moved into the shift register. And also this flag can be cleared by writing ‘0’ to this bit field.

  • Page 136: Receiver Flag And Interrupt

    14. USART A96G174/A96S174 User’s manual Even if there’s 2nd stop bit in the frame, the 2nd stop bit is ignored by the Receiver. That is, receiving the first stop bit means that a complete serial frame is present in the receiver shift register and contents of the shift register are to be moved into the receive buffer.

  • Page 137: Parity Checker

    A96G174/A96S174 User’s manual 14. USART 14.8.3 Parity checker If Parity bit is enabled (UPM[1]=1), Parity Checker calculates parity of data bits of incoming frames and compares the result with the parity bit of the received serial frame. 14.8.4 Disabling receiver In contrast to Transmitter, disabling the Receiver by clearing RXE bit makes the Receiver inactive immediately.

  • Page 138: Figure 73. Sampling Of Data And Parity Bit

    14. USART A96G174/A96S174 User’s manual As described above, when the Receiver clock is synchronized to the start bit, the data recovery can begin. Data recovery process is almost similar to the clock recovery process. The data recovery logic samples 16 times for each incoming bits for Normal mode and 8 times for Double Speed mode. It uses the samples 8, 9, and 10 to decide data value for Normal mode, and the samples 4, 5, and 6 for Double Speed mode.

  • Page 139: Spi Mode

    A96G174/A96S174 User’s manual 14. USART 14.9 SPI mode The USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. Full duplex, three-wire synchronous data transfer  Master or Slave operation ...

  • Page 140: Figure 75. Spi Clock Formats When Ucpha = 0

    14. USART A96G174/A96S174 User’s manual (UCPOL=0) (UCPOL=1) SAMPLE MOSI MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 75. SPI Clock Formats when UCPHA = 0 When UCPHA=0, the slave begins to drive its MISO2 output with the first data bit value when SS goes to active low.

  • Page 141: Figure 76. Spi Clock Formats When Ucpha = 1

    A96G174/A96S174 User’s manual 14. USART (UCPOL=0) (UCPOL=1) SAMPLE MOSI2 MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISO2 /SS2 OUT (MASTER) /SS2 IN (SLAVE) Figure 76. SPI Clock Formats when UCPHA = 1 When UCPHA=1, the slave begins to drive its MISO2 output when SS2 goes active low, but the data is not defined until the first XCK edge.

  • Page 142: Receiver Time Out (Rto)

    14. USART A96G174/A96S174 User’s manual 14.10 Receiver time out (RTO) This USART system supports the time out function. This function generates an interrupt when stop bits are not in RX line during URTOC setting value. RTO Count stops in RXD signal live state and RTO Clear/Start is executed by stop bit recognition.

  • Page 143: Register Map

    A96G174/A96S174 User’s manual 14. USART 14.11 Register map Table 25. USART Register Map Name Address Direction Default Description UCTRL1 USART Control 1 Register UCTRL2 USART Control 2 Register UCTRL3 USART Control 3 Register UCTRL4 1018H USART Control 4 Register USTAT...

  • Page 144: Register Description

    14. USART A96G174/A96S174 User’s manual 14.12 Register description UCTRL1 (USART Control 1 Register) CBH USIZE1 USIZE0 UMSEL1 UMSEL0 UPM1 UPM0 USIZE2 UCPOL UDORD UCPHA Initial value: 00 UMSEL[1:0] Selects operation mode of USART UMSEL1 UMSEL0 Operating Mode Asynchronous Mode (Normal UART)
  • Page 145 A96G174/A96S174 User’s manual 14. USART UCTRL2 (USART Control 2 Register) CCH UDRIE TXCIE RXCIE WAKEIE USARTEN Initial value: 00 UDRIE Interrupt enable bit for USART Data Register Empty. Interrupt from UDRE is inhibited (use polling) When UDRE is set, request an interrupt TXCIE Interrupt enable bit for Transmit Complete.
  • Page 146 14. USART A96G174/A96S174 User’s manual UCTRL3 (USART Control 3 Register) CDH MASTER LOOPS DISXCK SPISS USBS Initial value: 00 MASTER Selects master or slave in SPI or Synchronous mode operation and controls the direction of XCK pin. Slave mode operation and XCK is input pin.
  • Page 147 A96G174/A96S174 User’s manual 14. USART UCTRL4 (USART Control 4 Register) 1018H RTOEN RTO_FLAG FPCREN AOVSSEL AOVSEN Initial value: 00 RTOEN Enable receiver time out. Disable Enable RTO_FLAG This bit is set when RTO count overflows. This flag can generate an RTO interrupt.
  • Page 148 14. USART A96G174/A96S174 User’s manual USTAT (USART Status Register) CFH UDRE WAKE SOFTRST Initial value: 80 UDRE The UDRE flag indicates if the transmit buffer (UDATA) is ready to be loaded with new data. If UDRE is ‘1’, it means the transmit buffer is empty and can hold one or two new data.
  • Page 149 A96G174/A96S174 User’s manual 14. USART UBAUD (USART Baud-Rate Generation Register) FCH UBAUD7 UBAUD6 UBAUD5 UBAUD4 UBAUD3 UBAUD2 UBAUD1 UBAUD0 Initial value: FF UBAUD [7:0] The value in this register is used to generate internal baud rate in asynchronous mode or to generate XCK clock in synchronous or SPI mode.
  • Page 150 14. USART A96G174/A96S174 User’s manual RTOCH (Receiver Time Out Counter High Register) 101AH RTOCH7 RTOCH6 RTOCH5 RTOCH4 RTOCH3 RTOCH2 RTOCH1 RTOCH0 Initial value: 00 RTOCL (Receiver Time Out Counter Low Register) 101BH RTOCL7 RTOCL6 RTOCL5 RTOCL4 RTOCL3 RTOCL2 RTOCL1 RTOCL0...

  • Page 151: Baud Rate Settings (Example)

    A96G174/A96S174 User’s manual 14. USART 14.13 Baud rate settings (example) Table 26. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies Baud fOSC=1.00MHz fOSC=1.8432MHz fOSC=2.00MHz Rate U2X=0 U2X=1 U2X=0 U2X=1 U2X=0 U2X=1 UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR...
  • Page 152 14. USART A96G174/A96S174 User’s manual Table 26. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies (continued) Baud fOSC=8.00MHz fOSC=11.0592MHz fOSC=14.7456MHz Rate U2X=0 U2X=1 U2X=0 U2X=1 U2X=0 U2X=1 UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD 2400 0.2%...

  • Page 153: 0% Error Baud Rate

    14.14 0% error baud rate USART system of A96G174/A96S174 supports floating point counter logic for 0% error of baud rate. By using 8-bit floating point counter logic, cumulative error to below the decimal point can be removed. Floating point counter value is defined by baud rate error. In the baud rate formula, BAUD is presented in the integer count value.

  • Page 154: 15 Power Down Operation

    A96G174/A96S174 User’s manual 15 Power down operation A96G174/A96S174 has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. A96G174/A96S174 provides three kinds of power saving functions such as Main-IDLE mode, Sub-IDLE mode and STOP mode. During one of these three modes, program will be stopped.

  • Page 155: Idle Mode

    A96G174/A96S174 User’s manual 15. Power down operation 15.2 IDLE mode Power control register is set to ‘01h’ to enter into IDLE mode. In IDLE mode, internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally, but CPU stops.

  • Page 156: Released Operation Of Stop Mode

    15. Power down operation A96G174/A96S174 User’s manual CPU Clock Release External Interrupt STOP Instruction Execute BIT Counter Clear & Start By Software setting Normal Operation STOP Operation Normal Operation Before executed STOP instruction, BIT must be set properly by software to get stabilization.

  • Page 157: Figure 81. Stop Mode Release Flow

    A96G174/A96S174 User’s manual 15. Power down operation SET PCON[7:0] SET IEx.b STOP Mode Interrupt Request Corresponding Interrupt IEx.b==1 ? Enable Bit (IE, IE1, IE2, IE3) STOP Mode Release Interrupt Service Routine Next Instruction Figure 81. STOP Mode Release Flow...

  • Page 158: Register Map

    15. Power down operation A96G174/A96S174 User’s manual 15.5 Register map Table 28. Power-down Operation Register Map Name Address Direction Default Description PCON Power Control Register 15.6 Register description PCON (Power Control Register): 87H PCON7 – – – PCON3 PCON2 PCON1 PCON0 –...

  • Page 159: 16 Reset

    Accumulator Stack Pointer (SP) Peripheral Clock Control Register Refer to the Peripheral Registers A96G174/A96S174 has five types of reset sources as shown in the followings: External RESETB  Power ON RESET (POR)  WDT Overflow Reset (In the case of WDTEN = `1`) ...

  • Page 160: Power On Reset

    16. Reset A96G174/A96S174 User’s manual 16.2 Power on reset When rising device power, POR (Power On Reset) has a function to reset a device. If POR is used, it executes the device RESET function instead of the RESET IC or the RESET circuits.

  • Page 161: Figure 85. Configuration Timing When Power-On

    A96G174/A96S174 User’s manual 16. Reset Counting for configure option read start after POR is released Internal nPOR PAD RESETB “H” LVR_RESETB .. 27 28 BIT (for Configure) 00 01 02 03 BIT (for Reset) 1us X 256 X 28h = about 10ms...

  • Page 162: External Resetb Input

    16. Reset A96G174/A96S174 User’s manual Table 30. Boot Process Description Process Description Remarks ①  No Operation 0.7V to 0.9V  LSIRC (128kHz) ON ② 1st POR level Detection About 1.1V to 1.3V ③  (LSIRC 128kHz/32)x32h Delay section Slew Rate >= 0.025V/ms (=10ms) ...

  • Page 163: Figure 87. Timing Diagram After Reset

    A96G174/A96S174 User’s manual 16. Reset RESETB Release Internal Release RESETB ADDRESS CORE RESET Process Stabilization Time Main Program TST = 16.4ms Step �� ������ = × �������� × �� ���� Figure 87. Timing Diagram after RESET PRESCALER COUNT START OSC START TIMING Figure 88.

  • Page 164: Low Voltage Reset Process

    16.4 Low voltage reset process A96G174/A96S174 has an On-chip brown-out detection circuit (BOD) for monitoring VDD level during operation by comparing it to a fixed trigger level. Trigger level for the BOD can be selected by configuring LVRVS[2:0] bits to be 1.61V, 1.77V, 2.13V, 2.46V, 3.56V.

  • Page 165: Lvi Block Diagram

    A96G174/A96S174 User’s manual 16. Reset “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB ..27 28 BIT (for Config) 00 01 02 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms...

  • Page 166: Register Map

    16. Reset A96G174/A96S174 User’s manual 16.6 Register Map Table 31. Reset Operation Register Map Name Address Direction Default Description RSTFR Reset Flag Register LVRCR Low Voltage Reset Control Register LVICR Low Voltage Indicator Control Register 16.7 Reset Operation Register Description RSTFR (Reset Flag Register): E8H –...
  • Page 167 A96G174/A96S174 User’s manual 16. Reset LVRCR (Low Voltage Reset Control Register): D8H – – – – LVRVS2 LVRVS1 LVRVS0 LVREN – – – – Initial value: 00H LVRVS[2:0] LVR Voltage Select LVRVS2 LVRVS1 LVRVS0 Description 1.61V 1.77V 2.13V 2.46V 3.56V...

  • Page 168: 17 Memory Programming

    17. Memory programming A96G174/A96S174 User’s manual 17 Memory programming A96G174/A96S174 has flash memory to which a program can be written, erased, and overwritten while mounted on the board. Serial ISP mode is supported. Flash of A96G174/A96S174 features the followings: Flash Size : 8Kbytes ...

  • Page 169: Register Description

    A96G174/A96S174 User’s manual 17. Memory programming 17.1.2 Register description FEMR (Flash Mode Register): 1020H FSEL ERASE PBUFF OTPE FEEN Initial value: 00H FSEL Select flash memory. Deselect flash memory Select flash memory Enable program or program verify mode with VFY...
  • Page 170 17. Memory programming A96G174/A96S174 User’s manual FECR (Flash Control Register): 1021H EXIT1 EXIT0 WRITE READ nFERST nPBRST Initial value: 03H Enable flash bulk erase mode Disable bulk erase mode of Flash memory Enable bulk erase mode of Flash memory EXIT[1:0] Exit from program mode.
  • Page 171 A96G174/A96S174 User’s manual 17. Memory programming FESR (Flash Status Register): 1022H PEVBSY REMAPSI REMAP ROMINT WMODE EMODE VMODE Initial value: 80H PEVBSY Operation status flag. It is cleared automatically when operation starts. Operations are program, erase or verification Busy (Operation processing)
  • Page 172 17. Memory programming A96G174/A96S174 User’s manual FEARM (Flash address middle Register): 1029H ARM7 ARM6 ARM5 ARM4 ARM3 ARM2 ARM1 ARM0 Initial value: 00H ARM[7:0] Flash address middle FEARH (Flash address high Register): 1028H ARH7 ARH6 ARH5 ARH4 ARH3 ARH2 ARH1...

  • Page 173: Figure 93. Read Device Internal Checksum (Full Size)

    A96G174/A96S174 User’s manual 17. Memory programming Start OCD mode entry Write(OCD_CODE, 0xF555, 0xAA) Set checksum read mode Write(OCD_CODE, 0xFAAA, 0x55) Write(OCD_CODE, 0xF555, 0xA5) Write(OCD_XDATA, FEMR, 0x81) Set auto verify mode Write(OCD_CODE, FETR, 0x08) Write(OCD_CODE, FECR, 0x07) Busy check (FESR[7]=L) Read 24 - bit Checksum (H, M, L)

  • Page 174: Figure 94. Read Device Internal Checksum (User Define Size)

    17. Memory programming A96G174/A96S174 User’s manual Start OCD mode entry Write(OCD_CODE, 0xF555, 0xAA) Set checksum read mode Write(OCD_CODE, 0xFAAA, 0x55) Write(OCD_CODE, 0xF555, 0xA5) Write(OCD_XDATA, FEARM,Start Address Upper) Set auto verify mode Write(OCD_XDATA, FEARL,Start Address Lower) Write(OCD_XDATA, FEARM1,End Address Upper) Write(OCD_XDATA, FEARL1,End Address Lower)

  • Page 175: Table 33. Program And Erase Time

    A96G174/A96S174 User’s manual 17. Memory programming FETCR (Flash Time control Register): 1023H TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Initial value: 00H TCR[7:0] Flash Time control Program and erase time is controlled by setting FETCR register. Program and erase timer uses 10-bit counter.

  • Page 176: Memory Map

    17. Memory programming A96G174/A96S174 User’s manual 17.2 Memory map 17.2.1 Flash memory map Program memory uses 8K bytes of flash memory. It is read by byte and written by byte or page. One page is 32-bytes FFFFh pgm/ers/vfy Flash 8 Kbytes 0000h Figure 95.

  • Page 177: Serial In-System Program Mode

    A96G174/A96S174 User’s manual 17. Memory programming 17.3 Serial in-system program mode Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 18 Development tools in details about debugger. 17.3.1 Flash operation Configuration (This Configuration is just used for follow description.) FEMR[4] &...

  • Page 178: Figure 98. The Sequence Of Bulk Erase Of Flash Memory

    17. Memory programming A96G174/A96S174 User’s manual Master Reset Page Buffer Reset Page Buffer Load Configuration Reg.<0> Set Erase Erase Latency (500us) Page Buffer Reset Configuration Reg.<0> clear Reg.<6:5> setting Cell Read Pass/Fail? Figure 98. The Sequence of Bulk Erase of Flash Memory Flash read ①...
  • Page 179 A96G174/A96S174 User’s manual 17. Memory programming ④ Enter program/erase mode sequence. NOTE2 Write 0xAA to 0xF555. Write 0x55 to 0xFAAA. C. Write 0xA5 to 0xF555. NOTES: Refer to how to enter ISP mode. Command sequence to activate Flash write/erase mode. It is composed of sequentially writing data of Flash memory.
  • Page 180 17. Memory programming A96G174/A96S174 User’s manual ⑨ Insert one NOP operation ⑩ Read FESR until PEVBSY is 1. ⑪ Repeat ② to ⑧ until all pages are erased Flash bulk erase mode ① Enable program mode. ② Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 ③...
  • Page 181 A96G174/A96S174 User’s manual 17. Memory programming ⑥ Set page address. FEARH:FEARM:FEARL=20’hx_xxxx ⑦ Set FETCR. ⑧ Start program. FECR:0000_1011 ⑨ Insert one NOP operation ⑩ Read FESR until PEVBSY is 1. Flash OTP area erase mode ① Enable program mode. ② Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 ③...

  • Page 182: Mode Entrance Method Of Isp Mode

    17. Memory programming A96G174/A96S174 User’s manual ③ Read data from Flash Flash page buffer read ① Enable program mode. ② Select page buffer. FEMR:1000_1001 ③ Read data from Flash. Summary of flash program/erase mode Table 34. Operation Mode Operation mode...

  • Page 183: Security

    17.5 Security A96G174/A96S174 provides Lock bits which can be left un-programmed (“0”) or can be programmed (“1”) to obtain the additional features listed in Table 36. The Lock bit can only be erased to “0” with the bulk erase command and a value of more than 0x40 at FETCR.

  • Page 184: How To Write The Configure Option In User Program

    17. Memory programming A96G174/A96S174 User’s manual CONFIGURE OPTION 1: ROM Address 0000H (A96G174/A96S174 32K Series) – – – – PAEN PASS2 PASS1 PASS0 Initial value: 00H PAEN Enable Specific Area Write Protection Disable Protection Enable Protection PASS [2:0] Select Specific Area for Write Protection NOTE: When PAEN = ‘1’, it is applied.

  • Page 185: 18 Development Tools

    ABOV semiconductor does not provide any compiler for the A96G174/A96S174. Regarding the compilers, it is recommended to consult with your compiler provider. Since A96G174/A96S174 has the Mentor 8051 as a core, and ROM is smaller than 64Kbytes in size, a developer can use any standard 8051 compiler from other providers.

  • Page 186: Feature Of 94/96/97 Series Core

    18.2.1 Feature of 94/96/97 series core ABOV’s 8-bit microcontroller contains the M8051/CM8051 core that is an improved version of the 8051. The M8051/CM8051 core is compatible with the 8051, and reduces time of operation cycles. It makes development easier by providing the OCD debug function.
  • Page 187 Whole interrupts: 0, 6, 12, and 18 have higher priorities. The A96G174/A96S174 has the 96 series core and OCD 1 interface. The A96G174/A96S174 can be operated with the OCD II dongle too, because the OCD II dongle includes all functions of the OCD1.

  • Page 188: Ocd Type Of 94/96/97 Series Core

    Development tools A96G174/A96S174 User’s manual 18.2.2 OCD type of 94/96/97 series core Cores of the 96-series use the OCD 1 for debug interfaces, while cores of the 94-series and 97-series use the OCD 2 for debug interfaces. The OCD 1 and OCD 2 use the same method on the Hardware, however, the protocols are incompatible with each other.

  • Page 189: Interrupt Priority Of 94/96/97 Series Core

    A96G174/A96S174 User’s manual Development tools 18.2.3 Interrupt priority of 94/96/97 series core In the M8051, users can set interrupt priorities by group. The 96-series microcontroller with the basic M8051 core only supports interrupt priorities in group units. In the 94-series or 97-series microcontroller, users set interrupt priorities to have more functionalities than existing features, and can set individual priority for each interrupt source.

  • Page 190: Extended Stack Pointer Of 94/96/97 Series Core

    Development tools A96G174/A96S174 User’s manual 18.2.4 Extended stack pointer of 94/96/97 series core The M8051 uses IRAM area for Stack Pointer. However, 94-series and 97-series microcontrollers use both IRAM area and XRAM area for the Stack Pointer by configuring additional registers.

  • Page 191: Ocd (On-Chip Debugger) Emulator And Debugger

    A96G174/A96S174 User’s manual Development tools 18.3 OCD (On-chip debugger) emulator and debugger Microcontrollers with 8051 cores have an OCD (On-Chip Debugger), a debug emulation block. The OCD is connected to a target microcontroller using two lines such as DSCL and DSDA. The DSCL is used for clock signal and the DSDA is used for bi-directional data.

  • Page 192: Figure 101. Ocd 1 And Ocd 2 Connector Pin Diagram

    ― Logic power supply pin. The OCD emulator supports ABOV’s 8051 series MCU emulation. The OCD uses two wires that are interfaces between PC and MCU, which is attached to user’s system. The OCD can read or change the value of MCU’s internal memory and I/O peripherals. In addition, the OCD controls MCU’s internal debugging logic.

  • Page 193: On-Chip Debug System

    On-chip debug system A96G174/A96S174 supports On-chip debug (OCD) system. We recommend developing and debugging program with A96G1xx series. The OCD system of the A96G174/A96S174 can be used for programming the non-volatile memories and on-chip debugging. In this section, you can find detailed descriptions for programming via the OCD interface. Table 45 introduces features of the OCD.

  • Page 194: Entering Debug Mode

    Development tools A96G174/A96S174 User’s manual Figure 103 shows a block diagram of the OCD interface and the On-chip Debug system. Figure 103. On-Chip Debugging System in Block Diagram 18.3.2 Entering debug mode While communicating through the OCD, you can enter the microcontroller into DEBUG mode by applying power to it.

  • Page 195: Two-Wire Communication Protocol

    A96G174/A96S174 User’s manual Development tools 18.3.3 Two-wire communication protocol For the OCD interface, the semi-duplex communication protocol is used through separate two wires, the DSCL and DSDA. The DSCL is used for serial clock signal and the DSDA is used for bi-directional serial address and data.

  • Page 196: Figure 105. 10-Bit Transmission Packet

    Development tools A96G174/A96S174 User’s manual Figure 105. 10-bit Transmission Packet Packet transmission timing Figure 106 shows a timing diagram of a packet transmission using the OCD communication protocol. A start bit in the figure means start of a packet and is valid when the DSDA falls from ‘H’ to ‘L’ while External Host maintains the DSCL to ‘H’.

  • Page 197: Figure 107. Bit Transfer On Serial Bus

    A96G174/A96S174 User’s manual Development tools Figure 107 shows a timing diagram of each bit based on state of the DSCL clock and the DSDA data. Similar to I2C signal, the DSDA data is allowed to change when the DSCL is ‘L’. If the data changes when the DSCL is ‘H’, the change means ‘START’...

  • Page 198: Figure 109. Acknowledge On Serial Bus

    Development tools A96G174/A96S174 User’s manual As shown in Figure 109, when transferring data, a receiver outputs the DSDA to ‘L’ to inform the normal reception of data. If a receiver outputs DSDA to ‘H’, it means error reception of data.

  • Page 199: Programmers

    Development tools 18.4 Programmers 18.4.1 E-PGM+ E-PGM+ USB is a single programmer. You can program A96G174/A96S174 directly using the E-PGM+. 8 10 Figure 111. E-PGM+ (Single Writer) and Pinouts 18.4.2 OCD emulator OCD emulator allows users to write code on the device too, since OCD debugger supports In System...

  • Page 200: Gang Programmer

    18.5 Flash programming Program memory for A96G174/A96S174 is a Flash type. This Flash ROM is accessed through four pins such as DSCL, DSDA, VDD, and VSS in serial data format. For detailed information about the Flash memory programming, please refer to 17. Memory programming.

  • Page 201: Connection Of Transmission

    A96G174/A96S174 User’s manual Development tools 18.6 Connection of transmission OCD’s two-wire communication interfaces use the Open-Drain Method (Wire-AND Bi-Directional I/O). Normally, it is recommended to place a resister greater than 4.7kΩ for the DSCL and DSDA respectively. The capacitive load is recommended to be less than 100pF. Outside these ranges, because the communication may not be accomplished, the connection to Debug mode is not guaranteed.

  • Page 202: Circuit Design Guide

    Development tools A96G174/A96S174 User’s manual 18.7 Circuit design guide To program Flash memory, programming tools require 4 signal lines, DSCL, DSDA, VDD, and VSS. When designing a PCB circuit, you should consider these 4 signal lines for on-board programming. In addition, you need to be careful when designing the related circuit of these signal pins, because rising/falling timing of the DSCL and DSDA is very important for proper programming.

  • Page 203: Figure 114. Pcb Design Guide For On-Board Programming

    A96G174/A96S174 User’s manual Development tools 2 4 6 8 10 E-PGM+ , E-GANG4 , E-GANG6 VDD VSS DSCL DSDA Four-wire Interface 1 3 5 7 9 R1 (2k ~ 5k ) P01/DSCL(I) To application circuit R2 (2k ~ 5k )

  • Page 204: Appendix

    Appendix A96G174/A96S174 User’s manual Appendix Instruction table Instructions are either1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.

  • Page 205: Table 47. Instruction Table (Continued)

    A96G174/A96S174 User’s manual Appendix Table 47. Instruction Table (continued) Logical Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data...

  • Page 206: Table 47. Instruction Table (Continued)

    Appendix A96G174/A96S174 User’s manual Table 47. Instruction Table (continued) Data transfer Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7 MOV A,#data...

  • Page 207: Table 47. Instruction Table (Continued)

    A96G174/A96S174 User’s manual Appendix Table 47. Instruction Table (continued) Boolean Mnemonic Description Bytes Cycles Hex code CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit...

  • Page 208: Table 47. Instruction Table (Continued)

    Appendix A96G174/A96S174 User’s manual Table 47. Instruction Table (continued) Miscellaneous Mnemonic Description Bytes Cycles Hex code No operation Additional instructions (selected through EO[7:4]) Mnemonic Description Bytes Cycles Hex code MOVC M8051W/M8051EW-specific instruction @(DPTR++),A supporting software download into program memory TRAP...

  • Page 209: Revision History

    A96G174/A96S174 User’s manual Revision history Revision history Date Revision Description 2019.12.10 1.00 First creation 2020.02.04 1.01 Added the disclaimer and modified the distributor. 2020.04.02 1.02 Revise “Ordering information” 2020.04.06 1.03 Revise “Device Numbering Nomenclature” 2020.05.22 1.04 Revise “Low voltage reset and low voltage indicator characteristics”...
  • Page 210 Revision history A96G174/A96S174 User’s manual Updated High Speed Internal RC Oscillator Tolerance at Table 44. High Internal RC Oscillator Characteristics. Corrected the frequency unit from KHz to kHz. 2022.04.01 1.10 Updated the Table 41. BGR Characteristics at Electrical characteristics. 2022.04.12 1.11...
  • Page 211 ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders.

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