Texas Instruments LMKDB1 02 Series User Manual
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Texas Instruments LMKDB1 02 Series User Manual

Texas Instruments LMKDB1 02 Series User Manual

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www.ti.com
EVM User's Guide: LMKDB1102EVM, LMKDB1202EVM
LMKDB1x02 Evaluation Module
Description
The LMKDB1102 and LMKDB1202 evaluation module
(EVM) is designed to provide a quick setup to
evaluate the LMKDB1x02 LP-HCSL buffer that
supports PCIe Gen 1 to Gen 6. The printed circuit
board (PCB) contains several jumpers to enable
the LMKDB1x02 with desired user programming
and setup. The evaluation module provides flexibility
for compliance testing, system prototyping, and
performance evaluation of the LMKDB1x02 device.
LMKDB1102EVM
SNAU310 – JUNE 2024
Submit Document Feedback
Features
•
PCIe Gen 1 to Gen 6
•
Setup via jumper headers and pins
Applications
•
High performance computing
•
Server motherboard
•
NIC/SmartNIC
•
Hardware accelerator
Copyright © 2024 Texas Instruments Incorporated
LMKDB1202EVM
LMKDB1x02 Evaluation Module
Description
1

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Summary of Contents for Texas Instruments LMKDB1 02 Series

  • Page 1 The evaluation module provides flexibility • NIC/SmartNIC for compliance testing, system prototyping, and • Hardware accelerator performance evaluation of the LMKDB1x02 device. LMKDB1102EVM LMKDB1202EVM SNAU310 – JUNE 2024 LMKDB1x02 Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...

  • Page 2: Kit Contents

    The LMKDB1x02 is a high performance LP-HCSL buffer that supports PCIe Gen 1 to Gen 6. LMKDB1x02 has extremely low additive jitter, fail safe inputs, flexible power-up sequence, individual output enable pins, and loss of input signal (LOS) detection. LMKDB1x02 Evaluation Module SNAU310 – JUNE 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...

  • Page 3: Evm Measurements

    2.2 EVM Measurements Measurements can now be made on the clock outputs using an oscilloscope or a phase noise analyzer. SNAU310 – JUNE 2024 LMKDB1x02 Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...

  • Page 4: Output Status

    Table 3-5. LP-HCSL Differential CLock Output Impedance Select ZOUT_SEL Input Level Function Low (default) LMKDB1x02 has 85Ω output termination High LMKDB1x02 has 100Ω output termination LMKDB1x02 Evaluation Module SNAU310 – JUNE 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 5 CLKIN1 pins of the LMKDB1202 To enable internal 50Ω to ground terminations. Set the Input Termination on Input page to Internal termination Enabled. SNAU310 – JUNE 2024 LMKDB1x02 Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 6 LED status light for VDD supply selected from USB option or VDD_EXT External option through JP17. TP8, TP9 Test points for GND reference on the board. LMKDB1x02 Evaluation Module SNAU310 – JUNE 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 7 2. Output phase noise is measured through a Balun to the differential waveform from the LMKDB1x02 into a single-ended waveform for the phase noise analyzer. Figure 4-1. LMKDB1x02 Output Clock Phase Noise SNAU310 – JUNE 2024 LMKDB1x02 Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 8 Hardware Design Files www.ti.com 5 Hardware Design Files 5.1 Schematics Figure 5-1. Power Supply Figure 5-2. LMKDB1102 Device and CLKIN0_P/N Reference LMKDB1x02 Evaluation Module SNAU310 – JUNE 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 9 Hardware Design Files Figure 5-3. LMKDB1202 Device and CLKIN#_P/N Reference Figure 5-4. Clock Outputs CLK1 and CLK2 SNAU310 – JUNE 2024 LMKDB1x02 Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 10 Hardware Design Files www.ti.com Figure 5-5. Output Enable Pins (OE#) and LMKDB1102 Logic I/O Jumpers LMKDB1x02 Evaluation Module SNAU310 – JUNE 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 11 Hardware Design Files Figure 5-6. Output Enable Pins (OE#) and LMKDB1202 Logic I/O Jumpers Figure 5-7. Status LEDs and Test Points SNAU310 – JUNE 2024 LMKDB1x02 Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...

  • Page 12: Pcb Layouts

    Hardware Design Files www.ti.com 5.2 PCB Layouts Figure 5-8. Layer Stackup Figure 5-9. Top Layer (CLKIN / CLKOUT Signals) LMKDB1x02 Evaluation Module SNAU310 – JUNE 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 13 Hardware Design Files Figure 5-10. Bottom Layer Figure 5-11. GND Layer 1 SNAU310 – JUNE 2024 LMKDB1x02 Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 14 Hardware Design Files www.ti.com Figure 5-12. GND 2 Layer LMKDB1x02 Evaluation Module SNAU310 – JUNE 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 15 Grade 0, 0402 4.99k RES, 4.99 k, 1%, 0.063 W, 0402 0402 RC0402FR-074K99L Yageo America RES Thick Film, 0Ω, 0.2W, 0402 0402 CRCW04020000Z0EDHP Vishay Dale SNAU310 – JUNE 2024 LMKDB1x02 Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 16 Miniature, SMT TP7, TP8, TP9 PCIe Gen 1 to Gen 6 Ultra Low WQFN20 LMKDB1102REYT Texas Instruments Jitter, 2:2 LP-HCSL Clock Buffer and Clock MUX LMKDB1x02 Evaluation Module SNAU310 – JUNE 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 17 RES, 0, 5%, 0.063 W, AEC-Q200 0402 CRCW04020000Z0ED Vishay-Dale R18, R19, R21, Grade 0, 0402 R23, R25 4.99k RES, 4.99 k, 1%, 0.063 W, 0402 0402 RC0402FR-074K99L Yageo America SNAU310 – JUNE 2024 LMKDB1x02 Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 18 Miniature, SMT TP7, TP8, TP9 PCIe Gen 1 to Gen 6 Ultra Low WQFN20 LMKDB1202REYT Texas Instruments Jitter, 2:2 LP-HCSL Clock Buffer and Clock MUX LMKDB1x02 Evaluation Module SNAU310 – JUNE 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...

  • Page 19: Additional Information

    For additional information on LMKDB1x02, refer to LMKDB1120/1108/1104/1102/1204/1202 PCIe Gen 1 to Gen 6 Ultra Low Jitter 1:20, 1:8, 1:4, 1:2, 2:4, 2:2 LP-HCSL Clock Buffer and Clock MUX. SNAU310 – JUNE 2024 LMKDB1x02 Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 20 STANDARD TERMS FOR EVALUATION MODULES Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein.
  • Page 21 www.ti.com Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product.
  • Page 22 www.ti.com Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à...
  • Page 23 www.ti.com EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices.
  • Page 24 Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...

  • Page 25: Important Notice

    TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated...

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