Texas Instruments LMK04826 User Manual
Texas Instruments LMK04826 User Manual

Texas Instruments LMK04826 User Manual

Clock conditioner
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LMK04826/28 User's Guide
1
Introduction
These evaluation board instructions describes how to set up and operate the LMK04828/6 evaluation
module (EVM). The LMK04828/6 is the industry's highest performance clock conditioner with JEDEC
JESD204B support.
2
Evaluation Board Kit Contents
The evaluation board kit includes. -002 and -003 are currently available:
SV600788
Evaluation Board
USB Communications
LPT Communicaitions
SNAU145A – MAY 2013 – Revised JUNE 2013
Submit Documentation Feedback
Table 1. EVM Contents
-001
(1) LMK04828B Evaluation Board
(1) USB2UWIRE-IFACE
(1) CodeLoader uWire cable
Copyright © 2013, Texas Instruments Incorporated
User's Guide
SNAU145A – MAY 2013 – Revised JUNE 2013
-002
(1) LMK04826B Evaluation
(1) USB2ANY
-
LMK04826/28 User's Guide
-003
Board
1

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Summary of Contents for Texas Instruments LMK04826

  • Page 1 (1) LMK04826B Evaluation Evaluation Board (1) LMK04828B Evaluation Board Board USB Communications (1) USB2UWIRE-IFACE (1) USB2ANY LPT Communicaitions (1) CodeLoader uWire cable SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 2: Quick Start

    These SMAs not used by default. With PCB change, can be used for reference Reference input for single PLL mode. Figure 1. Quick Start Diagram LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 3: Quick Start Description

    For older pre-release boards, Pin Configuration must manually be changed and only work with USB2UWIRE-IFACE or LPT cable. Figure 2. Pin Configuration for Pre-Release Boards SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 4 On PLL tabs clicking Show Bits will show register info. • On other tabs, pressing ~ with a control focused will show help. LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 5 3. Set SYSREF_PD and SYSREF_DDLY_PD = 0 4. Set SYNC_DISX and SYNC_DISSYSREF = 0 (where X is the desired DCLKout) SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 6 9. Generate a SYNC event (i.e. toggle SYNC_POL on/off/on) 10. Ensure SYSREF_CLR = 0 (SYSREF tab, location: right side, below clock output pic) Figure 5. Pulsed SYSREF Output LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 7 Quick Start www.ti.com Figure 6. Clock Outputs Tab Setup for SYSREF Output on SDCLKout7 SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 8: Pll Loop Filters And Loop Parameters

    PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth. LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 9 Dual PLL, Internal VCO 122.88 MHz 122.88 MHz 122.88 MHz Figure 7. Selecting a Default Mode for the LMK04828 Device SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 10: Select Device

    Setup. This contains information on troubleshooting communications. Restoring a Default Mode Click “Mode” → “CLKin1 122.88 MHz, OSCin 122.88 MHz”; then press Ctrl+L. LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 11: Visual Confirmation Of Frequency Lock

    CLKin1. This assumes PLL1_LD_MUX = PLL1_DLD, PLL2_LD_MUX = PLL2_DLD and PLLX_LD_TYPE = Output (Push-Pull). SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 12: Enable Clock Outputs

    Unless otherwise noted, the connectors described can be assumed to be populated by default. Additionally, some applicable CodeLoader programming controls are noted for convenience. LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 13 On-board LDO regulators and 0 Ω resistor options provide flexibility to supply and route power to various devices. See the schematics in section Section 11 for more details. SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 14 The programmable logic I/O signals accessible through this header include: RESET, SYNC, Status_LD1, Status_LD2, CLKin_SEL0, and CLKin_SEL1. These logic I/O signals also have dedicated SMAs and test points. LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 15 A SYNC event can also be programmed by toggling the SYNC_POL_INV bit in the Bits/Pins tab in CodeLoader. Test point: CMOS, Programmable status I/O pin. RESET_TP Input/Output SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 16: Recommended Test Equipment

    50-ohm cables to minimize external sources of skew or other errors/distortion that may be introduced if using oscilloscope probes. LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 17: Port Setup Tab

    The Pin Configuration field is hardware dependent and normally does not need to be changed by the user (except for pre-release boards). For information on this configuration, refer to Figure SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 18 (50,150, 250, 1550 uA). Charge Pump State PLL1_CP_TRI PLL1 Charge Pump State. Click to toggle between Active and Tri- State. LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 19 Changes made on this tab will be reflected in the Clock Outputs tab. The VCO Frequency should conform to the specified internal VCO frequency range. SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 20 Left click to increase the component value, and right click to decrease the value. These values can also be changed in the Bits/Pins tab. LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 21 Figure 15. SYSREF Tab The SYSREF tab show the controls for SYSREF functionality as well as Dynamic Digital Delay enable. SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 22: Bits/Pins Tab

    Table 8 lists the test conditions used for output clock phase noise measurements with the Crystek 122.88 MHz VCXO. LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 23 10 kHz -153.3 34.5 100 kHz -162 32.9 1 MHz -165.7 22.7 10 MHz -168.1 515.4 40 MHz -168.1 60.5 SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 24 SDCLKout pairs. Below is a phase noise measurement of DCLKout2 (best phase noise clock output) using both a balun and single ended. Figure 18. LMK04826 DCLKout2, VCO0, 245.76 MHz, Div8, LVPECL20 /w 240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = Prodyn BIB-100G LMK04826/28 User’s Guide...
  • Page 25 Appendix B: Typical Phase Noise Performance Plots www.ti.com Figure 19. LMK04826 DCLKout2, VCO0, 245.76 MHz, Div8, LVPECL20 /w 240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback...
  • Page 26 Appendix B: Typical Phase Noise Performance Plots www.ti.com Figure 20. LMK04826 DCLKout2, VCO1, 245.76 MHz, Div10, LVPECL20 /w 240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = Prodyn BIB-100G LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright ©...
  • Page 27 Appendix B: Typical Phase Noise Performance Plots www.ti.com Figure 21. LMK04826 DCLKout2, VCO1, 245.76 MHz, Div10 , LVPECL20 /w 240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback...
  • Page 28 Figure 22. LMK04828 DCLKout2, VCO0, 245.76 MHz, Div10, LVPECL20 /w 240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = ADT2-1T LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 29 Figure 23. LMK04828 DCLKout2, VCO0, 245.76 MHz, Div10, LVPECL20 /w 240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 30 Figure 24. LMK04828 DCLKout2, VCO1, 245.76 MHz, Div12, LVPECL20 /w 240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = ADT2-1T LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 31 Figure 25. LMK04828 DCLKout2, VCO1, 245.76 MHz, Div12, LVPECL20 /w 240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 32 LP5900SD-3.3/NOPB LP5900 Component values C359 = 0.47 uF C360 = 0.47 uF R369 = 51 k Figure 26. Power Supply LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 33 Vcc_VCXO_OpAmp 0.1µF VTUNE1_TP VCXO Loop Filter C1_A1 C2_A1 C2pA1 0.1µF 0.68uF 2.7µF LMP7731MF R2_A1 PLL1 Loop Filter Figure 27. LMK04828B SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 34 0.375" Standoff PCB Rev: LOGO 0.375" Standoff 0.375" Standoff Texas Instruments LOGO 0.375" Standoff 0.375" Standoff ESD Susceptible Figure 28. Digital LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 35 142-0701-806 142-0701-806 SDCLKout13 SDCLKout13* SDCLKout13_1_N SDCLKout13_N 0.1µF 142-0701-806 SDCLKout13 SDCLKout13_1_P SDCLKout13_P 0.1µF 142-0701-806 Figure 29. Clock Outputs 1 of 2 SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 36 142-0701-806 DCLKout12 DCLKout12 DCLKout12_1_P DCLKout12_P 0.1µF 142-0701-806 DCLKout12* DCLKout12_1_N DCLKout12_N 0.1µF R237 142-0701-806 Figure 30. Clock Outputs 2 of 2 LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 37: Appendix D: Bill Of Materials

    Kemet C0603C209C5GAC 50V, +/-12.5%, C0G/NP0, 0603 C35, C310, C317, CAP, CERM, 10uF, Kemet C0805C106K8PAC C324, C352 10V, +/-10%, X5R, 0805 SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 38 R18, R305, R307, FB, 120 ohm, 500 Murata BLM18AG121SN1D 12 R342, R343, R344, mA, 0603 R345, R347, R354, R358, R371, R374 LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 39 150mA Linear 3.3/NOPB Regulator for RF/Analog Circuits Requires No Bypass Capacitor, 6-pin LLP, Pb-Free Connector, TH, Emerson Network 142-0701-201 Power SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 40: Lpt Driver Loading

    CodeLoader in the Port Setup tab as shown in Figure Figure 32. Selecting the LPT Port Address LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 41: Correct Lpt Mode

    Launch Microsoft XP Mode by clicking on Start > All Programs > Windows Virtual PC > Windows XP Mode, as shown below. SNAU145A – MAY 2013 – Revised JUNE 2013 LMK04826/28 User’s Guide Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 42 Once Windows XP is running, install the CodeLoader software by running the executable file. 14.4 Attach the USB device to your computer Figure 35. Attach USB LMK04826/28 User’s Guide SNAU145A – MAY 2013 – Revised JUNE 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 43: Regulatory Compliance Information

    Any exceptions to this are strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory authorities, which is responsibility of user including its acceptable authorization.
  • Page 44 FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
  • Page 45 Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan http://www.tij.co.jp...
  • Page 46 FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate Assurance and Indemnity Agreement. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated...
  • Page 47: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.
  • Page 48: Texas Instruments

    Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments LMK04826BEVM...

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