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GD32G5 Series
GigaDevice Semiconductor GD32G5 Series Manuals
Manuals and User Guides for GigaDevice Semiconductor GD32G5 Series. We have
1
GigaDevice Semiconductor GD32G5 Series manual available for free PDF download: Hardware Development Manual
GigaDevice Semiconductor GD32G5 Series Hardware Development Manual (39 pages)
Brand:
GigaDevice Semiconductor
| Category:
Microcontrollers
| Size: 1 MB
Table of Contents
Table of Contents
2
List of Figures
4
List of Tables
5
Introduction
6
Table 1-1. Applicable Products
6
Hardware Design
7
Power Supply
7
Backup Domain
7
Figure 2-1. Gd32G5Xx Series Power Supply Overview
7
VDD / VDDA Domain
9
Vref
9
Figure 2-2. VREF Connection
9
Table 2-1. VDD
9
Power Supply Design
10
Figure 2-3. Gd32G5Xx Recommended Power Supply Design
10
Reset and Power Management
11
Figure 2-4. Waveform of the POR/PDR
11
Figure 2-5. Waveform of the BOR
12
Figure 2-6. Waveform of the LVD Threshold
13
Figure 2-7. the RCU_RSTSCK Register
13
Figure 2-8. System Reset Circuit
13
Clock
14
Figure 2-8. Recommend External Reset Circuit
14
External High-Speed Crystal Oscillator Clock (HXTAL)
15
Figure 2-9. Gd32G5Xx Clock Tree
15
Figure 2-10. HXTAL External Crystal Circuit
16
Figure 2-11. HXTAL External Clock Circuit
16
External Low-Speed Crystal Oscillator Clock (LXTAL)
17
Figure 2-12. LXTAL External Crystal Circuit
17
Figure 2-13. LXTAL External Clock Circuit
17
Clock Output Capability (CKOUT)
18
Table 2-2. Clock Output Source Select
18
HXTAL Clock Monitor(Ckm
19
LXTAL Clock Monitor(Lckm
19
Startup Configuration
19
Table 2-3. Low-Speed Clock Output Source Select
19
Table 2-4. Boot Modes
19
Figure 2-14. Recommend BOOT Circuit Design
20
Typical Peripheral Modules
21
GPIO Circuit
21
Figure 2-15. Basic Structure of Standard IO
21
ADC Circuit
22
Figure 2-16. ADC Acquisition Circuit Design
22
Internal Temperature Sensor Calibration
23
DAC Circuit
24
CMP Circuit
25
Figure 2-17. CMP Block Diagram
25
Table 2-6. DAC Triggers and Outputs Summary
25
Table 2-7. CMP Inputs and Outputs Summary
26
Figure 2-18. CMP Hysteresis
27
Figure 2-19. the CMP Outputs Signal Blanking
27
Hrtimer
28
Table 2-8. Resolution with F
28
Power Saving Modes
30
Table 2-9. Power Domain Summary
30
Download the Debug Circuit
31
Figure 2-21. Recommend Standby External Wake-Up Pin Circuit Design
31
Figure 2-22. Recommend JTAG Wiring Reference Design
32
Figure 2-23. Recommend SWD Wiring Reference Design
32
Table 2-11. SWD Download Debug Interface Assignment
32
Reference Schematic Design
33
Figure 2-24. Gd32H7Xx Recommend Reference Schematic Design
33
PCB Layout Design
34
Power Supply Decoupling Capacitors
34
Clock Circuit
34
Figure 3-1. Recommend Power Pin Decoupling Layout Design
34
Reset Circuit
35
Figure 3-2. Recommend Clock Pin Layout Design (Passive Crystal)
35
Figure 3-3. Recommend NRST Trace Layout Design
35
Fan-Out for WLCSP Package
36
Figure 3-4. Fan-Out for WLCSP Package
36
Package Description
37
Table 4-1. Package Description
37
Table 5-1. Revision History
38
Important Notice
39
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