Datascope System 98 Service Manual page 150

2.3.3 Video Receiver Board (0670-00-0641)
The Video Reciever Board is functionally divided into two major circuit groups
as follows:
- LVDS Receiver / De-multiplexer
- Frame Buffer
The detailed theory of operation of these two circuit funtional groups will be
described below. The LVDS Receriver / De-mux is comprised of one IC while the
Frame Buffer is comprised of several devices.
LVDS Signal Receiver
The LVDS (low voltage differential signalling) receiver function is implemented
via a National Semiconductor DS90CR212 device, or equivalent. It works in
conjunction with the DS90CR211 on the Display Controller which takes as
inputs up to 21 parallel signal inputs and a high speed clock, time-division
multiplexes the inputs at seven times the clock rate and then sends them out in
serial fashion on three differential signal lines and one differential clock line.
Thus, the receiver must implement the exact opposite function. First it receives
the differential signal and clock lines, de-serializes them into shift registers and
makes them available at the device ouptuts.
The required signals to be transmitted from the Display Controller are as follows:
Four Upper Panel video bits UDO..UD3
Four Lower Panel video bits LDO..LD3
One Video Clock CP
One Latch Pulse LP
One First Line Marker FLM
One Display Enable ~ DISPLAY ACTIVE
In addition, the LVDS clock is transmitted with the above named signals to
synchronize their de-multiplexing. The LVDS clock is a free-running 30MHz
clock. This is the timing source for all Frame Buffer functions.
The Video Clock (CP) is the signal that indicates a new 8 bit video sample is
available at the output of the LVDS receiver on the falling edge of CP. This
signal is sent/received as one of the LVDS signals. It has a rate of 3.75MHz, or
one eighth of the 30MHz LVDS clock. There is a burst of 160 such pulses per
horizontal scan line. Each falling edge latches in eight data pulses, four each for
the upper and lower planes of the EL display. Therefore:
160 X 4 bits per clock = 640 bits (pixels) per scan line.
The Latch Pulse, analagous to Horizontal Sync, is a pulse that becomes active at
the end of each horizontal scan line, after the CP pulse burst has been terminated
for that line. It's function is to latch the data bits into a display panel. It is used
2-38 System 98 Service Manual
Chapter 2, Theory of Operation