Datascope System 98 Service Manual page 142

A 4 bit Bus-Time out counter is implemented within the MAIN PLD that
counts at one eighth of the CPU clock during each bus cycle. If that counter ever
reaches terminal count, which would take 7.5 micro-seconds, without either of
the DSACK signal becoming active a Bus-Time Out condition is declared. The
signal BERR* (Bus Error) is activated which terminates the bus cycle and causes
the DSS processor to reset. In addition to a Bus Time-Out, any access to an invalid
address or attempting to enter Service Diagnostic mode when not enabled will
cause a Bus Error condition.
The Interrupt Control function encodes the Interrupt Request signals onto the
Interrupt Priority Level signals which are presented to the CPU. The CPU, under
program control, may defer responding to this request. This PLD also supplies
the Interrupt Acknowledge (IACK) signals to the MFP and QUART when the
CPU does respond to their respective interrupt requests in order that the MFP or
QUART place their interrupt vector (an 8 bit number) on the most significant
bits of the data bus. This function is incorporated into the Interrupt Control
PLD.
The Write Enable PLD provides several versions of read and write strobes, each
qualified by slightly different timing, to the memory and peripheral devices of
the 68020 subsystem.
9 Real-Time Clock / NVRAM
This device supplies a battery powered time-of-day function that occupies the
first sixteen memory locations of the device. It can supply alarm and watch-dog
interrupts. The resolution of the clock is 10 milli-seconds.
It also provides 32K bytes (minus 16 bytes for the time-of-day clock registers) of
battery backed static RAM. This is used for fault journal and sleep mode data
storage. The battery which supplies power to this device is internal to the device
is a Lithium cell which will provide 10 years of data integrity.
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2-30 System 98 Service Manual
Chapter 2, Theory of Operation