Chipset Overview - American Megatrends StorTrends 3100 User Manual

American megatrends stortrends 3100: user guide
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Chipset Overview

Built upon the functionality and the capability of the E7520 chipset, The StorTrends 3100
motherboard provides the performance and feature set required for dual processor-based
servers, with configuration options optimized for communications, presentation, storage,
computation or database applications. The Intel E7520 chipset consists of the following
components: the Memory Controller Hub (MCH), the 82801ER I/O Controller Hub 5-R
(ICH5-R), and the Intel PCI-X Hub.
The E7520 MCH supports single or dual processors with Front Side Bus speeds of up to
800 MHz. Its memory controller provides direct connection to two channels of registered
DDR2- 400 with a matched system bus address and data bandwidths of up to 6.4GB/s.
The E7520 also supports the new PCI Express high speed serial I/O interface for superior
I/O bandwidth. The MCH provides three configurable x8 PCI Express interfaces which
may alternatively be configured as two independent x4 PCI Express interfaces. These
interfaces support connection of the MCH to a variety of other bridges that are compliant
with the PCI Express Interface Specification, Rev. 1.0a. The MCH interfaces with the
82801ER I/O Controller Hub 5-R (ICH5R) via a dedicated Hub Interface supporting a
peak bandwidth of 266 MB/s using a x4 base clock of 66 MHz. The PXH provide
connection between a PCI Express interface and two independent PCI bus interfaces that
can be configured for standard PCI 2.3 protocol, as well as the enhanced high-frequency
PCI-X protocol. The PXH can be configured to support for 32- or 64-bit PCI devices
running at 33 MHz, 66 MHz, 100 MHz, and 133 MHz.
The ICH5R I/O Controller Hub provides legacy support similar to that of previous ICH-
family devices, but with extensions in RAID 0,1 support, Serial ATA Technology, and an
integrated ASF Controller. In addition, the ICH5R also provides various integrated
functions, including a two-channel Ultra ATA/100 bus master IDE controller, USB 2.0
host controllers, an integrated 10/100 LAN controller, an LPC firmware hub (FWH) and
Super IO interface, a System Management Interface, a power management interface,
integrated IOxAPIC and 8259 interrupt controllers.
Chapter One : Introduction
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