Cypress Semiconductor CY7C185 Specification Sheet

Features
• High speed
— 15 ns
• Fast t
DOE
• Low active power
— 715 mW
• Low standby power
— 220 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE
• TTL-compatible inputs and outputs
• Automatic power-down when deselected

Functional Description

The CY7C185 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CE
1
CE
2
WE
OE
[1]
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Note:
1. For military specifications, see the CY7C185A datasheet.
Cypress Semiconductor Corporation
, CE , and OE features
1 2
INPUT BUFFER
256 x 32 x 8
ARRAY
POWER
DOWN
COLUMN DECODER
7C185–15
15
130
40/15
• 3901 North First Street
8K x 8 Static RAM
provided by an active LOW chip enable (CE
chip enable (CE ), and active LOW output enable (OE) and
2
three-state drivers. This device has an automatic power-down
feature (CE or CE ), reducing the power consumption by 70%
1 2
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE
puts are both LOW and CE
2
input/output pins (I/O through I/O
0
location addressed by the address present on the address
pins (A through A ). Reading the device is accomplished by
0 12
selecting the device and enabling the outputs, CE
active LOW, CE active HIGH, while WE remains inactive or
2
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
C185–1
7C185–20 7C185–25
20
110
20/15
• San Jose •
fax id: 1013
CY7C185
), an active HIGH
1
and WE in-
1
is HIGH, data on the eight data
) is written into the memory
7
and OE
1

Pin Configurations

DIP/SOJ/SOIC
Top View
NC V
1 28 CC
A WE
2 27
4
A CE
3 26
5 2
A A
4 25
6 3
A A
5 24
7 2
A A
8 6 23 1
A OE
9 7 22
A A
10 8 21 0
A CE
11 9 20 1
A I/O
12 10 19 7
I/O I/O
0 11 18 6
I/O I/O
1 5
12 17
I/O I/O
2 4
13 16
GND I/O
3
14 15
C185–2
7C185–35
25 35
100 100
20/15 20/15
CA 95134 • 408-943-2600
August 12, 1998