Cypress Semiconductor CY7C150 Specification Sheet

50
Features
• Memory reset function
• 1024 x 4 static RAM for control store in high-speed com-
puters
• CMOS for optimum speed/power
• High speed
— 10 ns (commercial)
— 12 ns (military)
• Low power
— 495 mW (commercial)
— 550 mW (military)
• Separate inputs and outputs
• 5-volt power supply 10% tolerance in both commercial
and military
• Capable of withstanding greater than 2001V static dis-
charge
• TTL-compatible inputs and outputs
Functional Description
The CY7C150 is a high-performance CMOS static RAM de-
signed for use in cache memory, high-speed graphics, and
data-acquisition applications. The CY7C150 has a memory re-
set feature that allows the entire memory to be reset in two
memory cycles.
Logic Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Cypress Semiconductor Corporation
Document #: 38-05024 Rev. **
D D D D
0 1 2 3
DATAINPUT
CONTROL
64 x 64
ARRA Y
COLUMN
COLUMN DECODER
DECODER
A A A A
6 7 8 9
Commercial
Military
Commercial
Military
• 3901 North First Street
Separate I/O paths eliminates the need to multiplex data in
and data out, providing for simpler board layout and faster sys-
tem performance. Outputs are three-stated during write, reset,
deselect, or when output enable (OE) is held HIGH, allowing
for easy memory expansion.
Reset is initiated by selecting the device (CS = LOW) and tak-
ing the reset (RS) input LOW. Within two memory cycles all
bits are internally cleared to zero. Since chip select must be
LOW for the device to be reset, a global reset signal can be
employed, with only selected devices being cleared at any giv-
en time.
Writing to the device is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
four data inputs (D
0
specified on the address pins (A
Reading the device is accomplished by taking chip select (CS)
and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the four
output pins (O through O
0
The output pins remain in high-impedance state when chip
enable (CE) or output enable (OE) is HIGH, or write enable
(WE) or reset (RS) is LOW.
A die coat is used to insure alpha immunity.
Pin Configuration
RS
CS
OE
A 3
WE
A 4
A 5
A 6
O
0
A 7
A 8
O
1
A 9
D 0
O
2
D 1
O 0
O
3
O 1
GND
C150–1
7C150 10 7C150 12
10 12
12
90 90
100
• San Jose
CY7C150
1Kx4 Static RAM
D ) is written into the memory location
3
through A ).
0 9
).
3
DIP/SOIC
Top View
1 V CC
24
2
A 2
23
3
22
A 1
4
A 0
21
5
20 RS
7C150 19 CS
6
18
7
WE
8
17 OE
9
16
D 3
10
15
D 2
11 14 O 3
O 2
13
12
C150-2
7C150 15 7C150 25 7C150 35
15 25
15 25
90 90
100 100
• CA 95134 • 408-943-2600
Revised August 24, 2001
35
90
100