Cypress CY62137EV30 Specification Sheet

Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62137CV30
• Ultra-low standby power
— Typical standby current: 1
— Maximum standby current: 7
•
Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Byte power-down feature
• Offered in Pb-free 48-ball VFBGA and 44-pin TSOPII
package
Logic Block Diagram
A
10
A
A
A
A
A
A
A
A
A
A
-
Pow er Down
Circuit
Note:
1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05443 Rev. *B
µ
A
µ
A
DATA IN DRIVERS
9
8
7
6
128K x 16
5
RAM Array
4
3
2
1
0
COLUMN DECODER
CE
BHE
BLE
• 198 Champion Court
2-Mbit (128K x 16) Static RAM
Functional Description
The CY62137EV30 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 90% when addresses are not toggling.
The device can also be put into standby mode reducing power
consumption by more than 99% when deselected (CE HIGH
or both BLE and BHE are HIGH). The input/output pins (I/O
through I/O ) are placed in a high-impedance state when:
15
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by asserting Chip En-
able (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
I/O ), is written into the location specified on the address pins
7
(A through A ). If Byte High Enable (BHE) is LOW, then data
0 16
from I/O pins (I/O through I/O
8
specified on the address pins (A
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O to I/O
0
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62137EV30 is available in 48-ball VFBGA and 44-pin
TSOPII packages.
I/O – I/O
0
I/O – I/O
8
,
• San Jose CA 95134-1709
CY62137EV30
MoBL
[1]
®
) in portable
through
0
) is written into the location
15
through A ).
0 16
. If Byte High Enable (BHE) is
7
to I/O . See
8 15
7
15
BHE
WE
CE
OE
BLE
• 408-943-2600
Revised February 14, 2006
®
0
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