Cpu Feature; Dram Configuration - AMD SB700 User Manual

3-11-1 CPU Feature

Virtualization
AMD K8 Cool & Quiet Control
TLB Check
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
3-11-2

DRAM Configuration

DRAM Latency(tcl)
RAS to CAS R/W Delay (Trtc)
Row precharge Time(Trp)
Minimum RAS Active Time(Tras)
DRAM Command Rate
CKE base Power dowe mode
CKE BASED Powerdown
Memclock tri-slating
Memclock Hole Remapping
Auto optimize Bottom10
DDRII Timing Item
Refresh Mode select
RAS to RAS Delay(Trrd)
Precharge Time(Trtp)
Idle Cycle Limit
Write Recovery Time(Twr)
TwTr Command Delay
Trfc 0 for DIMM1
* Trfc 1 for DIMM 1
* Trfc 2 for DIMM 2
* Trfc 2 for DIMM 3
Trfc 2 for DIMM 4
Read to write Delay tRTW
Read/Write Queue Bypass
Queue Bypass Max
Max Asynchronous Latency
Read Delay Trd
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
CAS # Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: Auto,3, 4 and 5.
RAS-to-CAS Delay
Phoenix – AwardBIOS CMOS Setup Utility
CPU Feature
Enabled
Disabled
Enabled
F6:Fail-safe Defaults
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Configuration
F6:Optimized Defaults
Menu Level >
F7:Optimized Defaults
Auto
Auto
Auto
Auto
2T
Disabled
per channel
Disabled
Enabled
Enabled
Disabled
Auto
5 clocks
3T or 5T
Auto
6 bus clocks
3 bus clock
75ns
75ns
75ns
Menu Level >>
75ns
75ns
Auto
Auto
Auto
Auto
Auto
F7:Standard Defaults
35
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