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Circuit Description
3. Transmitter System
3-1. Mic Amplifier
There are two micrphone inputs, J1004 (front) and J1006
(D-Sub). Each microphone inputs has it's own amplifier.
Which micrphone is selected is controlled by the CPU and
in addition, the amplified AF signal is selected with Flat-
AF selection switch Q1004 (BU4053BCFV). Mic Gain is
adjusted with Mic gain VR Q1014 (M62364PF), and Pre
Enphasis and Mic Mute Q1044 (BU4066BCFV) are passed
at FLAT-AF OFF. And, the option use is selected with OPT
selection switch Q1044 (BU4066BCFV) by the control
from CPU. The selected signal enters maximum devia-
tion adjustment volume Q1014 (M62364FP) after it goes
out of Buffer Amp Q1072 (AK2342B). The adjusted low
frequency signal ingredient is amplified by Q1046
(LM2902PW) added modulation terminal of TCXO
(X1002) the FM modulation is made by reference oscilla-
tor. The high frequency signal ingredient level is adjusted
by volume control Q1014 (M62364FP) to make frequency
balance between low frequency. After that, the signal is
delievered to the tranmsit carrier by modulator D1023
(HVC300A).
3-2. Drive and Final amplifier
The modulated signal from the VCO Q1031 (2SK508) is
buffered by Q1027 (2SC5226) and amplified by Q1015
(2SC3357). The low-level transmit signal is then applied
to the Power Module Q1009 (RA60H4452M1) for final am-
plification up to 50 watts output power. The transmit sig-
nal then passes through a low-pass filter to suppress har-
monic spurious radiation before delivery to the antenna.
3-3. Automatic Transmit Power Control
The output power of Power Module is detected by CM
coupler, and is detected by D1007 and D1008 (both
HSM88AS) and is inputted to comparator Q1048
(LM2902PW). The comparetor compares two different
voltages and makes output power stable by controlling
the bias voltage of the power module. There are 3 levels
of output power (Hi, Mid and Lo) which is switched by
the voltage of Q1014-CH1 (M62364FP).
3-4. PLL Frequency Synthesizer
The frequency synthesizer consists of PLL IC Q1054
(ADF4111BRU) VCO, TCXO (X1002) and buffer ampli-
fier. The output frequency from TCXO is 16.8 MHz and
the tolerance is ±2.5 ppm (in the temperature range -30 to
+60 degrees).
F-2
3-4-1. VCO
While the radio is receiving, the RX oscillator Q1029
(2SK508) in the VCO generates a programmed frequency
between 382.35 and 444.35 MHz as 1st local signal. While
the radio is transmitting the TX oscillator Q1031 (2SK508)
in the VCO generates a frequency between 450 and 512
MHz. The output from oscillator is amplified by buffer
amplifier Q1027 (2SC5226) and becomes the output of
the VCO. The output from VCO is divided one is ampli-
fied by Q1024 (2SC5226) and feed back to pin 6 of the
PLL IC Q1054 (ADF4111BRU). The other is amplified in
Q1023 (2SC5226) and in case of the reception it is put
into the mixer as the 1st local signal through D1020
(DAN222) in transmission it is amplified in Q1027
(2SC5226) and more amplified in Q1023 (2SC5226)
through D1022 (DAN222) and it is put the input terminal
of the Power Module Q1009.
3-4-2. VCV CNTL
Tuning voltage (VCV) of the VCO expands the lock range
of VCO by controlling the of varactor diode voltage and
the control voltage from PLL IC Q1054 (ADF4111BRU).
Control voltage is added to the varactor diode after con-
verted to D/A converter Q1014 (M62364FP).
3-4-3. PLL
The PLL IC Q1054 (ADF4111BRU) consists of reference
divider, main divider, phase detector, charge pumps and
Pulse Swallow Frequency Synthesis. The reference fre-
quency from TCXO is inputted to pin 8 of PLL IC Q1054
(ADF4111BRU) and is divided by reference divider. This
IC is decimal point dividing PLL IC Q1054 (ADF4111BRU)
and the dividing ratio becomes 1/8 of usual PLL frequency
step. Therefore, the output of reference divider is 8 times
of frequencies of the channel step. For example when the
channel stepping is 5 kHz, the output of reference divider
becomes 40 kHz. On the other hand, inputted feed back
signal to pin 6 of PLL IC Q1054 (ADF4111BRU) from VCO
is divided with the dividing ratio which becomes same
frequency as the output of reference divider. These two
signals are compared by phase detector, a phase pulse is
generated. The phase difference pulse and the pulse from
fractional accumulator pass through the charge pumps and
LPF. This becomes the DC voltage (VCV) to control the
VCO. The oscillation frequency of VCO is locked by the
control of this DC voltage. The PLL serial data from CPU
Q1604 (LC87F5KP6A) is sent with three lines of SDO (pin
20), SCK (pin 22) and PSTB (pin 44). The lock condition of
PLL is output from the UL (pin 14) terminal and UL be-
comes "H" at the time of the lock condition and becomes
"L" at the time of the unlocked condition. The CPU Q1604
(LC87F5KP6A) always watches over the UL condition, and
when it becomes "L" unlocked condition, the CPU Q1604
(LC87F5KP6A) prohibits transmitting and receiving.
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