Second Stage Bootloader; Application Startup - Espressif ESP32-S2 Programming Manual

Chapter 4. API Guides
1. Reset from deep sleep: if the value in RTC_CNTL_STORE6_REG is non-zero, and CRC value of RTC mem-
ory in RTC_CNTL_STORE7_REG is valid, use RTC_CNTL_STORE6_REG as an entry point address and
jump immediately to it. If RTC_CNTL_STORE6_REG is zero, or RTC_CNTL_STORE7_REG contains in-
valid CRC, or once the code called via RTC_CNTL_STORE6_REG returns, proceed with boot as if it was a
power-on reset. Note: to run customized code at this point, a deep sleep stub mechanism is provided. Please
see deep sleep documentation for this.
2. For power-on reset, software SOC reset, and watchdog SOC reset: check the GPIO_STRAP_REG register
if a custom boot mode (such as UART Download Mode) is requested. If this is the case, this custom loader
mode is executed from ROM. Otherwise, proceed with boot as if it was due to software CPU reset. Consult
ESP32-S2 datasheet for a description of SoC boot modes and how to execute them.
3. For software CPU reset and watchdog CPU reset: configure SPI flash based on EFUSE values, and attempt to
load the code from flash. This step is described in more detail in the next paragraphs.
Note: During normal boot modes the RTC watchdog is enabled when this happens, so if the process is interrupted
or stalled then the watchdog will reset the SOC automatically and repeat the boot process. This may cause the SoC
to strap into a new boot mode, if the strapping GPIOs have changed.
Second stage bootloader binary image is loaded from flash starting at address 0x1000. The 4 kB sector of flash before
this address is unused.

4.2.2 Second stage bootloader

In ESP-IDF, the binary image which resides at offset 0x1000 in flash is the second stage bootloader. Second stage
bootloader source code is available in
in ESP-IDF to add flexibility to flash layout (using partition tables), and allow for various flows associated with flash
encryption, secure boot, and over-the-air updates (OTA) to take place.
When the first stage bootloader is finished checking and loading the second stage bootloader, it jumps to the second
stage bootloader entry point found in the binary image header.
Second stage bootloader reads the partition table found by default at offset 0x8000
tables documentation for more information. The bootloader finds factory and OTA app partitions. If OTA app
partitions are found in the partition table, the bootloader consults the otadata partition to determine which one
should be booted. See Over The Air Updates (OTA)
For a full description of the configuration options available for the ESP-IDF bootloader, see Bootloader.
For the selected partition, second stage bootloader reads the binary image from flash one segment at a time:
• For segments with load addresses in internal
copied from flash to the load address.
• For segments which have load addresses in
regions, the flash MMU is configured to provide the correct mapping from the flash to the load address.
Once all segments are processed - meaning code is loaded and flash MMU is set up, second stage bootloader verifies
the integrity of the application and then jumps to the application entry point found in the binary image header.

4.2.3 Application startup

Application startup covers everything that happens after the app starts executing and before the app_main function
starts running inside the main task. This is split into three stages:
• Port initialization of hardware and basic C runtime environment.
• System initialization of software services and FreeRTOS.
• Running the main task and calling app_main.
Espressif Systems
components/bootloader directory of ESP-IDF. Second stage bootloader is used
for more information.
IRAM (Instruction RAM)
DROM (data stored in Flash)
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(configurable value). See
or DRAM (Data RAM), the contents are
or IROM (code executed from Flash)
partition
Release v4.4