Microchip Technology MPLAB ICD 5 User Manual page 90

Figure 10-7. RJ-45 Socket to RJ-11 Connector Pinout
Pin
1
2
3
4
5
6
7
8
10.6.2 Standard Communication
The main interface to the target processor is via standard communication. It contains the
connections to the high voltage (V
for programming and connecting with the target devices.
The V high-voltage lines can produce a variable voltage that can swing from 0-14V to satisfy the
PP
voltage requirements of the specific emulation processor.
The V sense connection draws very little current from the target processor. The actual power
DD
comes from the MPLAB ICD 5 In-Circuit Debugger system, as the V
reference only to track the target voltage. The V
The clock and data connections are interfaces with the following characteristics:
• Clock and data signals are in high-impedance mode (even when no power is applied to the
MPLAB ICD 5 In-Circuit Debugger system).
• Clock and data signals are protected from high voltages caused by faulty target systems, or
improper connections.
• Clock and data signals are protected from high current caused from electrical shorts in faulty
target systems.
RJ-45 Function
TMS EJTAG Test Mode Select
Reserved
PGC (ICSPCLK) Standard Com
Clock/TCK (JTAG Test
Clock)
PGD (ICSPDAT) Standard Com
Data/TDO (JTAG Test
Data Output)
GND Ground
V _TGT Power on target
DD
V Power
PP
TDI JTAG Test Data Input
), V sense lines, as well as clock and data connections required
PP DD
User Guide
© 2023 Microchip Technology Inc. and its subsidiaries
Pin
1
2
3
4
5
6
sense line is used as a
DD
connection is isolated with an optical switch.
DD
Hardware Specification
RJ-11
PGC (ICSPCLK)
PGD (ICSPDAT)
GND
V _TGT
DD
V
PP
DS-50003529B - 90