Analog Devices EVAL-ADMV8052 User Manual page 7

EVAL-ADMV8052 User Guide
Label Function
Band 1 Coefficients: define the interpolation coefficients for Band 1.
Band 2 Coefficients: define the interpolation coefficients for Band 2.
Band 3 Coefficients: define the interpolation coefficients for Band 3.
Summary: click this button to review the settings for the initial setup.
Apply: click this button to apply the settings to the chip. Note that clicking Apply Changes (J1) does not update the changes in
this section. In addition, at startup, the main diagram user controls cannot be updated until the Apply button is clicked at least once.
Restore Software Defaults: click this button to zero out the CONFIGURATION section prior to loading a different .csv file.
B Use the SFL Settings section to configure the SPI fast latch settings on the chip when in the SFL mode. Refer to the
data sheet for more information regarding the internal state machine and SFL mode functionality. This section includes the following:
FAST_LATCH_STATE: this value is the next state of the internal state machine pointer (read only).
FAST_LATCH_START: this value determines the start location within the internal state machine.
FAST_LATCH_STOP: this value determines the stop location within the internal state machine.
FAST_LATCH_DIRECTION: this bit determines the direction that the internal state machine advances for each rising edge of
the CS pin when in SFL mode.
C The Status section includes the following:
Mode: when the SFL pin is low, the mode is SPI Write. When the SFL pin is high, the mode is SPI Fast Latch, and the chip uses
the LUT.
CSB_AUX Count: when in SFL mode, this field displays the number of times the
Message: upon entering SFL mode, the Message field displays Waiting for CSB. Once the CSB_AUX pin is toggled, the
Message field displays the current LUT number followed by the next LUT number.
D The displayed block diagram section shows the position of the switch and capacitor codes for each filter band within the chip.
While in SPI Write mode, any changes to the WRx registers automatically trigger a read operation of the READBACK registers,
so that this section always reflects the actual hardware.
E The Filter Settings section shows several controls for configuring each filter band in the chip. Depending upon if
INTERPOLATE is enabled, various controls can be visible.
When INTERPOLATE is enabled (as shown in Figure 7), the following controls are visible:
Band Selection: this numeric up and down box (0 to 3) is used to set the desired filter band. A value of 0 corresponds to the
bypass configuration, and all other values correspond to the filter band number.
FC_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired center frequency value. Note that this is a
unitless quantity, where a 0 corresponds to the lowest center frequency within a particular band, and 255 corresponds to the
highest center frequency within a particular band.
Requested FC: enter in a requested center frequency in this text box. The value entered is used to select the desired band of
operation and compute the closest FC_LOAD Value for that frequency of operation.
Anticipated FC: this text box is an estimation of the operating center frequency based upon the FC_LOAD Value.
Switch Set: this check box determines if the input and output switches change.
INTERPOLATE: this check box enables the interpolation functionality on the chip.
TRACK: this check box enables filter tracking, whereby when the capacitor codes of one filter are changed, the other two non-
selected filter capacitor codes are also set to the same values.
When INTERPOLATE is disable (not shown in Figure 7), the following controls are visible:
Band Selection: this numeric up and down box (0 to 3) is used to set the desired filter band. A value of 0 corresponds to the
bypass configuration, and all other values correspond to the filter band number.
FC_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired center frequency capacitor code.
BW_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired bandwidth capacitor code.
MATCH_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired input and output match capacitor code.
Switch Set: this check box determines if the input and output switches change.
INTERPOLATE: this check box enables the interpolation functionality on the chip.
TRACK: this check box enables filter tracking, whereby when the capacitor codes of one filter are changed, the other two non-
selected filter capacitor codes are also set to the same values.
READBACK Values --> Filter Settings: this button is available when interpolation is disabled. Click this button to populate the
read back values from the hardware into the FC_LOAD, BW_LOAD, and MATCH_LOAD values.
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SDP-S logic pin, CSB_AUX, was toggled.
UG-1951
ADMV8052